U.S. patent application number 10/760292 was filed with the patent office on 2004-08-05 for process for manufacturing semiconductor integrated circuit device.
Invention is credited to Hinode, Kenji, Homma, Yoshio, Imai, Toshinori, Kondo, Seiichi, Noguchi, Junji, Ohashi, Naofumi, Owada, Nobuo, Yamaguchi, Hizuru.
Application Number | 20040152298 10/760292 |
Document ID | / |
Family ID | 16579782 |
Filed Date | 2004-08-05 |
United States Patent
Application |
20040152298 |
Kind Code |
A1 |
Ohashi, Naofumi ; et
al. |
August 5, 2004 |
Process for manufacturing semiconductor integrated circuit
device
Abstract
In order to provide an anticorrosive technique for metal wirings
formed by a chemical mechanical polishing (CMP) method, a process
for manufacturing a semiconductor integrated circuit device
according to the invention comprises the steps of: forming a metal
layer of Cu (or a Cu alloy containing Cu as a main component) over
the major face of a wafer and then planarizing the metal layer by a
chemical mechanical polishing (CMP) method to form metal wirings;
anticorroding the planarized major face of the wafer to form a
hydrophobic protective film over the surfaces of the metal wirings;
immersing the anticorroded major face of the wafer or keeping the
same in a wet state so that it may not become dry; and
post-cleaning the major face, kept in the wet state, of the
wafer.
Inventors: |
Ohashi, Naofumi;
(Hannou-shi, JP) ; Noguchi, Junji; (Tokyo, JP)
; Imai, Toshinori; (Tokyo, JP) ; Yamaguchi,
Hizuru; (Tokyo, JP) ; Owada, Nobuo; (Tokyo,
JP) ; Hinode, Kenji; (Tokyo, JP) ; Homma,
Yoshio; (Tokyo, JP) ; Kondo, Seiichi; (Tokyo,
JP) |
Correspondence
Address: |
ANTONELLI, TERRY, STOUT & KRAUS, LLP
1300 NORTH SEVENTEENTH STREET
SUITE 1800
ARLINGTON
VA
22209-9889
US
|
Family ID: |
16579782 |
Appl. No.: |
10/760292 |
Filed: |
January 21, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10760292 |
Jan 21, 2004 |
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10369716 |
Feb 21, 2003 |
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10369716 |
Feb 21, 2003 |
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10222848 |
Aug 19, 2002 |
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6531400 |
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10222848 |
Aug 19, 2002 |
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10050563 |
Jan 18, 2002 |
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6646629 |
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10050563 |
Jan 18, 2002 |
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09356707 |
Jul 20, 1999 |
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6376345 |
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Current U.S.
Class: |
438/633 ;
257/E21.304; 257/E21.582; 438/687; 438/906 |
Current CPC
Class: |
H01L 21/76838 20130101;
H01L 21/02074 20130101; H01L 21/0209 20130101; H01L 21/7684
20130101; Y10S 438/906 20130101; H01L 21/3212 20130101; G09G 5/399
20130101 |
Class at
Publication: |
438/633 ;
438/687; 438/906 |
International
Class: |
H01L 021/44; H01L
021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 24, 1998 |
JP |
10-209857 |
Claims
What is claimed is:
1. A process for manufacturing a semiconductor integrated circuit
device, comprising the steps of: (a) forming an insulating film
over a first major surface of a wafer; (b) forming a wiring groove
in the insulating film by patterning the insulating film; (c)
forming a metal layer including copper as its principal component,
over the insulating film and in the wiring groove; (d) removing the
metal layer outside the wiring groove by a chemical mechanical
polishing method so as to leave the metal layer in the wiring
groove; (e) after step (d), performing pre-cleaning of the first
major surface of the wafer by rubbing the first major surface of
the wafer with a polishing pad provided with a liquid chemical or
cleaning water; (f) after step (e), transferring the wafer to a
post cleaning portion of a single wafer processing apparatus; (g)
after step (f), performing scrub or brush cleaning of the first
major surface of the wafer with a liquid chemical; and then (h)
making the first major surface of the wafer dry, wherein steps (d)
to (h) are performed in the single wafer processing apparatus,
which has light shielding structure keeping an illuminance of the
inside of the apparatus at 100 lux or less, and step (f) includes
the substep of: (i) keeping the first major surface of the wafer
wet with a water shower.
Description
[0001] This application is a Continuation application of
application Ser. No. 10/369,716, filed Feb. 21, 2003, which is a
Continuation Application of Ser. No. 10/222,848, filed Aug. 19,
2002, and issued on Mar. 11, 2003, a U.S. Pat. No. 6,531,400, which
is a Continuation Application of Ser. No. 10/050,563 filed 18 Jan.
2002, and issued 1 Oct. 2002 as U.S. Pat. No. 6,458,674, which is a
Continuation Application of Ser. No. 09/356,707 filed 20 Jul. 1999
and issued 23 Apr. 2002 as U.S. Pat. No. 6,376,345 B1, the contents
of Ser. No. 09/356,707 being incorporated herein by reference in
their entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a technique for
manufacturing a semiconductor integrated circuit device and, more
particularly, to a technique which is effective in achieving
anticorrosion of metal wirings formed by a chemical mechanical
polishing (CMP) method.
[0003] Japanese Patent Laid-open No. 135192/1995 (hereinafter
referred to as "Hayakawa") has disclosed a post-polishing method
which makes it possible to lower the particle level after polishing
treatment on a wafer by performing, without drying the wafer, a
series of steps including chemical mechanical polishing, followed
by wafer inverting standby, physical cleaning, chemical-cleaning
(or spin-cleaning) and rinsing treatments. In the polishing
apparatus to be used in this process, a wafer mounting portion in
the polishing unit is made to have a construction which is capable
of keeping the wafer wet, and an inter-unit wet conveying mechanism
is used for conveying wafers among a polishing unit, a cleaning
unit and a rinsing/drying unit, whereas an in-unit wet conveying
mechanism is used for conveying wafers between the individual
cleaning chambers in the cleaning unit.
[0004] A CMP apparatus for an oxide film comprising a wafer feeding
portion, a polishing portion, a wafer extracting portion and a
dress unit is disclosed on pp. 53 to 55 of Electronic Materials,
issued in May, 1996, by the Association of Industrial Researches
(hereinafter referred to as "Ohmura et al."). In this apparatus,
the wafer is conveyed by a conveyor robot from a load cassette to a
polishing portion and is polished. The polished wafer is then
scrub-cleaned on its front and back sides with pure water, is
stocked in an unload cassette, and thereafter, is stocked in
water.
[0005] On pp. 62 to 65 of Electronic Materials, issued in May, 1996
(hereinafter referred to as "Tsujimura et al."), there is disclosed
a technique for the transfer of a wafer in an underwater stock from
a polishing step to a post-cleaning treatment (aiming at removing
undesired particles such as abrasive grains introduced at the
polishing time from the wafer surface and generally conducted
before the wafer surface is naturally dried).
[0006] On pp. 33 to 35 of Electronic Materials, issued in May, 1996
(hereinafter referred to as "Hirakura"), there is disclosed a CMP
apparatus comprising a polishing disc (or platen) for performing a
primary polishing treatment, a polishing disc for performing a
second polishing (or buff polishing) treatment, a cleaning station
for cleaning the polished wafer with water and a brush, and an
unloader for stocking the wafer in a submerged state.
[0007] Japanese Patent Laid-open No. 64594/1996 (hereinafter
referred to as "Shibuki") has disclosed a metal CMP process using a
slurry containing an anticorrosive agent, such as BTA, so as to
prevent corrosion of the metal, which might otherwise occur in the
metal CMP process.
SUMMARY OF THE INVENTION
[0008] Hitherto, the metal wirings of an LSI have been formed by a
process of depositing a metal film, such as an aluminum (Al) alloy
film or a tungsten (W) film, over a silicon substrate (or wafer)
using a sputtering method and then patterning the metal film by a
dry etching method using a photoresist film as a mask.
[0009] As the integration of an LSI has become higher in recent
years, however, the aforementioned process has become more critical
with respect to the wiring resistance due to the finer thickness of
the wiring width required by the high integration, producing a
higher factor to deteriorate the performance of a logic LSI which
requires an especially high performance. Therefore, recently
attention has been given to wirings using copper (Cu), which has an
electric resistance of about one half of that of Al alloy and an
electromigration resistance higher by about one figure than that of
Al alloy.
[0010] However, Cu is so low in the vapor pressure of its halide as
to make it difficult to form the wirings using the dry etching
treatment of the related art. Because of this difficulty, there has
been introduced a wiring forming process (the so-called damascene
process) by which grooves are formed in advance in the insulating
film over the silicon substrate, and the Cu film is deposited over
the insulating film including the insides of the grooves and any
unnecessary Cu film outside the grooves is then polished back by
chemical mechanical polishing (CMP) while leaving the Cu film in
the grooves.
[0011] When the Cu film is polished by the CMP method, however, a
portion of the Cu may be eluted by the action of an oxidizing agent
added to the polishing slurry, so that a portion of the Cu wirings
is corroded, thereby bringing about open defects or short-circuit
defects.
[0012] This corrosion of the Cu wirings characteristically occurs
in the Cu wirings which are connected with the p-type diffusion
layer of a pn junction (e.g., a diffusion resistance element, the
source and drain of an MOS transistor, or the collector, base and
emitter of a bipolar transistor) formed in the silicon substrate.
Further, when the metal wirings are formed by polishing another
metal material (e.g., W or an Al alloy) by the CMP method or when
metal materials (or plugs) are buried in through holes for
connecting upper and lower wirings, although not so serious as in
the case of Cu wirings, corrosion may be caused for the
aforementioned reasons if those metal wirings or plugs are
connected with the pn junction.
[0013] FIG. 14(a) is a model diagram illustrating an electromotive
force generating mechanism of the pn junction; FIG. 14(b) is a
graph illustrating the I-V characteristics of the pn junction at a
light irradiation time and at a dark time; and FIG. 15 is a model
diagram illustrating a corrosion occurring mechanism of the Cu
wirings.
[0014] When light comes into the pn junction formed in the silicon
substrate, as shown in FIG. 14(a), an external voltage (up to 0.6
V) at +on the p-side and at - on the n-side is generated by the
photovoltaic effect of silicon, so that the i-V characteristics of
the pn junction are shifted, as illustrated in FIG. 14(b). As a
result, a short-circuit current flows, as illustrated in FIG. 15,
through a closed circuit which is formed of a Cu wiring connected
with the p-side (or +side) of the pn junction--the pn junction--the
Cu wiring connected with the n-side (or - side) of the pn
junction--the polishing slurry which has stuck to the wafer
surface, so that the Cu.sup.2+ ions are dissociated from the
surface of the Cu wiring connected with the p-side (or +side) of
the pn junction, thereby to cause electrochemical corrosion (or
electrolytic corrosion).
[0015] FIG. 16 is a graph showing relations, which occur at a time
a voltage is applied, between a slurry concentration (%) and a Cu
etching (eluting) rate. For a slurry concentration of 100%, as seen
from FIG. 16, the eluting rate of Cu is relatively low, but
abruptly rises when the polishing slurry is diluted to some extent
with water. It can be said from the foregoing discussion that, when
light comes in a pn junction in a case where some of the polishing
slurry or its aqueous solution has stuck to the surface of the
silicon wafer, the elution of Cu grows prominent to cause
electrolytic corrosion. Concretely, when light comes in the surface
of the wafer either in the course of conveyance from the polishing
step to the post-cleaning step or at a standby time, electrolytic
corrosion occurs in the Cu wirings connected with the p-type
diffusion layer of the pn junction.
[0016] An object of the present invention is to provide a technique
which is capable of preventing the corrosion of metal wirings
formed by using the CMP method.
[0017] This and other objects and various novel features of the
invention will become apparent from the following description when
taken in conjunction with the accompanying drawings.
[0018] A representative aspect of the invention to be disclosed
herein will be briefly described in the following.
[0019] A process for manufacturing a semiconductor integrated
circuit device according to the invention comprises the steps of:
forming metal wirings by forming a metal layer (or conductive
layer) over the major face of a wafer and then by planarizing the
metal layer by a chemical mechanical polishing (CMP) method. The
so-called "CMP technique" for planarizing the metal layer includes
one technique using a standard polishing pad and floating abrasive
grains, one technique using stationary abrasive grains, an
intermediate technique and the so-called "abrasion grain free CMP"
technique using a slurry containing substantially no abrasive
grains. Further, the planarizing treatment includes not only a
wiring burying technique, such as used in the damascene or dual
damascene processes, but also the metal CMP technique for burying
metal plugs. The method further includes the steps of forming a
hydrophobic protective film over the surface of the metal wirings
by pre-cleaning the planarized major face of the wafer just after
the polishing treatment with a view to clearing the wafer surface
of an undesired chemical, such as the oxidizing agent at the
polishing time, and by anticorroding the pre-cleaned major face.
The anticorroding treatment may be the cleaning step itself or its
sub-step having a main object to form a hydrophobic protective film
over the surface of the metal. Just after this, the anticorroding
treatment is performed simultaneously with the cleaning treatment.
The "just after" indicator means "before the wafer surface is dried
after the polishing treatment" or "before the metal is corroded
with a residual oxidizing agent". By this anticorroding treatment,
it is possible to prevent the electrochemical corrosion of the
metal wirings to a considerable extent. The term "electrochemical
corrosion" refers to the corrosion of the metal accompanied by the
battery action of the formed closed circuit which includes the
metal, the pn junction, the metal and the polishing liquid
component on the pattern of the wafer. The method further comprises
the steps of immersing the anticorroded major face of the wafer or
keeping it in a wet state so that it may not become dry. The term
"wet stock" generally means "keeping or transfer" while preventing
a dry state by immersing the wafer in pure water or the like, by
feeding a pure water shower or by keeping the wafer in a saturated
vapor atmosphere. The method then provides the step of
post-cleaning the major face of the wafer which has been kept in
the wet state. The "post-cleaning" treatment is generally performed
before the surface becomes dry, with a view to clearing the wafer
surface of undesired particles, such as abrasive grains' introduced
at the polishing time. This cleaning treatment frequently involves
both a mechanical cleaning treatment, such as a scrub cleaning
treatment using a brush, and a weak etching treatment with a
chemical solution.
[0020] A summary of the features of the invention will be briefly
described as follows.
[0021] 1. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0022] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0023] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method;
[0024] (c) anticorroding the planarized first major face of the
wafer;
[0025] (d) immersing the anticorroded first major face of the wafer
in a liquid or keeping the same in a wet state so that it may not
become dry; and
[0026] (e) post-cleaning the first major face, kept in the wet
state, of the wafer.
[0027] 2. A process for manufacturing a semiconductor integrated
circuit device according to Item 1, wherein the anticorroding step
(c) includes the steps of: mechanically cleaning a polishing slurry
which has stuck to the first major face at the step (b); and
forming a protective film over the surface portion of the metal
layer of the first major face, from which the polishing slurry has
been removed, of the wafer.
[0028] 3. A process for manufacturing a semiconductor integrated
circuit device according to Item 2, wherein the protective film is
a hydrophobic protective film.
[0029] 4. A process for manufacturing a semiconductor integrated
circuit 0.5 device according to any one of Items 1 to 3, wherein
the post-cleaning step (e) includes the step of mechanically
cleaning the foreign particles which have stuck to the first major
face of the wafer at the step (b).
[0030] 5. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0031] (a) forming a metal layer whose main component is copper,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0032] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method;
[0033] (c) anticorroding the planarized first major face of the
wafer;
[0034] (d) immersing the anticorroded first major face of the wafer
in a liquid or keeping the same in a wet state so that it may not
become dry; and
[0035] (e) post-cleaning the first major face, kept in the wet
state, of the wafer.
[0036] 6. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0037] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0038] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method;
[0039] (c) anticorroding the planarized first major face of the
wafer; and
[0040] (d) immersing the anticorroded first major face of the wafer
in a liquid or keeping the same in a wet state at a shaded wafer
stocking portion so that it may not become dry.
[0041] 7. A process for manufacturing a semiconductor integrated
circuit device according to Item 6, wherein the wafer stocking
portion is shaded to have an illuminance of 500 luxes or less.
[0042] 8. A process for manufacturing a semiconductor integrated
circuit device according to. Item 6, wherein the wafer stocking
portion is shaded to have an illuminance of 300 luxes or less.
[0043] 9. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0044] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0045] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method; and
[0046] (c) drying the planarized first major face of the wafer just
after the planarizing step.
[0047] 10. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0048] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0049] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method; and
[0050] (c) post-cleaning the planarized first major face of the
wafer at a shaded post-cleaning portion.
[0051] 11. A process for manufacturing a semiconductor integrated
circuit device according to Item 10, wherein the post-cleaning step
(c) includes the step of removing a foreign particle by applying a
mechanical friction to the first major face of the wafer in the
presence of an alkaline or weakly alkaline chemical.
[0052] 12. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0053] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0054] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method;
[0055] (c) anticorroding the planarized first major face of the
wafer; and
[0056] (d) post-cleaning the anticorroded first major face of the
wafer.
[0057] 13. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0058] (a) forming a metal layer whose main component is copper,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0059] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method; and
[0060] (c) forming a hydrophobic protective film over the
planarized surface of the metal layer by anticorroding the
planarized first major face of the wafer.
[0061] 14. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0062] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0063] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing method
using a sheet treatment; and
[0064] (c) post-cleaning the planarized first major face of the
wafer at a shaded post-cleaning portion.
[0065] 15. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0066] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0067] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing method
using a sheet treatment;
[0068] (c) anticorroding the planarized first major face of the
wafer; and
[0069] (d) post-cleaning the anticorroded first major face of the
wafer.
[0070] 16. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0071] (a) forming a metal layer whose main component is a metal,
over a first major face of a Wafer having a pattern of a
semiconductor integrated circuit;
[0072] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method;
[0073] (c) anticorroding the planarized first major face of the
wafer; and
[0074] (d) immersing the anticorroded first major face of the wafer
in a liquid or keeping the same in a wet state at a shaded wafer
stocking portion, kept at a temperature as low as not to proceed an
electrochemical corrosion substantially, so that it may not become
dry.
[0075] 17. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0076] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0077] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing
method; and
[0078] (c) forming a protective film over the planarized surface of
the metal layer by anticorroding the planarized first major face of
the wafer.
[0079] 18. A process for manufacturing a semiconductor integrated
circuit device according to Item 17, the anticorroding step (c) is
conducted under such a condition that an oxidizing agent having
stuck to the first major face of the wafer at the step (b) does not
substantially act.
[0080] 19. A process for manufacturing a semiconductor integrated
circuit device according to Item 17 or 18, wherein the protective
film is a hydrophobic protective film.
[0081] 20. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0082] (a) forming a metal layer whose main component is a metal,
over a first major face of a wafer having a pattern of a
semiconductor integrated circuit;
[0083] (b) planarizing the first major face, having the formed
metal layer, of the wafer by a chemical mechanical polishing method
using a sheet treatment;
[0084] (c) anticorroding the planarized first major face of the
wafer;
[0085] (d) immersing the anticorroded first major face of the wafer
in a liquid or keeping the same in a wet state so that it may not
become dry; and
[0086] (e) post-cleaning the first major face, kept in the wet
state, of the wafer.
[0087] The summary of other invention will be briefly described by
itemizing it, as follows.
[0088] 21. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0089] (a) forming a plurality of semiconductor elements over the
major face of a semiconductor substrate;
[0090] (b) forming a metal layer over the plurality of
semiconductor elements through an insulating film;
[0091] (c) forming a plurality of metal wirings, electrically
connected with the plurality of semiconductor elements, by
planarizing the metal layer by a chemical mechanical polishing
method;
[0092] (d) anticorroding the surfaces of the metal wirings;
[0093] (e) immersing the anticorroded surfaces of the metal wirings
in a liquid or keeping the same in a wet state so that they may not
become dry; and
[0094] (f) post-cleaning the surfaces, kept in the wet state, of
the metal wirings.
[0095] 22. A process for manufacturing a semiconductor integrated
circuit device according to Item 21, wherein the anticorroding step
(d) includes the steps of: removing a polishing slurry, having
stuck to the surfaces of the metal wirings, by a mechanism cleaning
treatment; and forming a protective film over the surfaces, from
which the polishing slurry was removed, of the metal wirings.
[0096] 23. A process for manufacturing a semiconductor integrated
circuit device according to Item 22, wherein the protective film is
a hydrophobia protective film.
[0097] 24. A process for manufacturing a semiconductor integrated
circuit device according to any one of Items 21 and 23, wherein the
plurality of semiconductor elements have a pn junction, and the
plurality of metal wirings are partially electrically connected
with one of the pn junction whereas the remaining plurality of
metal wirings are electrically connected with the other of the pn
junction.
[0098] 25. A process for manufacturing a semiconductor integrated
circuit device according to any one of Items 21 to 24, wherein the
metal wirings include metal plugs.
[0099] 26. A process for manufacturing a semiconductor integrated
circuit device according to any one of Items 21 to 25, wherein the
metal wirings contain at least copper.
[0100] 27. A process for manufacturing a semiconductor integrated
circuit device according to any one of Items 21 to 26, wherein the
anticorroded surfaces of the metal wirings are dipped in a liquid
or kept in a wet state at a shaded wafer stocking portion, so that
they may not become dry.
[0101] 28. A process for manufacturing a semiconductor integrated
circuit device according to Item 27, wherein the wafer stocking
portion is shaded to have an illuminance of 500 luxes or less.
[0102] 29. A process for manufacturing a semiconductor integrated
circuit device according to Item 27, wherein the wafer stocking
portion is shaded to have an illuminance of 300 luxes or less.
[0103] 30. A process for manufacturing a semiconductor integrated
circuit device according to Item 27, wherein the wafer stocking
portion is shaded to have an illuminance of 100 luxes or less.
[0104] 31. A process for manufacturing a semiconductor integrated
circuit device, comprising the steps of:
[0105] (a) forming a plurality of semiconductor elements over the
major face of a semiconductor substrate;
[0106] (b) forming a metal layer over the plurality of
semiconductor elements through an insulating film;
[0107] (c) forming a plurality of metal wirings, electrically
connected with the plurality of semiconductor elements, by
planarizing the metal layer by a chemical mechanical polishing
method; and
[0108] (d) post-cleaning the planarized surfaces of the metal
wirings, after shaded, at a post-cleaning portion.
[0109] 32. A process for manufacturing a semiconductor integrated
circuit device according to Item 31, wherein the metal wirings
contain at least copper.
[0110] 33. A process for manufacturing a semiconductor integrated
circuit device comprising the steps of:
[0111] (a) forming a plurality of semiconductor elements over the
major face of a semiconductor substrate;
[0112] (b) forming a metal layer over the plurality of
semiconductor elements through an insulating film;
[0113] (c) forming a plurality of metal wirings, electrically
connected with the plurality of semiconductor elements, by
planarizing the metal layer by a chemical mechanical polishing
method; and
[0114] (d) drying the planarized surfaces of the metal wirings just
after the planarizing treatment.
[0115] 34. A process for manufacturing a semiconductor integrated
circuit device according to Item 33, wherein the metal wirings
contain at least copper.
BRIEF DESCRIPTION OF THE DRAWINGS
[0116] FIG. 1 is a sectional view of an essential portion of a
wafer and shows a stage in the process for manufacturing an MOS-LSI
according to Embodiment 1 of the invention;
[0117] FIG. 2 is a sectional view of the essential portion of the
wafer and shows a further stage in the MOS-LSI manufacturing
process according to Embodiment 1 of the invention;
[0118] FIG. 3 is a sectional view of the essential portion of the
wafer and shows a further stage in the MOS-LSI manufacturing
process according to Embodiment 1 of the invention;
[0119] FIG. 4 is a sectional view of the essential portion of the
wafer and shows a further stage in the MOS-LSI manufacturing
process according to Embodiment 1 of the invention;
[0120] FIG. 5 is a sectional view of the essential portion of the
wafer and shows a further stage in the MOS-LSI manufacturing
process according to Embodiment 1 of the invention;
[0121] FIG. 6 is a sectional view of the essential portion of the
wafer and shows a further stage in the MOS-LSI manufacturing
process according to Embodiment 1 of the invention;
[0122] FIG. 7 is a sectional view of the essential portion of the
wafer and shows a further stage in the MOS-LSI manufacturing
process according to Embodiment 1 of the invention;
[0123] FIG. 8 is a diagram showing the overall configuration of a
CMP apparatus to be used in Embodiment 1 of the invention;
[0124] FIG. 9 is a schematic diagram showing a polishing portion of
the CMP apparatus to be used in Embodiment 1 of the invention;
[0125] FIG. 10 is a sectional view of the essential portion of the
wafer formed by the MOS-LSI manufacturing process according to
Embodiment 1 of the invention;
[0126] FIG. 11 is a sectional view of the essential portion of the
wafer formed by the MOS-LSI manufacturing process according to
Embodiment 1 of the invention;
[0127] FIG. 12 is a diagram of the overall configuration of a CMP
apparatus to be used in Embodiment 2 of the invention;
[0128] FIG. 13 is a diagram of the overall configuration of a CMP
apparatus to be used in Embodiment 3 of the invention;
[0129] FIG. 14(a) is a model diagram showing an electromotive force
generating mechanism of a pn junction, and FIG. 14(b) is a graph
illustrating I-V characteristics of the pn junction at a light
irradiation time and at a dark time;
[0130] FIG. 15 is a model diagram showing a corrosion generating
mechanism of a Cu wiring; and
[0131] FIG. 16 is a graph showing relations, which occur at a time
voltage is applied, between a slurry concentration and a Cu etching
(eluting) rate.
DETAILED DESCRIPTION OF THE INVENTION
[0132] The invention will be described in detail in connection with
various embodiments with reference to the accompanying drawings.
Here, throughout all the drawings for explaining the embodiments,
members having identical functions will be designated by identical
reference numerals, and their repeated description will be omitted.
Further, in the following embodiments, the descriptions of the
identical or similar portions will not be repeated as a rule,
unless especially necessary to an understanding of the
invention.
[0133] Moreover, the following embodiments will be described
separately in a plurality of sections or as different modes of the
embodiment, if necessary for the sake of convenience. Unless
explicitly specified, however, the sections or modes of an
embodiment are not to be considered as unrelated to each other, but
one may be related to the other in a partial or whole modification
or in a detailed or supplementary explanation. Further, when a
reference is made to the number (including the number, numerical
value, amount and range) of elements in the following embodiments,
no limitation should be placed on the specific number, unless
explicitly specified to be so or clarified in principle, but the
number may be more or less than that specific number. In the
following embodiments, moreover, it is needless to say that the
constituent elements (including process steps) are not necessarily
essential unless explicitly specified to be so or apparently
essential in principle.
[0134] Likewise, in the following embodiments, the shapes or
positional relationships of the constituent elements should
include, when referred to, those substantially approximating or
resembling the shapes unless explicitly specified or unless
otherwise apparent. This will apply also to the aforementioned
numerical value and range.
[0135] Further, the following terminologies as used in this
specification are generally interpreted to have the following
meanings with reference to the descriptions of the various features
described herein.
[0136] The term "metal CMP" generally refers to a planarization of
a surface made mainly of a metal, by chemical action of a polishing
liquid and a mechanical polishing treatment of the surface of a
wafer having a formed pattern. The metal CMP process includes the
use of not only floating abrasive grains, such as in damascene or
dual damascene processes, but also stationary abrasive grains, as
well as the so-called "abrasive grain-free CMP" process using a
slurry containing substantially no abrasive grains.
[0137] The term "just after" generally refers to "the metal CMP
step before the wafer surface is naturally dried after the
polishing treatment or before the metal is corroded with a residual
oxidizing agent".
[0138] The term "pre-cleaning" generally refers to the cleaning
treatment which is conducted just after the polishing treatment
with one object to clear the wafer surface of an undesired
chemical, such as the oxidizing agent, at the polishing time.
[0139] The term "corrosion preventing treatment" generally refers
to the treatment for forming an hydrophobic protective film on the
surface of the metal at a sub-step of the aforementioned
pre-cleaning.
[0140] The term "wetting treatment" generally refers to an
immersing in pure water, a feeding of a pure water shower or a
holding under a drying-preventing state in the saturated atmosphere
of the pure water.
[0141] The term "post-cleaning" generally refers to a cleaning
treatment which is generally conducted before the surface is
naturally dried, with one object being to clear the wafer surface
of undesired particles, such as the abrasive grains, at the
polishing time.
[0142] The term "electrochemical corrosion" generally refers to the
corrosion of the metal which forms a pattern on the wafer by the
battery action of the aforementioned metal and a closed circuit
formed of a pn junction, the metal and an abrasive liquid
component.
[0143] The term "shading" generally refers to an illuminance within
such a range that the electrochemical corrosion is not intensified
by light, and widely refers to a substantial darkening to an
illuminance of 1,000 luxes or less in the working region of an
ordinary wafer step. That is, it goes without saying that this
shading includes not only a shading of light from the environment
with a shading wall or the like, but also a darkening of the
illumination of the place itself where the apparatus is placed.
When an essential portion is to be exclusively shaded with a
shading wall or a shading film, an advantage is attained in that
the object can be achieved without lowering the workability in the
remaining portions. In this connection, the invention can generally
expect a considerable effect for an illuminance of 500 luxes or
less. Considering the heterogeneity of the flow of the wafer to be
treated in the mass production, however, an illuminance of 300
luxes or less is desired in the wetting treatment relating to the
CMP, i.e., after the CMP treatment portion to the drying step of
the post-cleaning step. Of these, further, an illuminance of 200
luxes or less is more desirable especially in corrosible, portions
(for the CMP, corrosion-preventing, pre-cleaning, wetting and
post-cleaning treatments). Moreover, in such a region in these CMP
related wetting portions which require no considerable illuminance
for the processing, a stable corrosion-preventing effect can be
ensured by setting the illuminance to 150 luxes or less, more
desirably to 100 luxes or less.
[0144] Further, when there is used an abrasive grain-free CMP (or
widely a CMP using a slurry containing 0.5 wt. % or less of
abrasive grains, as the abrasive grain concentration in the slurry
is ordinarily 0.1 wt. % or less. When more stable characteristics
are demanded, however, the concentration is desired to be 0.05 wt.
% or less.), since the polishing treatment is conducted mainly in
the metal corrosion region, it is considered that the necessity for
the shading is enhanced in order to suppress the electrochemical
corrosion by light.
[0145] It is also possible to use the abrasive grain-free CMP or a
corrosion preventing agent in another CMP treatment. In this case,
the rate of polishing the metal may become lower according to the
property of the slurry. In this case, the main polishing treatment
is executed as in the embodiment with the slurry containing
substantially no corrosion preventing agent, and the corrosion
preventing treatment is then executed at the subsidiary polishing
treatment step or at the corrosion preventing or cleaning step.
Then, the main polishing treatment can be executed under optimum
conditions. If the remaining conditions are satisfied, however, the
corrosion preventing treatment can be used together with the main
polishing treatment.
[0146] The term "mechanical cleaning treatment" generally refers to
cleaning which is conducted by rubbing the surface with a scrub
brush or the like. In the present specification, moreover, the term
"wafer" denotes not only a single-crystalline silicon wafer, but
also a silicon epitaxial wafer or one having one or a plurality of
epitaxial regions formed on an insulating substrate. The
"semiconductor integrated circuit device" contains not only those
formed over the aforementioned various wafers, but also electric or
electronic circuit devices formed over another substrate, such as a
TFT liquid crystal, except for an explicitly denied case.
[0147] [Embodiment 1]
[0148] A process for manufacturing an MOS-LSI according to one
embodiment of the invention will be described sequentially in steps
with reference to FIGS. 1 to 11. First of all, as shown in FIG. 1,
a semiconductor substrate (wafer) 1 of p-type single crystalline
silicon, for example, is prepared. An n-type well 2n, a p-type well
2p and a field oxide film 3 are formed over the major face of the
semiconductor substrate 1 by the well-known ion implantation and
selective oxidation (LOCOS) method, and the individual surfaces of
the n-type well 2n and the p-type well 2p are thermally oxidized to
form a gate oxide film 4.
[0149] Next, as shown in FIG. 2, gate electrodes 5 are formed over
the individual gate oxide films 4 of the n-type well 2n and the
p-type well 2p. After this, an n-channel MISFET (Qn) and a
p-channel MISFET (Qp) are formed by doping the p-type well 2p with
ions of an n-type-impurity (e.g., phosphor) to form a source and a
drain (or n-type semiconductor regions 6) and by doping n-type well
2n with ions of a p-type impurity (e.g., boron) to form a source
and a drain (or p-type semiconductor regions 7).
[0150] Next, as shown in FIG. 3, a silicon oxide film 8 is
deposited over the semiconductor substrate 1 by the CVD method and
is then dry-etched by using a photoresist film as a mask to form
contact holes 9 over the source and drain (or the n-type
semiconductor regions 6) of the n-channel MISFET (Qn) and contact
holes 10 over the source and drain (or the p-type semiconductor
regions 7) of the p-channel MISFET (Qp).
[0151] Next, as shown in FIG. 4, first-layer w wirings 11 to 16 are
formed over the silicon oxide film 8, and a first-layer interlayer
insulating film 17 is then formed by depositing a silicon oxide
film over those W wirings 11 to 16 by the CVD method. After this,
through holes 18 to 21 are formed in the interlayer insulating film
17 by the dry-etching method using a photoresist film as a mask.
The first-layer W wirings 11 to 16 are formed, for example, by
depositing a W film by the CVD method (or sputtering method) over
the silicon oxide film 8 including the inside of the contact holes
9 and 10, and then by patterning the W film by the dry-etching
method using a photoresist film as a mask.
[0152] Next, as shown in FIG. 5, plugs 22 are formed in the through
holes 18 to 21, and a silicon oxide film 23 is then deposited over
the interlayer insulating film 17 by the CVD method. After this,
grooves 24 to 26 are formed in the silicon oxide film 23 by the
dry-etching method using a photoresist film as a mask. The plugs 22
are formed by depositing a w film by the CVD method over the
interlayer insulating film 17 including the insides of the through
holes 18 to 21, and by etching back (or polishing by a
later-described CMP method) the W film.
[0153] Next, as shown in FIG. 6, a Cu film (or a Cu alloy film
containing Cu as a major component) 27 is deposited over the
silicon oxide film 23 including the insides of the grooves 24 to 26
by using a low-pressure long-distance sputtering method, for
example. Here, when the grooves 24 to 26 have such a large aspect
ratio that the sputtering method finds it difficult to bury the Cu
film 27 sufficiently therein, the semiconductor substrate 1 may be
thermally treated after the deposition of the Cu film 0.27 to cause
the Cu film 27 to reflow into the grooves 24 to 26. Alternatively,
the Cu film 27 may be formed by the CVD method or electric plating
method which is better in the step coverage than the sputter-reflow
method.
[0154] Next, as shown in FIG. 7, second-layer Cu wirings 28 to 30
are formed in the grooves 24 to 26 by polishing the aforementioned
Cu film 27 using the CMP method, as will be described in the
following, to planarize its surface. FIG. 8 is a schematic diagram
showing a sheet type CMP apparatus 100 to be used for polishing the
Cu film 27. This CMP apparatus 100 comprises: a loader 120 for
accommodating a plurality of wafers 1 each having the Cu film 27
formed on its surface; a polishing portion 130 for polishing and
planarizing the Cu film 27; an anticorroding portion 140 for making
the polished surface of the wafer 1 anticorrosive; an immersing
portion 150 for preventing the anticorroded wafer 1 from becoming
dry on its surface until it is post-cleaned; a post-cleaning
portion 160 for post-cleaning the anticorroded wafer 1; and an
unloader 170 for accommodating a plurality of post-cleaned wafers
1.
[0155] As shown in FIG. 9, the polishing portion 130 of the CMP
apparatus 100 is equipped with a casing 101 having an opened upper
portion. On the upper end portion of a rotary shaft 102 attached to
the casing 101, there is mounted a polishing disc 104 (or platen)
to be rotationally driven by a motor 103. On the surface of this
polishing disc 104, there is mounted a polishing pad 105 which is
formed by homogeneously applying a synthetic resin having a number
of pores.
[0156] Further, this polishing portion 130 is equipped with a wafer
carrier 106 for holding the wafer 1. A drive shaft 107, to which
the wafer carrier 106 is attached, is rotationally driven together
with the wafer carrier 106 by a (not-shown) motor and is moved
upward and downward over the polishing disc 104.
[0157] The wafer 1 is held on the wafer carrier 106 with its major
face to be polished being directed downward, by a (not-shown)
vacuum sucking mechanism disposed in the wafer carrier 106. In the
lower end portion of the wafer carrier 106, there is formed a
recess 106a for accommodating the wafer 1. When the wafer 1 is
fitted in the recess 106a, its exposed face takes a level
substantially identical to or slightly protruding from the lower
end face of the wafer carrier 106.
[0158] Over the polishing disc 104, there is disposed a slurry
supply tube 108 for supplying a polishing slurry (S) between the
surface of the polishing pad 105 and the face of the wafer 1. This
face of the wafer 1 is chemically and mechanically polished with
the polishing slurry (S) supplied from the lower end of the slurry
supply tube 108. The polishing slurry (S) to be used is exemplified
by an aqueous dispersion or solution which contains mainly abrasive
grains such as alumina and an oxidizing agent such as an aqueous
solution of hydrogen peroxide or ferric nitrate.
[0159] Further, this polishing portion 130 is equipped with a
dresser 109 or a tool for shaping (or dressing) the surface of the
polishing pad 105. This dresser 109 is attached to the lower end
portion of a drive shaft 110 which is moved upward and downward
over the polishing disc 104, and is rotationally driven by a
(not-shown) motor.
[0160] The dressing treatment is performed after several wafers 1
have been polished (in the batch treatment) or each time the
polishing treatment of one wafer 1 is carried out (in the sheet
treatment). Alternatively, the dressing treatment may be effected
simultaneously with the polishing treatment. When the wafer 1 is
pushed onto the polishing pad 105 by the wafer carrier 106 and
polished for a predetermined time period, for example, the wafer
carrier 106 is retracted upward.
[0161] Next, the dresser 109 is moved downward and pushed onto the
polishing pad 105 to dress the surface of the polishing pad 105 for
a predetermined time period, and is then retracted upward.
Subsequently, another wafer 1 is attached to the wafer carrier 106,
and the aforementioned polishing treatment is repeated. After the
wafer 1 is thus polished, the rotation of the polishing disc 104 is
stopped to end the polishing work.
[0162] The wafer 1 thus polished is subjected on its surface to the
anticorroding treatment at the anticorroding portion 140. This
anticorroding portion 140 is made to have a construction similar to
that of the aforementioned polishing portion 130. Here, the major
face of the wafer 1 is pushed to the polishing pad attached to the
surface of the polishing disc (or platen), so that the polishing
slurry is mechanically removed. After this, a chemical solution
containing an anticorrosive agent such as benzotriazole (BTA) is
fed to the major face of the wafer 1, so that a hydrophobic
protective film is formed over the surface portions of the
aforementioned Cu wirings 28 to 30 formed over the major face of
the wafer 1.
[0163] The aforementioned pre-cleaning treatment for mechanically
removing the undesired chemical in the polishing slurry containing
the oxidizing agent from the surface of the wafer 1 is preferably
performed just after the end of the polishing work. That is, the
pre-cleaning treatment is performed either before the surface of
the polished wafer 1 is naturally dried or before the
electrochemical corroding reaction of the Cu wirings 28 to 30 is
substantially started by the oxidizing agent in the polishing
slurry left on the surface of the wafer 1.
[0164] The mechanical cleaning (or pre-cleaning) treatment of the
polishing slurry can also be performed by cleaning the surface of
the wafer 1 with pure water while brushing it with a scrub brush
such as a nylon brush. At the anticorroding treatment after the
pre-cleaning treatment, further, the pure water scrub cleaning,
pure water ultrasonic cleaning, pure water flow cleaning or pure
water spin cleaning treatment may be performed prior to or together
with the anticorroding treatment thereby to remove the oxidizing
agent in the polishing slurry sufficiently from the major face of
the wafer 1 at the polishing portion 130, so that the hydrophobic
protective film is formed under a condition in which the oxidizing
agent does not substantially act.
[0165] The anticorroded wafer 1 is temporarily stocked in the
immersing portion 150 so that its surface may be prevented from
becoming dry. The immersing portion 150 is provided for preventing
the surface of the anticorroded wafer 1 from becoming dry until the
wafer 1 is post-cleaned. The immersing portion 150 is made to have
a structure in which a predetermined number of wafers 1 are
immersed and stocked in an immersing bath (or stocker) overflowing
pure water, for example. At this time, the Cu wirings 28 to 30 can
be more reliably prevented from being corroded, by feeding the
immersing bath with pure water which is cooled to such a low
temperature as to prevent any substantial advance of the
electrochemical corrosion of the Cu wirings 28 to 30.
[0166] The prevention of the wafer 1 from becoming dry may be
performed by any method, such as for example a feed of pure water
shower, other than the aforementioned stock in the immersing bath,
if it can keep at least the surface of the wafer 1 in the wet
state. Here, when the aforementioned polishing treatment and
anticorroding treatment are performed by the sheet method, the
aforementioned stock in the immersing bath is not necessarily
indispensable if these treatments and the post-cleaning treatment
proceed at the same timing, but the anticorroded wafer 1 may be
instantly conveyed to the post-cleaning portion 160. Also, in this
case, however, in order to prevent the wafer 1 being conveyed from
becoming dry, the wafer 1 is preferably conveyed while being kept
wet on its surface by a pure water immersing method or pure water
shower feeding method.
[0167] The wafer 1 thus conveyed to the post-cleaning portion 160
is instantly post-cleaned while its surface is being kept wet.
Here, the surface of the wafer 1 is scrub-cleaned (or
brush-cleaned) while being fed with a weak alkaline chemical
solution such as aqueous ammonia so as to neutralize the oxidizing
agent, and the surface of the wafer 1 is then subjected to etching
with an aqueous solution of hydrofluoric acid so that it is cleared
of foreign grains (or particles) by the etching treatment. Prior to
or together with the aforementioned scrub-cleaning treatment, the
surface of the wafer 1 may be subjected to pure water
scrub-cleaning, pure water ultrasonic cleaning, pure water
flow-cleaning or pure water spin-cleaning treatment, and the back
of the wafer 1 may be subjected to pure water scrub-cleaning
treatment.
[0168] The post-cleaned wafer 1 is rinsed with pure water and
spin-dried and is stocked under the dry state in the unloader 170,
and a plurality of wafers are conveyed altogether as a unit to a
subsequent step.
[0169] Now, there will be a brief description of a process which is
performed after the Cu wires have been formed. First of all, as
shown in FIG. 10, a silicon oxide film is deposited over the Cu
wirings 28 to 30 of the second layer by the CVD method to form a
second-layer interlayer insulating film 31. Next, through holes 32
to 34 are formed in the interlayer insulating film 31 by a
dry-etching method using a photoresist film as a mask. Plugs 35 of
a W film are buried in the through holes 32 to 34. Subsequently, a
silicon oxide film 36 is deposited over the interlayer insulating
film 31 by the CVD method, and third-layer cu wirings 40 to 42 are
formed in grooves 37 to 39 formed in the silicon oxide film 36. The
plugs 35 and the third-layer Cu wirings 40 to 42 are individually
formed by a method similar to that of the aforementioned plugs 22
and second-layer Cu wirings 28 to 30. After this, as shown in FIG.
11, a passivation film 43 is formed by depositing a silicon oxide
film and a silicon nitride film over the Cu wirings 40 to 42 by the
CVD method thereby to complete a CMOS-logic LSI.
[0170] [Embodiment 2]
[0171] FIG. 12 is a schematic diagram showing the sheet type CMP
apparatus 100 to be used in this embodiment for forming the CU
wirings. This CMP apparatus 100 comprises: a loader 120 for
accommodating a plurality of wafers 1 each having a Cu film formed
on its surface; a polishing portion 130 for polishing and
planarizing the Cu film to form wirings; an anticorroding portion
140 for making the polished surface of the wafer 1 anticorrosive;
an immersing portion 150 for preventing the anticorroded wafer 1
from becoming dry on its surface until it is post-cleaned; a
post-cleaning portion 160 for post-cleaning the anticorroded wafer
1; And an unloader 170 for accommodating a plurality of
post-cleaned wafers 1. In accordance with a procedure similar to
the aforementioned one of Embodiment 1, the wafer 1 is subjected to
individual polishing, anticorroding, immersing and post-cleaning
treatments.
[0172] Further, this CMP apparatus 100 is able to prevent a
short-circuit current from being generated by a photovoltaic
effect, by providing a shading structure for the immersing portion
(or wafer stocking portion) 150 for preventing the surface of the
anticorroded wafer 1 from becoming dry, thereby to prevent the
surface of the stocked wafer 1 from being illuminated with an
illuminating light. In order to provide the immersing portion 150
with a shading structure, the illuminance of the inside of the
immersing bath (or stocker) is set to at most 500 luxes or less,
preferably 300 luxes or less, more preferably 100 luxes or less, by
coating the surrounding portion of the immersing bath (or stocker)
with a shading sheet.
[0173] Further, the corrosion of the Cu wirings can be effectively
prevented not only by providing the immersing portion 150 with a
shading structure, but also by feeding the immersing bath with pure
water which is cooled to such a low temperature that the
electrochemical corrosion of the Cu wirings may not substantially
proceed.
[0174] Furthermore, when the anticorroded wafer 1 is not
temporarily stocked in the immersing bath, but is instantly
conveyed to the post-cleaning portion 160, it is possible to
provide a shading structure for the midway conveyance path from the
anticorroding portion 140 to the post-cleaning portion 160 or to
provide both the conveyance path and the post-cleaning portion 160
with a shading structure. Further, even when the anticorroded wafer
1 is temporarily stocked in the immersing bath, the treating
portions at and downstream of the polishing portion 130, that is,
all the anticorroding portion 140, the immersing portion 150 and
the post-cleaning portion 160 may be provided with a shading
structure.
[0175] [Embodiment 3]
[0176] FIG. 13 is a schematic diagram showing a sheet type CMP
apparatus 200 to be used in this embodiment for forming Cu wirings.
This CMP apparatus 200 comprises: a loader 220 for accommodating a
plurality of wafers 1 each having a Cu film formed on its surface;
a polishing portion 230 for polishing and planarizing the Cu film
to form wirings; a drying portion 240 for drying the polished
surface of the wafer 1; a post-cleaning portion 250 for
post-cleaning the wafer 1; and an unloader 260 for accommodating a
plurality of post-cleaned wafers 1.
[0177] In the Cu wiring forming process Using the CMP apparatus
200, the wafer 1 which has been polished by the polishing portion
230 is conveyed to the drying portion 240 just after the polishing
treatment, that is, instantly before an electrochemical corrosion
with an oxidizing agent, left on the surface of the wafer 1, in the
polishing slurry can be started, so that the water content in the
polishing slurry is removed by a forced drying treatment. After
this, the wafer 1 is conveyed, while being kept in the dry state,
to the post-cleaning portion 250 in which it is post-cleaned, and
is accommodated in the unloader 170 after being rinsed with pure
water and spin-dried. The treatment at the polishing portion 230
and the treatment at the post-cleaning portion 250 are performed by
a procedure similar to the aforementioned one of Embodiment 1.
[0178] According to this embodiment, since the surface of the wafer
1 is kept in the dry state for the time period just after the
polishing treatment and before the post-cleaning treatment, the
start of any electrochemical corrosion can be suppressed to prevent
the corrosion of the Cu wirings effectively.
[0179] [Embodiment 4]
[0180] With reference to FIGS. 1 to 11, there will be described an
abrasive grain-free CMP process using a dual damascene process. In
the case of this embodiment, the plugs 22 and the copper wiring 27
of FIG. 6 are replaced by a copper wiring which is integrally made
(through a conductive barrier thin film of TiN) by plating, CVD or
a sputtering method. Under this state, the Abrasive grain-free CMP
process is executed over the main polishing stage 130. Because of a
high material selectivity of this process, the polishing
substantially terminates over the substrate film after the copper
has been removed. By this treatment, the copper is substantially
removed from the upper face of the wafer, but is locally left by
the roughness of the substrate. The wafer is transferred to the
auxiliary polishing stage 140 so that it may be cleared of the
residual copper film. This auxiliary polishing stage is given a
structure similar to that of the aforementioned main polishing
stage 130, so that it performs polishing treatment by the ordinary
CMP process while supplying the slurry containing the abrasive
grains. Next, at the same auxiliary stage 140, the removal of the
residual barrier layer and the anticorrosion treatment are
performed while suppressing the dishing of the copper wiring
portion by adding a corrosion preventing agent of copper (in an
amount of 0.001 wt. % or more, desirably 0.01% or more, more
desirably 0.1%) such as a. BTA (i.e., benzotriazole or its
derivative) to the slurry containing the aforementioned abrasive
grains.
[0181] After this, the wafer is stocked wet in the pure water bath
150 and is then subjected at the post-cleaning portion 160 to pure
water shower cleaning, ammonia cleaning (these two cleaning
treatments have a main object to remove the abrasive grains),
cleaning with hydrofluoric acid (having a main object to eliminate
the contamination), and spin-drying treatments until it is
transferred to the unloader 170.
[0182] Here, the illuminance is held at 200 luxes or less,
desirably at 100 luxes or less, from the main polishing stage 130
to the spin-drying portion 160.
[0183] Although our invention has been specifically described on
the basis of various embodiments, it should not be limited thereto,
but could naturally be modified in various ways without departing
from the gist thereof.
[0184] Although the foregoing embodiments have been described in
connection with a process using a sheet type CMP apparatus, the
invention should not be limited thereto, but can also be applied to
a process in which the individual polishing, corrosion preventing,
immersing and post-cleaning treatments are performed by the batch
method (to treat a plurality of sheets as a whole), or a
sheet-batch mixed process in which those treatments are partially
performed by the sheet method, whereas the remaining treatments are
performed by the batch method.
[0185] Further, the foregoing embodiments have been described for
the case in which the Cu wirings are formed by polishing a Cu film
(or a Cu alloy film whose main component is Cu) by the CMP method.
However, the invention should not be limited thereto, but can be
widely applied to the so-called "dual damascene process" in which a
metal layer of a Cu film, a W film or an Al alloy film is buried
simultaneously in the grooves and the through holes formed in the
insulating film, for example, and is then polished and planarized
by the CMP method to form the wirings and the plugs simultaneously,
such as the metal CMP process in which the surface side of the
wafer having the formed pattern is treated by the chemical action
of the polishing liquid and by mechanical polishing treatment to
polish and planarize the surface of the metal or the metal layer
whose main component is the metal.
[0186] Incidentally, the abrasive grain-free CMP process has been
described in detail in our Japanese Patent Application 299937/1997
(bearing an application date of Sep. 12, 1997) and its
corresponding U.S. application Ser. No. 09/182,438 (bearing a US
application date of Oct. 30, 1998).
[0187] The effects to be obtained by a representative aspect of the
invention disclosed herein will be briefly described in the
following.
[0188] According to the invention, since it is possible to reliably
prevent the corrosion of the metal wirings or metal plugs to be
formed by the CMP method, it is possible to improve the reliability
and the production yield of a high-speed LSI using the CU
wirings.
* * * * *