U.S. patent application number 10/380038 was filed with the patent office on 2004-03-04 for semiconductor device and fabrication method therefor.
Invention is credited to Akahori, Takashi, Chung, Gishi, Kawamura, Kohei.
Application Number | 20040041266 10/380038 |
Document ID | / |
Family ID | 26599616 |
Filed Date | 2004-03-04 |
United States Patent
Application |
20040041266 |
Kind Code |
A1 |
Akahori, Takashi ; et
al. |
March 4, 2004 |
Semiconductor device and fabrication method therefor
Abstract
With a stopper layer 19 as an etching stopper, a second groove
14a and a contact hole 13a are formed. Copper is buried inside the
second groove 14a and the contact hole 13a, thereby forming a plug
layer 22 and an overlying wiring layer 21 connected to an
underlying wiring layer 17 via the plug layer 22. The stopper layer
19 is comprised of Si, C and N as essential components. First and
second cap layers 18 and 23 are also comprised of Si, C and N as
essential components.
Inventors: |
Akahori, Takashi; (Kanagawa,
JP) ; Chung, Gishi; (Yamanashi, JP) ;
Kawamura, Kohei; (Yamanashi, JP) |
Correspondence
Address: |
Crowell & Moring
Intelletual Property Group
PO Box 14300
Washington
DC
20044-4300
US
|
Family ID: |
26599616 |
Appl. No.: |
10/380038 |
Filed: |
September 12, 2003 |
PCT Filed: |
September 11, 2001 |
PCT NO: |
PCT/JP01/07880 |
Current U.S.
Class: |
257/758 ;
257/E21.266; 257/E21.576; 257/E21.579 |
Current CPC
Class: |
H01L 21/76801 20130101;
H01L 21/76834 20130101; H01L 23/53295 20130101; H01L 21/76807
20130101; H01L 21/76829 20130101; H01L 2924/0002 20130101; H01L
23/53238 20130101; H01L 21/314 20130101; H01L 2924/0002 20130101;
H01L 2924/00 20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 11, 2000 |
JP |
2000-274426 |
Sep 11, 2000 |
JP |
2000-274427 |
Claims
1. (Amended) A semiconductor device comprising: a first insulating
layer (13) which has a through hole; a second insulating layer (19)
which is provided on said first insulating layer (13), has a first
opening overlapping said through hole and includes Si, C and N; and
a third insulating layer (14) which is provided on said second
insulating layer (19) and has a first groove or hole connected with
said first opening and larger in diameter than said first opening;
and a first conductive layer (21, 22) buried in said through hole,
said first opening and said first groove or hole.
2. (Amended) The semiconductor device according to claim 1, wherein
a ratio of a quantity of C atoms to a quantity of Si atoms in said
second insulating layer (19) is 0.2 or more.
3. (Amended) The semiconductor device according to claim 1, wherein
a ratio of a quantity of N atoms to said quantity of Si atoms in
said second insulating layer (19) is 0.15 or more.
4. (Amended) The semiconductor device according to claim 1, wherein
a ratio of a quantity of C atoms to a quantity of Si atoms in said
second insulating layer (19) is 0.2 to 0.8, and a ratio of a
quantity of N atoms to said quantity of Si atoms in said second
insulating layer (19) is 0.15 to 1.0.
5. (Amended) The semiconductor device according to claim 1, wherein
said second insulating layer (19) further includes H and contains
10.sup.21 to 10.sup.22 CH.sub.n groups (n being an integer of 1 to
3) per volume area.
6. (Amended) The semiconductor device according to claim 5, wherein
said second insulating layer (19) has dielectric constant of 6 or
less.
7. (Amended) The semiconductor device according to claim 1, wherein
said first conductive layer (21, 22) is comprised of copper.
8. (Amended) The semiconductor device according to claim 1, wherein
said first insulating layer (13) and/or said third insulating layer
(14) are/is comprised of silicon fluoride oxide or carbon
fluoride.
9. (Amended) The semiconductor device according to claim 1, further
comprising a fourth insulating layer (23) which is provided on said
third insulating layer (14) and said first conductive layer (21,
22), and includes Si, C and N.
10. (Amended) The semiconductor device according to claim 9,
wherein a ratio of a quantity of N atoms to said quantity of Si
atoms in said fourth insulating layer (23) is 0.15 or more.
11. The semiconductor device according to claim 9, wherein a ratio
of a quantity of C atoms to a quantity of Si atoms in said fourth
insulating layer (23) is 0.2 or more.
12. (Amended) The semiconductor device according to claim 9,
wherein a ratio of a quantity of C atoms to a quantity of Si atoms
in said fourth insulating layer (23) is 0.2 to 0.8, and a ratio of
a quantity of N atoms to said quantity of Si atoms in said fourth
insulating layer (23) is 0.15 to 1.0.
13. (Amended) The semiconductor device according to claim 9,
wherein said fourth insulating layer (23) further includes H and
contains 10.sup.21 to 10.sup.22 CH.sub.n groups (n being an integer
of 1 to 3) per volume area.
14. (Amended) The semiconductor device according to claim 13,
wherein said fourth insulating layer (23) has dielectric constant
of 6 or less.
15. (Amended) The semiconductor device according to claim 1,
further comprising: a fifth insulating layer (18) which is provided
under said first insulating layer (13), has a second opening
overlapping said through hole and includes Si, C and N; a sixth
insulating layer (12) which has a second groove or hole connected
to said second opening and larger in diameter than said second
opening, and a second conductive layer (17) buried in said second
groove or hole and electrically connected to said first wiring
layer (21) via said conductive layer (22).
16. (Amended) The semiconductor device according to claim 15,
wherein a ratio of a quantity of C atoms to a quantity of Si atoms
in said fifth insulating layer (18) is 0.2 or more.
17. (Amended) The semiconductor device according to claim 15,
wherein a ratio of a quantity of N atoms to said quantity of Si
atoms in said fifth insulating layer (18) is 0.15 or more.
18. (Amended) The semiconductor device according to claim 15,
wherein a ratio of a quantity of C atoms to a quantity of Si atoms
in said fifth insulating layer (18) is 0.2 to 0.8, and a ratio of a
quantity of N atoms to said quantity of Si atoms in said fifth
insulating layer (18) is 0.15 to 1.0.
19. (Amended) The semiconductor device according to claim 15,
wherein said fifth insulating layer (18) further includes H and
contains 10.sup.21 to 10.sup.22 CH.sub.n groups (n being an integer
of 1 to 3) per volume area.
20. (Amended) The semiconductor device according to claim 19,
wherein said fifth insulating layer (18) has dielectric constant of
6 or less.
21. (Amended) The semiconductor device according to claim 15,
wherein said second conductive layer (17) is comprised of
copper.
22. The semiconductor device according to claim 15, wherein said
sixth insulating layer (12) is comprised of silicon fluoride oxide
or carbon fluoride.
23. (Amended) A fabrication method for a semiconductor device
comprising the steps of: forming a first insulating layer (13);
forming a second insulating layer (19) including Si, C and N on
said first insulating layer (13); forming a third insulating layer
(14) on said second insulating layer (19); forming a through hole
penetrates through said first insulating layer (13), said second
insulating layer (19) and said third insulating layer (14);
selectively etching said third insulating layer (14) using said
second insulating layer (19) as a stopper to form a first groove or
hole connected with said through hole and larger in diameter than
said through hole; and burying a first conductive layer (21, 22)
inside said through hole and said first groove or hole.
24. (Amended) The fabrication method according to claim 23, wherein
said second insulating layer (19) is formed so that a ratio of a
quantity of C atoms to a quantity of Si atoms in said second
insulating layer (19) is 0.2 or more.
25. (Amended) The fabrication method according to claim 23, wherein
said second insulating layer (19) is formed so that a ratio of a
quantity of N atoms to said quantity of Si atoms in said second
insulating layer (19) is 0.15 or more.
26. The fabrication method according to claim 23, wherein said
second insulating layer (19) is formed so that a ratio of a
quantity of C atoms to a quantity of Si atoms in said second
insulating layer (19) is 0.2 to 0.8, and a ratio of a quantity of N
atoms to said quantity of Si atoms in said second insulating layer
(19) is 0.15 to 1.0.
27. (Amended) The fabrication method according to claim 23, wherein
said second insulating layer (19) is formed so that said second
insulating layer (19) contains 10.sup.21 to 10.sup.22 CH.sub.n
groups (n being an integer of 1 to 3) per volume area.
28. (Amended) The fabrication method according to claim 23, wherein
said second insulating layer (19) is formed by plasma CVD using an
organic silazane compound as a staring material.
29. (Amended) The fabrication method according to claim 23, wherein
said first insulating layer (13) and/or said third insulating layer
(14) are/is formed with silicon fluoride oxide or carbon
fluoride.
30. (Amended) The fabrication method according to claim 23, wherein
said first conductive layer (21, 22) is formed with copper.
31. (Amended) The fabrication meddled according to claim 23,
further comprising a step of forming a fourth insulating layer (23)
including Si, C and N on said first insulating layer (13) and said
first conductive layer (21,22).
32. (Amended) The fabrication method according to claim 31, wherein
said fourth insulating layer (23) is formed so that a ratio of a
quantity of C atoms to a quantity of Si atoms in said fourth
insulating layer (23) is 0.2 or more.
33. (Amended) The fabrication method according to claim 31, wherein
said fourth insulating layer (23) is formed so that a ratio of a
quantity of N atoms to said quantity of Si atoms in said fourth
insulating layer (23) is 0.15 or more.
34. (Amended) The fabrication method according to claim 31, wherein
said fourth insulating layer (23) is formed so that a ratio of a
quantity of C atoms to a quantity of Si atoms in said fourth
insulating layer (23) is 0.2 to 0.8, and a ratio of a quantity of N
atoms to said quantity of Si atoms in said fours insulating layer
(23) is 0.15 to 1.0.
35. (Amended) The fabrication method according to claim 31, wherein
said fourth insulating layer (23) is formed so that said fourth
insulating layer (23) contains 10.sup.21 to .sup.10.sup.22 CH.sub.n
groups (n being an integer of 1 to 3) per volume area.
36. (Amended) The fabrication method according to claim 31, wherein
said fourth insulating layer (23) is formed by plasma CVD using an
organic silazane compound as a starting material.
37. (Amended) The semiconductor device according to claim 23,
further comprising: forming a fifth insulating layer (12) which is
provided a second conductive layer (17) in one surface thereof;
forming a sixth insulating layer (18) which is provided on said
fifth insulating layer (12) and said second conductive layer (17)
and includes Si, C and N; forming said first insulating layer (13)
on said sixth insulating layer (18); and forming said through hole
to reach said second conductive layer (17) through said sixth
insulating layer (18).
38. (Amended) The fabrication method according to claim 37, wherein
said sixth insulating layer (18) is formed so that a ratio of a
quantity of C atoms to a quantity of Si atoms in said sixth
insulating layer (18) is 0.2 or more.
39. The fabrication method according to claim 37, wherein said
sixth insulating layer (18) is formed so that a ratio of a quantity
of N atoms to said quantity of Si atoms in said sixth insulating
layer (18) is 0.15 or more.
40. (Amended) The fabrication method according to claim 37, wherein
said sixth insulating layer (18) is formed so that a ratio of a
quantity of C atoms to a quantity of Si atoms in said sixth
insulating layer (18) is 0.2 to 0.8, and a ratio of a quantity of N
atoms to said quantity of Si atoms in said sixth insulating layer
(18) is 0.15 to 1.0.
41. (Amended) The fabrication method according to claim 37, wherein
said sixth insulating layer (18) is formed so that said sixth
insulating layer (18) contains 10.sup.21 to 10.sup.22 CH.sup.n
groups (n being an integer of 1 to 3) per volume area.
42. (Amended) The fabrication method according to claim 37, wherein
said sixth insulating layer (18) is formed by plasma CVD using an
organic silazane compound as a starting material.
43. (Amended) The fabrication method according to claim 37, wherein
said fifth insulating layer (12) is formed with silicon fluoride
oxide or carbon fluoride.
44. (Amended) The fabrication method according to claim 37, wherein
said second conductive layer (17) is formed with copper.
45. (Deleted)
46. (Deleted)
Description
TECHNICAL FIELD
[0001] The present invention relates to a highly reliable
semiconductor device and a fabrication method for a semiconductor
device.
BACKGROUND ART
[0002] To acquire a high-performance large scale integrated circuit
(LSI), copper has recently been used as a wiring material. As
copper has a lower resistance than that of aluminum, a fast circuit
is provided. As copper has a high diffusibility, however, copper,
if in directly contact with a semiconductor, deteriorates the
semiconductor characteristics.
[0003] Due to the high diffusibility, unlike aluminum wires, copper
wires cannot be formed by an etching process. Therefore, a
so-called dual damascene scheme is used as a method of forming
copper multilayer wiring without etching.
[0004] The following describes steps of fabricating a semiconductor
device having copper multilayer wiring using the dual damascene
scheme with reference to FIGS. 10A to 10D. First, a cap layer 103
of silicon nitride or the like is formed on a first insulating
layer 102 of silicon oxide or the like in which an underlying
wiring layer 101 is buried. The underlying wiring layer 101
comprises a conductive layer 104 of copper or the like and a
barrier layer 105 of tantalum nitride or the like which encloses
the conductive layer 104.
[0005] Next, a second insulating layer 106 of silicon oxide or the
like is formed on the cap layer 103. The cap layer 103 prevents
diffusion of copper to the second insulating layer 106 from the
underlying wiring layer 101. Further, a stopper layer 107 of
silicon nitride or the like is formed on the second insulating
layer 106, and a third insulating layer 108 of silicon oxide or the
like is deposited on the stopper layer 107. This provides a
resultant structure as shown in FIG. 10A.
[0006] Subsequently, as shown in FIG. 10B, a first photoresist
pattern 109 is formed on the third insulating layer 108 and a hole
110 with the conductive layer 104 as its bottom is formed by
etching. At this time, etching is carried out under the conditions
where the second and third insulating layers 106 and 108, the
stopper layer 107 and the cap layer 103 are all etched. After
etching, the first photoresist pattern 109 is removed by ashing or
the like.
[0007] Then, as shown in FIG. 10C, a second photoresist pattern 111
is formed on the third insulating layer 108 and selective etching
is performed. Here, etching is carried out under the conditions
where the third insulating layer 108 is etched while the stopper
layer 107 is not etched. That is, the stopper layer 107 serves as
an etching stopper.
[0008] In etching, a trench hole 112 which overlaps the hole 110
and has the stopper layer 107 as its bottom is formed in the third
insulating layer 108. As a result, the trench hole 112 and a
contact hole 113 which connects the trench hole 112 to the
underlying wiring layer 101 are formed. After etching, the second
photoresist pattern 111 is removed by ashing or the like.
[0009] Subsequently, a barrier layer 114 of tantalum nitride or the
like is formed on the inner walls of the trench hole 112 and the
contact hole 113 by CVD or the like. Further, after the trench hole
112 and the contact hole 113 are buried by plating, excess metal
layers are removed by CMP. Through the above-described steps, a
plug layer 15 and an overlying wiring layer 116 which is connected
to the underlying wiring layer 101 via the plug layer 115 are
formed as shown in FIG. 10D. By repeating the above-described
steps, a multi-level wiring layer having two or more layers can be
formed.
[0010] The stopper layer 107 and the cap layer 103 exist in the
interlayer insulating film in the semiconductor device that is
formed by the dual damascene scheme. Normally, the stopper layer
107 and the cap layer 103 are comprised of insulating films of the
same material, i.e., they are formed by using the same film
deposition apparatus.
[0011] The insulating films that constitute the cap layer 103 and
the stopper layer 107 can generally be classified into a type which
essentially consists of silicon (Si) and nitrogen (N) (hereinafter
referred to as SiCN-based film) and a type which essentially
consists of Si and carbon (C) (hereinafter referred to as SiC
film).
[0012] As the insulating films are present in the interlayer
insulating film they are demanded of a low dielectric constant.
Further, the insulating films are demanded of a high etching
selectivity, as the stopper layer, with respect to the interlayer
insulating film, and are demanded of a high barrier property
against an wiring material (i.e. low metal diffusibility) as the
cap layer.
[0013] In case where the insulating films are formed of an SiC
film, while the dielectric constant of the film is about 5 which is
relatively low and a high etching selectivity is obtained with
respect to the interlayer insulating film, the barrier property
against copper thereof is low. In case where the insulating films
are composed of an SiCN-based film, on the other hand, while the
barrier property against copper is high, the dielectric constant is
about 7 to 8 which is relatively high and the etching selectivity
is low. In case where FSG (Fluorinated Silicate Glass) is used for
the interlayer insulating film, the SiCN-based film is likely to be
damaged by fluorine radicals that are produced at the time of
etching.
[0014] As apparent from the above, the insulating films that
constitute the conventional stopper layer and/or cap layer did not
fully satisfy all of a low dielectric constant, a high etching
selectivity with respect to the interlayer insulating film and a
barrier property for the wiring material, and it was hard to
provide a sufficiently reliable semiconductor device.
DISCLOSURE OF INVENTION
[0015] It is therefore an object of the invention to provide a
highly reliable semiconductor device and a fabrication method
therefor.
[0016] It is another object of the invention to provide a
semiconductor device which includes an insulating film having a low
dielectric constant, a high etching selectivity with respect to an
interlayer insulating film and a barrier property for a wiring
material, and a fabrication method for the semiconductor
device.
[0017] To achieve the objects, according to the first aspect of the
invention, there is provided a semiconductor device which comprises
a first insulating layer which has, on one surface thereof, a
groove or a hole reaching an other surface side; a second
insulating layer which is provided on said first insulating layer,
has an opening overlapping said groove or hole and is comprised of
Si, C and N as essential components; and a conductive layer buried
inside said groove or hole and said opening.
[0018] According to the second aspect of the invention, there is
provided a fabrication method for a semiconductor device which
comprises the steps of forming a first insulating layer, forming a
second insulating layer containing Si, C and N as essential
components on said first insulating layer, selectively etching said
second insulating layer to form an opening; etching said first
insulating layer using said opening as a mask, thereby forming an
wrong groove or hole; and burying a conductive layer inside said
opening or said wiring groove or hole.
BRIEF DESCRIPTION OF DRAWINGS
[0019] FIG. 1 shows a partial cross section of a semiconductor
device according to a first embodiment;
[0020] FIGS. 2A to 2H illustrate fabrication steps for the
semiconductor device shown in FIG. 1;
[0021] FIG. 3 shows the compositions of an SiCN-based film
according to the first embodiment;
[0022] FIG. 4 shows the ratio of the etching rate of the SiCN-based
film shown in FIG. 3 to the etching rate of an SiCN-based film;
[0023] FIG. 5 shows the results of studying the barrier property of
the SiCN-based film shown in FIG. 3 with respect to copper by using
SIMS;
[0024] FIG. 6 illustrates the relationship between the number of
CH.sub.n groups and the dielectric constant of an SiCN-based film
according to a second embodiment;
[0025] FIG. 7 shows the results of studying the barrier property of
the SiCN-based film shown in FIG. 6 with respect to copper by using
SIMS;
[0026] FIG. 8 exemplifies the results of studying the barrier
property of an SiCN-based film by using SIMS;
[0027] FIGS. 9A to 9E illustrate a modification of the fabrication
method of a semiconductor device; and
[0028] FIGS. 10A through 10D are diagrams for explaining the dual
damascene scheme.
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment)
[0029] A semiconductor device according to one embodiment of the
invention is described below with reference to the accompanying
drawings.
[0030] FIG. 1 is a partial cross-sectional view showing the
structure of a semiconductor device according to the embodiment.
This semiconductor device has elements, such as a memory and
transistors, formed on a silicon substrate, and a multi-level
wiring layer formed on an interlayer insulating film which covers
the elements. FIG. 1 shows a two-level wiring layer near the
surface of the semiconductor device.
[0031] As shown in FIG. 1, a semiconductor device 11 has a first
insulating layer 12, a second insulating layer 13, a third
insulating layer 14 and a passivation film 15.
[0032] The first insulating layer 12 is comprised of silicon
fluoride oxide (SiOF) and is formed, for example, 0.8 .mu.m thick.
The first insulating layer 12 has a first groove 12a. An underlying
wiring layer 17 of copper is buried in the first groove 12a via a
first barrier film 16. The first barrier film 16 has capabilities
to prevent diffusion of copper outside the first groove 12a and
enhance the adhesion between the first insulating layer 12 and the
underlying wiring layer 17. The first barrier film 16 is comprised
of a multilayer of a high melting-point metal, such as Ta/TaN, W/WN
or Ti/TiN, or an alloy thereof.
[0033] A first cap layer 18 is formed, for example, 50 nm thick on
the surface of the first insulating layer 12. The first cap layer
18 prevents copper of the underlying wiring layer 17 from being
diffused into the second insulating layer 13. The first cap layer
18 is comprised of a film which essentially consists of silicon
(Si), carbon (C) and nitrogen (N) (hereinafter referred to as
SiCN-based film).
[0034] The second insulating layer 13 is provided on the first cap
layer 18. The second insulating layer 13, which is comprised of
SiOF, is formed, for example, 0.8 .mu.m thick.
[0035] A stopper layer 19 is formed, for example, 50 nm thick on
the second insulating layer 13. The stopper layer 19 serves as an
etching stopper in the fabrication process for the semiconductor
device 11 which will be discussed later. The stopper layer 19 is
formed of substantially the same SiCN-based film as that of the
first cap layer 18.
[0036] A contact hole 13a, which penetrates through the second
insulating layer 13, the first cap layer 18 and the stopper layer
19, is formed in the second insulating layer 13. The contact hole
13a is formed in such a way as to overlap the first groove 12a.
[0037] The third insulating layer 14 is provided on the stopper
layer 19. The third insulating layer 14, which is comprised of
SiOF, is formed, for example, 0.8 .mu.m thick. Formed in the third
insulating layer 14 is a second groove 14a, which penetrates the
third insulating layer 14 and has the stopper layer 19 as its
bottom. The second groove 14a is formed in such a way as to overlap
the contact hole 13a The first groove 12a and the second groove 14a
are connected by the contact hole 13a.
[0038] Copper as a wiring material is buried in the second groove
14a and the contact hole 13a via a second barrier film 20. The
second barrier film 20 has substantially the same composition as
the first barrier film 16 and prevents copper diffusion.
[0039] The copper that is buried in the second groove 14a forms an
overlying wiring layer 21. The copper that is buried in the contact
hole 13a forms a plug layer 22 which connects the underlying wiring
layer 17 to the overlying wiring layer 21.
[0040] A second cap layer 23 is formed, for example, 50 nm thick on
the second insulating layer 13 in such a way as to cover the top
surface of the overlying wiring layer 21. The second cap layer 23
prevents copper diffusion above the overlying wiring layer 21.
[0041] The passivation film 15 is formed, for example, 0.8 .mu.m
thick on the second cap layer 23. The passivation film 15 is
comprised of a silicon fluoride oxide film A protective film 24,
which is comprised of a silicon oxide film, a silicon nitride oxide
film or the like, is formed, for example, 50 nm thick on the
passivation film 15.
[0042] As mentioned above, the SiCN-based film according to the
first embodiment, which forms the f and second cap layers 18 and 23
and the stopper layer 19, essentially consists of Si, C and N.
Specifically, the ratio of the quantity of C atoms in the film to
the quantity of Si atoms (ClSi) ranges from 02 to 0.8, and the
ratio of the quantity of N atoms to the quantity of Si atoms (N/Si)
ranges from 0.15 to 1.0.
[0043] The SiCN-based film which has the above-described
composition has a dielectric constant of about 5 to 55. This is
lower than the dielectric constant (about 7) of the film that
essentially consists of Si and N (hereinafter referred to as
SiN-based film) but is approximately the same as the dielectric
constant (about 5) of the film that essentially consists of Si and
C (SiC-based film).
[0044] The following describes a fabrication method for the
semiconductor device 11 having the above-described structure with
reference to the drawings. In the first embodiment, the
semiconductor device 11 is fabricated by using the dual damascene
scheme. FIG. 2A to FIG. 2H illustrate fabrication steps for the
semiconductor device in order.
[0045] First, a semiconductor substrate 10 having the first
insulating layer 12 in which the underlying wiring layer 17 is
formed is prepared. Then, the first cap layer 18 is formed, for
example, 50 nm thick on the first insulating layer 12 including the
underlying wiring layer 17. The first cap layer 18, which is
comprised of an SiCN-based film, is formed by chemical vapor
deposition (CVD) which uses an electron cyclotron resonance (ECR)
plasma. A mixed gas of, for example,
SiH.sub.4/C.sub.2H.sub.4/N.sub.2/Ar (flow rate (sccm): 10/5/25/100
to 10/25/5/100) is used in film deposition.
[0046] Further, the second insulating layer 13 of SiOF is formed,
for example, 0.8 .mu.m thick on the first cap layer 18. Film
deposition is carried out by ECR plasma CVD using a mixed gas of,
for example, SiH.sub.4/SiF4/O.sub.2/Ar (flow rate (sccm):
50/50/200/100). This yields a resultant structure as shown in FIG.
2A.
[0047] Then, as shown in FIG. 2B, the stopper layer 19, comprised
of an SiCN-based film, is formed, for example, 50 nm thick on the
second insulating layer 13. Film deposition is carried out by ECR
plasma CVD using a mixed gas of, for example,
SiH.sub.4/C.sub.2H.sub.4/N.sub.2/Ar (flow rate (sccm): 10/5/25/100
to 10/25/5/100).
[0048] Subsequently, as shown in FIG. 2C, the third insulating
layer 14 14 of SiOF is formed, for example, 0.8 .mu.m thick on the
stopper layer 19. For example, film deposition is carried out by
ECR plasma CVD using a mixed gas of SiH.sub.4/SiF.sub.4/O.sub.2/Ar
(flow rate (sccm): 50/50/200/100).
[0049] Then, a first photoresist pattern 30 is formed on the third
insulating layer 14 by using photolithography technique. Next,
etching is performed with the first photoresist pattern 30 as a
mask. This forms a hole 31, which penetrates the second insulating
layer 13, the third insulating layer 14 and so forth and has the
underlying wiring layer 17 as its bottom, as shown in FIG. 2D.
Here, etching is executed by reactive ion etching (RIE) using a
mixed gas plasma of, for example, O.sub.2 and CF.sub.4.
Accordingly, an SiOF film (the second insulating layer 13 and the
third insulating layer 14) and an SiCN-based film (the first cap
layer 18 and the stopper layer 19) are etched simultaneously.
Thereafter, the first photoresist pattern 30 is removed by
ashing.
[0050] Subsequently, a second photoresist pattern 32 is formed on
the third insulating layer 14 by using the photolithography
technique. Next, etching is performed with the second photoresist
pattern 32 as a mask. The etching is carried out under the
conditions where while the SiOF film (the third insulating layer
14) is etched, the SiCN-based film (the stopper layer 19) is not
etched. The etching is executed by RIE using a mixed gas plasma of,
for example, C.sub.4F.sub.8 and CO. Accordingly, the second groove
14a whose bottom is the stopper layer 19 and the contact hole 13a
which extends from the second groove 14a to the underlying wiring
layer 17 are formed, as shown in FIG. 2E.
[0051] Subsequently, as shown in FIG. 2F, the second barrier film
20 is formed on the entire inner walls of the second groove 14a and
the contact hole 13a by sputtering or the like. The second barrier
film 20 is, for example, a TaN and Ta deposited film (Ta/TaN).
[0052] Then, after a seed layer of copper is formed on the entire
surface of the semiconductor substrate 10 by sputtering or the
like, copper plating is performed. As a result, the interiors of
the second groove 14a and the contact hole 13a are buried with
copper. Then, the excess metal layers on the surface of the
semiconductor substrate 10 are removed by chemical mechanical
polishing (CMP). As a result, the overlying wiring layer 21 and the
plug layer 22 as shown in FIG. 2G are formed.
[0053] Further, the second cap layer 23 comprised of an SiCN-based
film is formed, for example, 50 nm thick on the third insulting
layer 14 including the overlying wiring layer 21. The second cap
layer 23 is deposited in the same way as the first cap layer
18.
[0054] Further, the passivation film 15 of, for example, SiOF is
formed, for example, 0.8 .mu.m thick on the second cap layer 23 by
ECR plasma CVD.
[0055] Finally, the protective film 24 of silicon oxide is formed
50 nm thick. As a result, the semiconductor device 11 as shown in
FIG. 2H is acquired Here, the second cap layer 23, the passivation
film 15 and the protective film 24 are deposited by the same ECR
plasma CVD apparatus. This completes the fabrication process.
EXAMPLES
[0056] In the example of the fabrication process, the SiCN-based
film is formed by ECR plasma CVD using a mixed gas of
SiH.sub.4/C.sub.2H.sub.4/N.- sub.2/Ar (flow rate (sccm):
10/5/25/100 to 10/25/5/100). FIG. 3 shows the ratio of the quantity
of C atoms in the SiCN-based film to the quantity of Si atoms
(C/Si) and the ratio of the quantity of N atoms to the quantity of
Si atoms (N/Si) when deposition is carried out while the mixing
ratio of the C.sub.2H.sub.4 gas and the N.sub.2 gas is changed with
a constant flow rate of SiH.sub.4.
[0057] The quantities of the Si, C and N atoms in the SiCN-based
film were calculated by Rutherford backscattering spectroscopy
(RPS). In FIG. 3, cases I and VII respectively show the results in
the case where N.sub.2 alone was used and the case where
C.sub.2H.sub.4 alone was used. Cases II to VI respectively show the
results in the cases where, given that the total flow rate of
C.sub.2H.sub.4 and N.sub.2 is 30 sccm, the individual flow rates
were changed to 5, 10, 15, 20 and 25.
[0058] As apparent from the results of cases II to VI in FIG. 2,
the ratio of the C content to the N content in the SiCN-based film
varies in accordance with the ratio of the flow rate of
C.sub.2H.sub.4 to the flow rate of N.sub.2. That is, the greater
the amount of C.sub.2H.sub.4 in the process gas is, the higher the
C content (C/Si) in the SiCN-based film to be formed becomes. The
greater the amount of N.sub.2 becomes, on the other hand, the
higher the N content (N/Si) in the SiCN-based film becomes. Of
course, the SiN film and the SiC film are respectively formed in
cases I and II where only one of C.sub.2H.sub.4 and N.sub.2 is
used.
[0059] It is understood that when the flow rates of C.sub.2H.sub.4
and N.sub.2 are changed between 5/25 to 25/5, N/Si varies within
the range of 0.2 (case VI) to 0.9 (case II), and C/Si varies within
the range of 0.25 (case II) to 0.8 (case VI).
[0060] FIG. 4 shows the results of studying the etching rate for
the films with the structures shown in FIG. 3 (cases I to VII).
FIG. 4 shows the ratio of the etching rate when the etching rate of
the SiN film (case 1) is set to 1. An O.sub.2/CF.sub.4 plasma gas
was used in etching.
[0061] As apparent from FIG. 4, the etching rate of the SiC film
(case VII) is equal to or greater than double that of the SiN film.
It is apparent that the SiCN-based film shows an intermediate
etching rate between those of the SiC film and the SiN film, and a
higher etching rate is acquired as the C content in the film
increases.
[0062] In case where the SiOF film is used as an interlayer
insulating film and the SiN film (case I) is used as an etching
stopper, the etching selectivity is low and a good etching shape is
not obtained. In case of the SiCN-based film (cases II to VI) whose
C/Si is equal to or greater than 0.2 or at least 0.25 or above,
however, the etching rate is high and a high etching selectivity to
the SiOF film is obtained, so that a good etching profile is
obtained. It is seen from FIG. 3 that when N/Si is equal to or
smaller than 1 or at least 0.9 or below, a high barrier property is
acquired.
[0063] The barrier property of the SiCN-based film (cases II to VI)
that is formed in the above-described manner against the wiring
material, particularly, the barrier property against copper was
studied. Copper has the highest diffusibility among wiring
materials which are generally used. Note that studies were also
made on the SiN film (case I) and the SiC film (case VII).
[0064] Specifically, the barrier property was studied as follows.
First, an SiCN-based film is deposited on the silicon substrate and
further a copper layer is formed 0.2 .mu.m thick. Then, the silicon
substrate is held at 450.degree. C. for seven hours. For the
silicon substrate after the heat treatment, the SIMS (Secondary Ion
Mass Spectroscopy) strength of copper in the vicinity of the
interface between the silicon substrate and the SiCN-based film was
studied. Generally, if diffusion of copper to the silicon substrate
is not detected by the SIMS under the above-described conditions,
it is considered that there is no problem in the usage of the
device. FIG. 5 shows the results.
[0065] It is seen from FIG. 5 that, for the SiC film (case VII),
copper is detected near the interface and the barrier property of
the SiC film against copper is low. For the SiN film (case I) and
the SiCN-based film (cases II to VI), however, copper is not
detected and a high barrier property against copper is shown This
shows that the higher the N content in the film gets (the lower the
C content is), the higher the barrier property gets. Further, it is
understood that when the ratio of N to Si (N/Si) in the film is
0.15 or greater or at least 0.2 or above, a high barrier property
is obtained so that diffusion of the wiring material such as
copper, can be prevented. Referring to FIG. 3, it is understood
that when C/Si is 0.85 or greater or at least 0.8 or above, a high
barrier property is obtained.
[0066] It is understood from the results shown in FIGS. 4 and 5
that the SiCN-based film whose C/Si is 0.2 or greater or at least
0.25 or above (N/Si is 1 or smaller or at least 0.9 or smaller and
whose N/Si is 0.15 or greater or at least 0.2 or greater (C/Si is
0.85 or greater or at least 0.8 or above) has a low dielectric
constant and has an excellent etching selectivity and a high
barrier property. It is therefore apparent that the SiCN-based film
in the first embodiment which has such compositions that C/Si is
0.2 to 0.8 and N/Si is 0.15 to 1.0 has a low dielectric constant,
an excellent etching selectivity and a high barrier property, and
is suitable as an etching stopper and a cap film.
(Second Embodiment)
[0067] A semiconductor device 11 according to the second embodiment
of the invention has the same structure as that of the first
embodiment shown in FIG. 1 and has an insulating film comprised of
an SiCN-based film. The SiCN-based film in the second embodiment
contains 10.sup.21 to 10.sup.22 CH.sub.n groups (n being an integer
of 1 to 3), i.e., CH groups, CH.sub.2 groups and CH.sub.3 groups,
per volume area.
[0068] The SiCN-based film in the second embodiment is formed by
using various kinds of starting materials including at least one of
Si, CH.sub.n groups and N as an essential element. For example,
monosilane (SiH.sub.4), ethylene (C.sub.2H.sub.4) and nitrogen
(N.sub.2) can be used as starting materials. Further, an organic
silicon material containing Cn groups (e.g., methylated silane,
silazane material and a N-containing material (e.g., N.sub.2,
NH.sub.3) can be used as starting materials. Furthermore, a
material containing Si, CH.sub.n groups and N, for example,
methylated silane, can be used alone.
[0069] The SiCN-based film is formed in such a way as to contain a
predetermined number (10.sup.21 to 10.sup.22 groups/cm.sup.3) of
CH.sub.n groups in the film. The quantity of CH.sub.n groups can be
adjusted by changing the mixing ratio or the like of the starting
materials.
[0070] FIG. 6 illustrates the relationship between the number of Co
groups per unit volume (groups/cm.sup.3) in the SiCN-based film
formed of various staring materials and the dielectric constant. 1a
FIG. 6, the SiCN-based films that were formed by using the
following mixed gases A to F are checked. Here, the quantity of
CH.sub.n bonding was measured in the direction of the film depth by
an X-ray photoelectron spectroscopy (XPS).
[0071] A: silane (SiH.sub.4)/C.sub.2H.sub.4/N.sub.2/Ar
[0072] B: trimethylsilane (SiH(CH.sub.3).sub.3)/N.sub.2/Ar
[0073] C: trimethylsilane/NH.sub.3/Ar
[0074] D: hexamethylcyclotrisilazne
((Si(CH.sub.3).sub.2--NH).sub.3)/Ar
[0075] E: hexamethylcyclotrisilme
((Si(CH.sub.3).sub.2--NH.sub.3)/N.sub.2/- Ar
[0076] F: hexamethylcyclotrisilazne/NH.sub.3/Ar
[0077] It is understood from FIG. 6 that in any one of the A to F
cases, an SiCN-based insulating film having a low dielectric
constant can be obtained by increasing the quantity of CH.sub.n
groups. When SiH.sub.4, C.sub.2H.sub.4 and N.sub.2 are used (A),
for example, the dielectric constant of the film drops from about
6.8 to 5 as the quantity of CH.sub.n groups in the SiCN-based film
to be formed is increased from 10.sup.20 (groups/cm.sup.3) to less
than 10.sup.22 (groups/cm.sup.3). When hexamethylcyclotrisilazne
and NH.sub.3 are used (F), the dielectric constant of the film
drops from about 6.8 to 4.2 as the quantity of CH.sub.n groups in
the film is increased from 10.sup.20 (groups/cm.sup.3) to less than
10.sup.21 (groups/cm.sup.3).
[0078] It is apparent that the SiCN-based film containing 10.sup.21
(groups/cm.sup.3) or larger CH.sub.n groups has a dielectric
constant of 6 or less, specifically, 5.5 or less. This shows that
the SiCN-based film in the second embodiment which contains
10.sup.21 to 10.sup.22 (groups/cm.sup.3) CH.sub.n groups has a
dielectric constant of 6 or less. This is lower than the dielectric
constant (7 to 8) of the SiN film that is normally used as a
stopper film or the like, so that the SiCN-based film can be
suitably used as a stopper film or the like.
[0079] It is understood that in case where the quantity of CH
groups in the film is the same but the staring materials differ,
the dielectric constant differs. For example, the larger the
molecular size of the starting material is, the lower the
dielectric constant becomes. That is, a lower dielectric constant
is obtained when trimethylsilane (SiH(CH.sub.3).sub.3) is used than
when monosilane (SiH.sub.4) is used, and a much lower dielectric
constant is obtained when hexamethylcyclotrisilaze
((Si(CH.sub.3).sub.2--NH).sub.3) is used.
[0080] The following describes the barrier property of the
SiCN-based film against copper.
[0081] FIG. 7 shows the relationship between the quantity of
CH.sub.n groups in the SiCN-based film and the diffusibility of
copper. Copper diffusion was measured by the SIMS (Secondary Ion
Mass Spectroscopy). In the measurement, a substrate which has an
SiCN-based film (0.05 .mu.m) and a silicon oxide film (0.1 .mu.m)
deposited in order on a copper layer was used and the substrate was
heated at 400.degree. C. for three hours after which the
measurement was made by the SIMS.
[0082] According to the measurement using the SIMS, the results as
shown in FIG. 8 are obtained. FIG. 8 shows the SIMS strengths of
Si, C and copper and the quantities of the individual atoms at a
predetermined depth from the surface. The diffusion range of copper
shown in FIG. 7 indicates the diffusion range of copper into the
SiCN-based film (to the depth of 0.1 .mu.m to 0.15 .mu.m from the
surface) in FIG. 8.
[0083] It is apparent from FIG. 7 that when the quantity of
CH.sub.n groups per unit volume is about 10.sup.21
(groups/cm.sup.3), copper is hardly diffused. It is apparent that
when the quantity of CH.sub.n groups is about 10.sup.21 to about
10.sup.22 (groups/cm.sup.3), diffusion in the SiCN-based film is
seen but diffusion in the silicon oxide film is suppressed. This
shows that the SiCN-based film in the second embodiment which
contains 10.sup.21 to 10.sup.22 (groups/cm.sup.3) CH.sub.n groups
has a good barrier property against copper.
[0084] The invention is not limited to the above-described
embodiments, but can be modified and adapted in various forms. The
following describes modifications of the embodiments, which can be
adapted to the invention.
[0085] In the embodiments, etching of the interlayer insulating
film uses a mixed gas of O.sub.2 and CF.sub.4 and a mixed gas of
C.sub.4F. and CO. But, they are not restrictive and a plasma gas,
such as a mixed gas of H.sub.2, Ar and N.sub.2, can also be used.
Further, for CF.sub.4 and C.sub.4F.sub.8, other fluorocarbon
materials (C.sub.mF.sub.n (m and n being integers of 0 or above)
can be used.
[0086] In the embodiments, the second cap layer 23, the passivation
film 15 and the protective film 24 were deposited by using ECR
plasma CVD apparatus. However, this is not restrictive and at least
one of those layer and films may be formed in another CVD apparatus
or all of them may be formed in separate CVD apparatuses.
[0087] In the embodiments, the SiCN based film was formed with
SiH.sub.4, C.sub.2H.sup.4 and N.sub.2 as source gas compounds. As
illustrated in the second embodiment, however, any source compounds
can be used as long as they are compounds containing Si, C and N
and the SiCN-based film is formed by a single compound or by the
reaction of the proper combination of those compounds.
[0088] When three source gas compounds each containing Si, C and N
are used, for example, SIH.sub.4 is for an Si-containing material,
C.sub.2H.sub.4, CH.sub.4, C.sub.2H.sub.6, C.sub.2H.sub.2 and so
forth have only to be combined properly for a C-containing compound
and N.sub.2, NF.sub.3, N.sub.2O, N.sub.2O.sub.4, NO, N.sub.3H.sub.8
and so forth have only to be combined properly for an N-containing
compound.
[0089] Two kinds of gases, a source compound containing Si and C
and a source compound containing N, may be mixed in film
deposition. In this case, the aforementioned compounds are used as
the N-containing compound, an organic silane, such as alkylsilane
or alkoxylsilane, is used as the compound containing Si and C, and
they should be properly combined. As alkylsilane, for example,
there is methylated silane, such as methylsilane
(SiH.sub.3(CH.sub.3)), dimethylsilane (SiH.sub.2(CH.sub.3).sub.2),
trimethylsilane (SiH(CH.sub.3)) or tetramethylsilane
(Si(CH.sub.3).sub.4). As alkoxylsilane, for example, there is
methoxylated silane, such as trimethoxymethylsilane
(Si(CH.sub.3)(OCH.sub.3).sub.3). To the contrary, a source gas
containing Si and N and a source gas containing C may be mixed. In
this case, the C-containing compound should be selected from those
mentioned above, and as the compound containing Si and N,
disilaazane (SiH.sub.3--NH--SiH.sub.- 3), for example, may be used,
and they should be properly combined.
[0090] Further, a compound containing all of Si, C and N can be
used as a source gas. As such a compound, an organic silazane
compound having silane bonding (--Si--N--) can be used. In case
where an organic silazane compound is used, it may be subjected to
thermal polymerization to form a film by, for example, plasma CVD.
Usable organic silazane compounds are, for example, triethylsilazne
(SiEt.sub.3NH.sub.2), tripropylsilazane (SiPr.sub.3NH.sub.2),
triphenylsilazane (SiPh.sub.3NH.sub.2), tetramethyldisilazane
(SiMeH--NH--SiMe.sub.2H), hexamethyldizane
(SiMe.sub.3--NH--SiMe.sub.3), hexaethyldisilazine
(SiEt.sub.3--NH--SiEt.s- ub.3), hexaphenyldisne
(SiPh.sub.3--NH--SiPh.sub.3), heptamethy lisilaane
(SiMe.sub.3--NMe--SiMe.sub.3), dipropyl-tetramethyldisilazane
(SiPrMe.sub.2--NH--SiPrMe.sub.2), di-n-butyl etarethyldisilazane
(SiBuMe.sub.2--NH--SiBuMe.sub.2), di-n-octyl-tetramethyldisilazine
(SiOcMe.sub.2--NH--SiOcMe.sub.2),
triethyl-trimethylcyclotrisilazane ((SiEtH--NMe).sub.3),
hexamethylcyclotrisilazane (SiMe.sub.2--NH).sub.3),
hexaethylcyclotrisilazane (SiEt.sub.2-NH).sub.3),
hexaphenylcyclotrisilaz- ane ((SiPh.sub.2--NH).sub.3),
octamethylcyclotetrasilazane ((SiMe.sub.2--NH).sub.4),
octaethylcyclotetrasilazane ((SiEt.sub.2-NH).sub.4),
tetraethyl-tetramethylcyclotetrasilazane ((SiHEt-NMe).sub.4),
cyanopropylmethylcyclosilazane (SiMeNC(CH.sub.2).sub.3--NM,
tetraphenyldimethyldisilazane (SiMePh.sub.2--NH--SiMePh.sub.2),
dipheyl-tetramethyldisilazane ((SiMe.sub.2Ph).sub.2--NH),
trivinyltrimethylcyclotrisilazane
((CH.sub.2.dbd.CH--SiMe--NH).sub.3),
tetravinyltetramethylcyclotetrasilaz- ane
(CH.sub.2.dbd.CH--SiMe--NH).sub.4, and
divinyl-tetramethyldisilazane
(CH.sub.2.dbd.CH--SiMe.sub.2--NH--SiMe.sub.2--CH.dbd.CH.sub.2). In
those formulae, Me indicates a methyl group (CH.sub.3), Et
indicates an ethyl group (CH.sub.5), Pr indicates a propyl group
(C.sub.3H.sub.7), Oc indicates an n-octyl group
(n-C.sub.8H.sub.17), and Ph indicates a phenyl group
(C.sub.6H.sub.5).
[0091] Although it is sufficient to have source gases containing
Si, C and N, one for each kind, in the above-described example,
this is not restrictive. For example, a gas having N.sub.2,
C.sub.2H.sub.2 added to organic silane or a gas having N.sub.2
added to organic silazane may be used.
[0092] In the embodiments, the stopper layer 19 is provided in
interlayer insulating film to form a part of the bottom of the
second groove 14a. But, the stopper layer may be formed on the top
surface of the interlayer insulating film. FIG. 9A to FIG. 9D show
a fabrication process in this case.
[0093] In this case, first, a stopper layer 41 (SiCN-based film) is
formed on an interlayer insulating film 40 which has an wiring
layer 17 or the like and is covered with the first cap layer 18.
Next, a first opening 41a is formed in the stopper layer 41 as
shown in FIG. 9A by using the photolithography technique.
Subsequently, with the first opening 41a as a mask, the interlayer
insulating film 40 is etched, thus forming a hole 40a in the
interlayer insulating film 40 as shown in FIG. 9B.
[0094] Next, a second opening 41b is formed in the stopper layer 41
as shown in FIG. 9C by using the photolithography technique.
Subsequently, with the second opening 41b as a mask, the interlayer
insulating film 40 is etched. At this time, etching is stopped in
time before the interlayer insulating film 40 is not completely
etched. As a result, a trench hole 42 and a contact hole 43 are
formed as shown in FIG. 9D. Thereafter, copper burying, the
formation of the second cap layer 23 and so forth are executed to
provide the semiconductor device 11 as shown in FIG. 9E.
[0095] In the embodiments, silicon fluoride oxide is used for the
interlayer insulating film. But, the invention can also suitably
adapted to a case where a carbon fluoride film is used for the
interlayer insulating film Although the conductive layer that
constitutes wiring is formed of copper, it is not limited to copper
but aluminum or an alloy thereof or the like may be used.
[0096] In the embodiments, the SiCN-based film is deposited by ECR
plasma CVD. The film deposition method is not limited to this type,
but may be plasma CVD inductive coupled plasma (ICP) CVD, helicon
wave plasma CVD, parallel plate plasma CVD or the like.
INDUSTRIAL APPLICABILITY
[0097] The invention is useful for fabrication of a highly reliable
semiconductor device.
[0098] This application is based on Japanese Patent Applications
No. H12-274426 filed on Sep. 11, 2000 and No. H12-274427 filed on
Sep. 11, 2000, and including specification, claims, drawings and
summary. The disclosure of the above Japanese Patent Applications
is incorporated herein by reference in its entirety.
* * * * *