U.S. patent application number 10/387698 was filed with the patent office on 2004-02-05 for method and apparatus for integrated chemical mechanical polishing of copper and barrier layers.
Invention is credited to Basol, Bulent M., Talieh, Homayoun, Truong, Tuan, Wang, Yuchun, Young, Douglas W..
Application Number | 20040023607 10/387698 |
Document ID | / |
Family ID | 28046746 |
Filed Date | 2004-02-05 |
United States Patent
Application |
20040023607 |
Kind Code |
A1 |
Talieh, Homayoun ; et
al. |
February 5, 2004 |
Method and apparatus for integrated chemical mechanical polishing
of copper and barrier layers
Abstract
A method of polishing a plurality of layers on a surface of a
semiconductor wafer includes polishing a first layer using a
polishing solution on a first portion of polishing pad and
polishing another layer using a polishing solution on another
portion of polishing pad. The polishing solution used for each
layer is preferably suited to polish its respective layer. The
different portions of polishing pad, likewise, are preferably
suited to polish a corresponding wafer layer. The different
portions of polishing pad may be located on the same pad or on
different pads.
Inventors: |
Talieh, Homayoun; (San Jose,
CA) ; Basol, Bulent M.; (Manhattan Beach, CA)
; Young, Douglas W.; (Sunnyvale, CA) ; Wang,
Yuchun; (San Jose, CA) ; Truong, Tuan; (San
Jose, CA) |
Correspondence
Address: |
NuTool Inc.
Legal Department
1655 McCandless Drive
Milpitas
CA
95035
US
|
Family ID: |
28046746 |
Appl. No.: |
10/387698 |
Filed: |
March 13, 2003 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10387698 |
Mar 13, 2003 |
|
|
|
10346425 |
Jan 17, 2003 |
|
|
|
10387698 |
Mar 13, 2003 |
|
|
|
10199471 |
Jul 19, 2002 |
|
|
|
60417544 |
Oct 10, 2002 |
|
|
|
60365001 |
Mar 13, 2002 |
|
|
|
Current U.S.
Class: |
451/296 ;
257/E21.304 |
Current CPC
Class: |
B24B 49/16 20130101;
B24B 37/04 20130101; H01L 21/3212 20130101; B24B 21/04
20130101 |
Class at
Publication: |
451/296 |
International
Class: |
B24B 021/00 |
Claims
1. A method of polishing a plurality of layers on a surface of a
semiconductor wafer, the method comprising the steps of: polishing
a first layer using a polishing solution on a first portion of
polishing pad; and polishing another layer using a polishing
solution on another portion of polishing pad.
2. A method according to claim 1, wherein the polishing solution
used to polish the first layer is different from the polishing
solution used to polish the another layer.
3. A method according to claim 2, wherein the first layer is copper
and the polishing solution used to polish the first layer is
suitable for polishing copper and wherein the another layer is a
barrier layer and the polishing solution used to polish the another
layer is suitable for polishing the barrier layer.
4. A method according to claim 1, wherein the first portion of
polishing pad and the another portion of polishing pad are portions
located on different polishing pads.
5. A method according to claim 2, wherein the first portion of
polishing pad and the another portion of polishing pad are portions
located on different polishing pads.
6. A method according to claim 1, wherein the first layer is copper
and the first portion of polishing pad is suitable for polishing
copper and wherein the another layer is a barrier layer and the
another portion of polishing pad is suitable for polishing the
barrier layer.
7. A method according to claim 3, wherein the first layer is copper
and the first portion of polishing pad is suitable for polishing
copper and wherein the another layer is a barrier layer and the
another portion of polishing pad is suitable for polishing a
barrier layer.
8. A method according to claim 2, further comprising the step of
cleaning the polishing solution used to polish the first layer from
the wafer and the first portion of polishing pad before polishing
the another layer.
9. A method according to claim 8, further comprising the steps of:
supplying the polishing solution used to polish the first layer to
the first portion of polishing pad; and supplying the polishing
solution used to polish the another layer to the another portion of
polishing pad after the polishing solution used to polish the first
layer is cleaned off.
10. A method according to claim 1, wherein the polishing of the
first layer and the polishing of the another layer are performed
using reverse linear polishing and by moving a portion of polishing
pad with respect to a support platen, the support platen being used
to support the portion of polishing pad by supplying fluid to a
back side of the portion of polishing pad.
11. A method according to claim 1, further comprising the step of
polishing said first layer using another polishing solution.
12. A method of polishing a first and second layers on a surface of
a semiconductor wafer, the method comprising the steps of:
polishing said first layer using a first polishing solution on a
pad; and polishing said second layer using a second polishing
solution on the same said pad.
13. A method according to claim 12, further comprising the step of
cleaning said first polishing solution from said wafer and said pad
before polishing said second layer.
14. A method according to claim 13, wherein said first polishing
solution is cleaned off after an endpoint of said first layer is
reached.
15. A method according to claim 13, further comprising the steps
of: supplying said first polishing solution to said pad; and
supplying said second polishing solution to said pad after said
first polishing solution is cleaned off.
16. A method according to claim 13, wherein said second polishing
solution is cleaned off after an endpoint of said second layer is
reached.
17. A method according to claim 13, wherein said cleaning said
first polishing solution includes: raising said wafer from said
pad; rinsing said surface of said wafer with a rinsing solution;
removing excess rinsing solution after rinsing; and lowering said
wafer to said pad.
18. A method according to claim 12, wherein said polishing of first
and second layers is performed using reverse linear polishing.
19. A method according to claim 12, wherein said polishing said
first layer using said first polishing solution continues until a
first layer endpoint is reached; and wherein said polishing said
second layer using said second polishing solution continues until a
second layer endpoint is reached.
20. A method according to claim 12, further comprising polishing
said first layer using another polishing solution.
21. An integrated semiconductor wafer processing system including a
plurality of processing stations, comprising: a first polishing pad
to polish a first layer of a semiconductor wafer; and another
polishing pad to polish another layer of the semiconductor
wafer.
22. The integrated semiconductor wafer processing system of claim
21, further comprising: a first polishing solution line to deliver
a polishing solution to the first polishing pad; and another
polishing solution line to deliver a polishing solution to the
another polishing pad.
23. The integrated semiconductor wafer processing system of claim
22, wherein the polishing solution delivered to the first polishing
pad is different from the polishing solution delivered to the
another polishing pad.
24. The integrated semiconductor wafer processing system of claim
23, wherein the first polishing pad is a fixed abrasive polishing
pad and the polishing solution delivered to the first polishing pad
includes abrasive particles.
25. The integrated semiconductor wafer processing system of claim
21, wherein the another polishing pad is a polymeric polishing pad
without fixed abrasives.
26. The integrated semiconductor wafer processing system of claim
23, wherein the polishing solution delivered to the another
polishing pad is a barrier layer removal slurry comprising: about
0.1% to about 5% abrasive particles; barrier removal chemical; and
a pH adjusting component, wherein the solution has a pH between 7
and 12.
27. The integrated semiconductor wafer processing system of claim
23, wherein the polishing solution delivered to the another
polishing pad is a slurry comprising: abrasive particles
concentration from about 1% to about 2%, wherein the abrasive
particles are selected from the group consisting of fumed silica,
colloidal silica and ceria; hydroxylamine; a corrosion inhibitor,
and a pH adjusting component selected from the group consisting of
KOH, NaOH, NH.sub.4OH and TMAH, wherein the solution has a pH
between about 9 and about 10.
28. The integrated semiconductor wafer processing system of claim
21, further comprising: a first CMP station which comprises the
first polishing pad; and another CMP station which comprises the
another polishing pad.
29. The integrated semiconductor wafer processing system of claim
21, wherein the first polishing pad and the another polishing pad
polish the wafer using reverse linear motion.
30. A chemical mechanical polishing device for polishing a surface
of a semiconductor wafer, comprising: a polisher that includes a
single pad that polishes a first layer and a second layer of the
surface of the wafer; and a polishing solution distribution system
providing a first polishing solution to said single pad for
polishing said first layer during a first interval and a second
polishing to solution to said single pad during a second interval
for polishing said second layer.
31. A chemical mechanical polishing device according to claim 30,
wherein said pad is a fixed abrasive pad.
32. A chemical mechanical polishing device according to claim 31,
wherein said first and second polishing solutions do not contain
any abrasive particles.
33. A chemical mechanical polishing device according to claim 31,
wherein said first and second polishing solutions contain less than
5% abrasive particles.
34. A chemical mechanical polishing device according to claim 30,
wherein the chemical mechanical device is a reverse linear chemical
mechanical polisher.
35. A chemical mechanical polishing device according to claim 30,
further comprising a system to clean the pad and the wafer between
the first and second intervals.
36. A chemical mechanical polishing device according to claim 30,
wherein said first layer comprises copper and said second layer
comprises tantalum.
37. A chemical mechanical polishing device according to claim 30,
wherein said first polishing solution comprises an oxidizer, a
complexing reagent, and a corrosion inhibitor and said second
polishing solution comprises a complexing reagent and a corrosion
inhibitor.
38. A chemical mechanical polishing device according to claim 30,
wherein the second polishing solution is a barrier layer removal
slurry comprising: about 0.1% to about 5% abrasive particles;
barrier removal chemical; and a pH adjusting component, wherein the
solution has a pH between 7 and 12.
39. A chemical mechanical polishing device according to claim 30,
wherein the second polishing solution is a slurry comprising:
abrasive particles concentration from about 1% to about 2%, wherein
the abrasive particles are selected from the group consisting of
fumed silica, colloidal silica and ceria; hydroxylamine; a
corrosion inhibitor, and a pH adjusting component selected from the
group consisting of KOH, NaOH, NH.sub.4OH and TMAH, wherein the
solution has a pH between about 9 and about 10.
40. A chemical mechanical polishing device according to claim 30,
wherein said single pad includes a first portion and a second
portion, said first portion suitable to polish said first layer and
said second portion suitable to polish said second layer.
Description
RELATED APPLICATIONS
[0001] This is a continuation-in-part U.S. Ser. No. 10/346,425
filed Jan. 17, 2003 (NT-278-US) and U.S. Ser. No. 10/199,471 filed
Jul. 19, 2002 (NT-258-US), all incorporated herein by
reference.
[0002] This application claims priority to U.S. Prov. No.
60/417,544 filed Oct. 10, 2002 (NT-278-P2) and U.S. Prov. No.
60/365,001 filed Mar. 13, 2002 (NT-237-P), all incorporated herein
by reference.
FIELD
[0003] The invention relates to the field of chemical mechanical
polishing. More particularly, the invention relates to a method and
apparatus for integrated polishing of both copper and barriers
layers.
BACKGROUND
[0004] Conventional semiconductor devices generally include a
semiconductor substrate, usually a silicon substrate, and a
plurality of sequentially formed dielectric interlayers such as
silicon dioxide and conductive paths or interconnects made of
conductive materials. Copper and copper alloys have recently
received considerable attention as interconnect conductor because
of their superior electromigration and low resistivity
characteristics. The interconnects are usually formed by filling
copper in features or cavities etched into the dielectric
interlayers by a metallization process. The preferred method of
copper metallization process is electroplating. In an integrated
circuit, multiple levels of interconnect networks laterally extend
with respect to the substrate surface. Interconnects formed in
sequential interlayers can be electrically connected using vias or
contacts.
[0005] In a typical process, first an insulating interlayer is
formed on the semiconductor substrate. Patterning and etching
processes are performed to form features such as trenches, vias or
dual damascene structures in the insulating layer. Then, copper is
electroplated to fill all the features. However, the plating
process results in a copper layer within the features, as well as
on the substrate surface. The excess copper overburden on the
surface is then removed before the subsequent processing step.
[0006] Conventionally, after patterning and etching, the insulation
layer is first coated with a barrier layer, typically, a tantalum
or tantalum/tantalum nitride composite layer. The barrier layer
coats the vias and the trenches as well as the top surface of the
insulation layer to ensure good adhesion and acts as a barrier
material to prevent diffusion of the copper into the semiconductor
devices and through the insulation layer. Next a seed (conductive)
layer, which is often a copper layer, is deposited on the barrier
layer. The seed layer forms a conductive material base for copper
film growth during the subsequent copper deposition. As the copper
film is electroplated, the copper layer quickly fills the vias but
coats the wide trench and the surface in a conformal manner. When
the deposition process is continued to ensure that the trench is
also filled, a thick copper layer or overburden is formed on the
substrate. Conventionally, after the copper plating, a CMP
(Chemical Mechanical Polishing) process is employed to globally
planarize and reduce the thickness of the copper layer down to the
level of the surface of the barrier layer. To electrically isolate
the copper filled features, the barrier layer is then removed by
another CMP step.
[0007] Chemical mechanical polishing (CMP) of semiconductor wafers
for VLSI (Very Large Scale Integration) and ULSI (Ultra Large Scale
Integration) applications has important and broad application in
the semiconductor industry. CMP is a semiconductor wafer flattening
and polishing process that combines chemical removal of layers such
as insulators and metals with mechanical buffering of a wafer
surface. CMP is also used to flatten/polish wafers after crystal
growing and during the wafer fabrication process, and is a process
that provides global planarization of the wafer surface. For
example, during the integrated circuit fabrication process, CMP is
often used to flatten/polish the profiles that build up in
multilevel metal interconnection schemes. Achieving the desired
flatness of the wafer surface must take place without contaminating
the desired surface. Also, the CMP process must avoid polishing
away portions of the functioning circuit parts.
[0008] Conventional systems for the chemical mechanical polishing
of semiconductor wafers will now be described. One conventional CMP
process requires positioning a wafer on a holder rotating about a
first axis and lowered onto a polishing pad rotating in to the
opposite direction about a second axis. The wafer holder presses
the wafer against the polishing pad during the planarization
process. A polishing solution such as a polishing agent or slurry
is typically applied to the polishing pad during the polishing of
the wafer. The content of the polishing solution depends on the
nature of the material to be removed during the CMP. For example,
if the material is metallic, the polishing solution may be composed
any one or more of abrasives, oxidizers, complexing reagents
(etching chemicals), inhibitors and/or surfactants. The oxidizer in
the polishing solution oxidizes the surface of the metallic
material while the oxidized metallic material is removed chemically
and mechanically by abrasion due to the friction with the pad or
the abrasive powder or both. Etching chemicals can be used to
increase the polishing rate of the metallic material.
[0009] In another conventional CMP process, a wafer holder
positions and presses a wafer against a belt shaped polishing pad
while the pad is moved continuously in the same linear direction
relative to the wafer. The so called belt shaped polishing pad is
movable in one continuous path during this polishing process. These
conventional polishing processes may further include a conditioning
station positioned in the path of the polishing pad for
conditioning the pad during polishing. Factors that need to be
controlled to achieve the desired flatness and planarity may
include polishing time, pressure between the wafer and pad, speed
of rotation, slurry particle size, polishing solution feed rate,
the chemistry of the polishing solution, and pad material.
[0010] Although the CMP processes described above are widely used
and accepted in the semiconductor industry, challenges remain. Due
to the differences in the properties of materials used for copper,
barrier and other layers which need to be subjected to polishing,
conventional systems often include different polishing solutions
and different types of polishing pads for the differing layers.
This often means that a copper layer must be polished using one pad
while a barrier layer must be removed using an entirely different
pad. Also, the differences in pad materials and polishing solution
composition may cause unintended side effects such as erosion and
dishing into layers other than the one being polished. This
increases the time, cost, defect rate and complexity in the
polishing process.
[0011] Specifically, the art of polishing has attempted to solve
the problem of polishing a copper layer above a barrier layer of
tantalum. It should be noted that all descriptions made with
reference to Ta-barrier is applicable to a TaN barrier and to a
Ta/TaN stack.
[0012] The CMP tools of prior art are complex and expensive
machines. An integrated polishing method and apparatus that serves
to effectively polish both tantalum and copper to reduce the cost
and complexity and shorten the time required for the polishing of a
semiconductor wafer is needed.
SUMMARY
[0013] The invention overcomes the identified limitations with
conventional chemical mechanical polishing and provides a technique
for polishing multiple layers of a workpiece.
[0014] In one or more embodiments of the invention, a plurality of
layers of a semiconductor wafer is polished using the same pad.
This is achieved by supplying different polishing solutions when
polishing each layer of a differing composition. In one embodiment,
a copper layer is first polished using a first polishing solution
delivered to the pad. Afterwards, a barrier layer of the same wafer
is polished using a second polishing solution delivered onto the
same pad. After each layer is polished, both the pad and/or wafer
may be cleaned by using a rinse with or without a subsequent blow
or spinning process to remove excess solution. In an alternate
embodiment, the copper and barrier layer removal may be performed
in an integrated CMP system using multiple polishing pads or
multiple portions of a single polishing pad. Further, multiple
polishing solutions may be combined with multiple polishing pads to
optimize polishing efficiency.
[0015] In other embodiments of the invention, a plurality of layers
of a semiconductor wafer is polished using different polishing
solutions in different CMP stations. In one embodiment, a copper
layer is first polished using a first polishing solution delivered
to a pad in a first CMP station. Afterwards, a barrier layer of the
same wafer is polished using a second polishing solution in a
second CMP station.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1A illustrates a cross-section of a semiconductor wafer
before depositing a copper layer on it;
[0017] FIG. 1B illustrates a cross-section of the semiconductor
wafer shown in FIG. 1A, wherein a planar conductive layer has been
deposited on top of the wafer;
[0018] FIG. 1C illustrates a cross-section of the semiconductor
wafer in FIG. 1B after polishing the copper layer in accordance
with one or more embodiments of the invention;
[0019] FIG. 1D illustrates a cross-section of layers of the
semiconductor wafer in FIG. 1C after polishing the barrier layer in
accordance with one or more embodiments of the invention;
[0020] FIG. 1E is a flowchart of one or more embodiments of the
invention which use two different polishing solutions on the same
pad;
[0021] FIG. 1F is a flowchart of one or more embodiments of the
invention which use three different polishing solutions on the same
pad;
[0022] FIG. 2 illustrates a cross-section of the semiconductor
wafer shown in FIG. 1A, wherein a thick conductive layer has been
deposited on top of the wafer;
[0023] FIG. 3 is a flowchart of at least one embodiment of the
invention using separate polishing solution lines;
[0024] FIG. 4 is a flowchart of at least one embodiment of the
invention using separate polishing solution lines;
[0025] FIG. 5 is a flowchart of at least one embodiment of the
invention using a component line and oxidizer line;
[0026] FIGS. 6A-B illustrate a side view and a plan view of a
polishing station configured in accordance with one or more
embodiments of the invention;
[0027] FIGS. 7A-B illustrate a detailed view of wafer polishing
using a single pad according to one or more embodiments of the
invention;
[0028] FIG. 8 depicts a block diagram of an integrated CMP system
having multiple CMP stations, according to one or more embodiments
of the invention; and
[0029] FIG. 9 is a flowchart of an embodiment of method of
polishing copper and barrier layers of a semiconductor wafer using
an integrated CMP system having multiple CMP stations, such as the
CMP system described with reference to FIG. 8.
DETAILED DESCRIPTION
[0030] The invention is directed to a method and apparatus for
chemical mechanical polishing of multiple layers of a workpiece
such as a semiconductor wafer. The various techniques described
herein may involve a single polishing pad or multiple polishing
pads. Additionally, the techniques may involve a single polishing
solution or multiple polishing solutions. Further, a single portion
of a polishing pad or multiple portions of a single polishing pad
(each portion having a different composition) may be utilized. The
term "polishing pad" is interchangeable with the terms "polishing
member" and "polishing belt". The terms "wafer", "semiconductor
wafer", "workpiece", and "substrate" are interchangeable.
[0031] In one embodiment, a first type of polishing solution is
supplied for polishing a first layer such as a copper layer. Once
the endpoint of the copper layer is reached, the supply of the
first type of polishing solution is stopped and the wafer and the
pad are rinsed. In the context of this application, the endpoint
can be described as having been achieved when a given layer is
removed from the top of the underlying layer and the underlying
layer is exposed. A second type of polishing solution is then
supplied for polishing a second layer such as a barrier layer on
the same pad. In another embodiment a first type of polishing
solution is supplied on the pad to polish the copper layer
partially at high speed. A second type of polishing solution is
then supplied to remove the rest of the copper layer. Yet a third
type of polishing solution is subsequently used to remove the
barrier layer.
[0032] With respect to the polishing solution used, the polishing
solution can be either various polishing agents without abrasive
particles or slurries with abrasive particles, depending upon the
type of pad used for polishing and the desired type of polishing.
For example, the polishing pad can contain abrasives embedded in
the front side of the pad with polishing agents that do not contain
abrasive particles being introduced, or can use a polishing pad
that does not contain such embedded abrasives and instead uses a
slurry, or can use some other combination of belt, slurry and/or
polishing agents. The polishing solution may include a chemical
that oxidizes the material that is then mechanically removed from
the wafer, as is described further hereinafter, as well as may
contain abrasive particles made from colloidal silica or fumed
silica. The polishing agent or slurry generally grows a thin layer
of silicon dioxide or oxide on the front surface of the wafer, and
the buffering action of the pad mechanically removes the oxide. As
a result, high profiles on the wafer surface are removed until an
extremely flat surface is achieved.
[0033] Referring back to the first embodiment, after reaching the
endpoint of the copper layer polishing, supply of the first type of
polishing solution is discontinued so that polishing of the barrier
layer commences with the second type of polishing solution. All of
these and other embodiments use the same pad to polish both copper
and barrier layers. The apparatus for performing these and other
embodiments couple and control the necessary polishing solution
lines in tandem. In an aspect of the invention, polishing solution
lines are embodied in a polishing solution distribution system.
[0034] In discussing the invention, various references will be made
to specific copper layers, barrier layers, polishing solutions,
pads and other components. Such reference is by way of illustration
only as it should be readily understood that any form, manner and
type of layers, polishing solutions, pads and other components can
be substituted as appropriate for the desired application,
polishing system and/or wafer. For instance, in the description,
both the deposited copper layer and the underlying seed layer are
often referred to as the copper layer while the barrier layer is
referred to as the tantalum layer. Such description depends on the
composition of the wafer used and the layers currently being
processed and should not be considered to limit the invention in
any manner.
[0035] Also, in describing the invention, references to the "same
pad" may also include different sections of one pad and in all
instances "same type of pad" refers to a similar composition of pad
throughout the pad's various sections, if any. Like reference
numerals will be used to designate like elements and like
structures when describing the various figures.
[0036] FIG. 1A illustrates a portion of an exemplary substrate 11
that usually includes a silicon wafer. The illustrated portion of
substrate 11 includes a patterned insulating layer 14 or field
comprising a dielectric material. Cavities 16 or features such as
trenches and vias are formed in the insulating layer 14 by etching
away portions of the insulating layer using well known techniques.
The features 16 may expose portions of the substrate surface. A
barrier layer 15 such as Ta or TaN or Ta/TaN stacked layer is
formed in the cavities 16 and on top surface 17 of the insulating
layer or field surface. The barrier layer may have a thickness on
the order of 200-300 .ANG.. Although it is not shown in the FIGS.
1a-1e, the barrier layer 15 is lined with a thin copper seed layer
to initiate copper growth on the barrier layer. A planar conductive
layer 12, such as a copper layer, is formed, using an ECMD
(Electrochemical Mechanical Deposition) process, over the copper
seed layer. For example, the thickness of the copper layer 12 is
about 1000 .ANG..
[0037] FIGS. 1B exemplifies a beginning substrate having a planar
copper layer that is produced using an ECMD process. An example
ECMD process is disclosed in U.S. Pat. No. 6,176,992 entitled
"Method and apparatus for electro-chemical mechanical deposition"
issued Jan. 23, 2001 and commonly owned by the assignee of the
present application. Use of a substrate with a planar copper layer
as a beginning substrate is just for the purpose of
exemplification. The inventive process, as will be shown in FIG. 2,
can also use beginning substrates having a thick conformal copper
layer that is produced using a conventional electrodeposition
process such as ECD (Electro Chemical Deposition) and is within the
scope of the present invention.
[0038] FIGS. 1C and 1D exemplify later stages of the polishing
process of such beginning samples that are shown in FIGS. 1B and 2.
The polishing process of the present invention uses a single
polishing belt or pad (abrasive or non-abrasive) throughout the
polishing process.
[0039] In accordance with the invention, the barrier layer 15 and
copper layer 12 are polished using the same polishing pad or belt
(not shown). The pad first polishes and removes copper layer 12
from the wafer 11 until reaching its "endpoint" and then removes
the barrier layer 15 up to its "endpoint". For purposes of
describing the various embodiments of the invention, the endpoint
of the copper layer 12 may be defined as the first instance along
the layer 12 when the barrier layer 15 is reached during polishing.
Likewise, the endpoint of the barrier layer 15 may be defined as
the first instance at which the top 17 of field 14 is reached
during polishing. It should be noted that after the endpoint for
copper and barrier removal, a predetermined amount of over-polish
may be carried out in either or both cases to eliminate any
possible residues of materials on the wafer surface. The copper
layer 12 is polished by a pad (not shown) by delivering onto the
pad a first type of polishing solution (described below). The
chemical reactions in the first type of polishing solution in
conjunction with the mechanical abrasive action of the pad upon
copper layer 12 removes copper layer 12. The removal of copper
layer 12 occurs until its endpoint is reached, which is defined as
the start of barrier layer 15 beneath it. The resulting wafer 11 is
shown in FIG. 1C. The barrier layer 15 and the features 16 remain
while the copper layer 12 has been removed up to level of the
barrier layer 15.
[0040] After polishing the copper, the wafer surface and the pad
surface are briefly cleaned using a cleaning fluid such as water.
When cleaning, the wafer surface and the pad surface may or may not
be separated, but if separated the wafer surface and the pad
surface can then be separately cleaned, and this type of cleaning
can be done in cleaning referred to hereafter. After cleaning, the
wafer surface may or may not be spun to remove excess solution, but
the excess solution on the pad is preferably blown off making its
surface ready to receive a different chemistry. At this point, a
second type of polishing solution may be disposed onto the same
pad. Then, using the second type of polishing solution, barrier
layer 15 is polished until the top surface 17 of the field 14 is
reached. This polishing action creates a planarized surface of the
wafer 11, as shown in FIG. 1D. Each of the features 16 are now
electrically isolated from one another and the top surface is flat
and planar for future processing. FIG. 1E is a flowchart of one or
more embodiments of the invention. In the chemical mechanical
polishing process 10 of semiconductor wafers, an individual wafer
(or even, a group of wafers if a parallel polishing system is
implemented) must first be positioned for polishing (block 100) on
the pad. The positioning may be achieved by means of a carrier head
or housing, which positions a wafer in a close proximity to the
polishing pad (see FIG. 6A). Next in process 10, a first type of
polishing solution is supplied for copper layer polishing (block
110). During the process, the first type of chemical polishing
solution is disposed between the copper layer 12 and the polishing
pad so as to chemically and mechanically polish the copper while
the wafer is pressed against the pad. As the wafer is pressed
against the polishing pad, the movement of the polishing pad
relative to the wafer provides the mechanical action on the copper
surface 12.
[0041] This mechanical action in combination with the chemical
reaction of the polishing solution polishes the copper surface.
Rotation of the carrier head assists in the polishing solution
delivery and as well as in obtaining uniform polishing rates across
the copper layer. Chemical mechanical polishing with the first type
of polishing solution (which is particularly well suited to the
polishing of copper) continues until the endpoint of the copper
layer 12 is reached (checked at block 120). Once the copper layer
12, end-point is reached (once the barrier layer 15 has been
exposed), and optional over-polish is done, the first type of
polishing solution is cleaned off (block 130). The cleaning of the
polishing solution off the pad may be achieved using a high
pressure rinse with DI water and/or air blow method (see below).
Also, the wafer 11 itself may separately be cleaned by rinsing with
DI water and then have the DI water removed by spinning the wafer,
with the wafer typically still being wet, but not having excess DI
water disposed thereon.
[0042] Once the polishing solution of the first type is cleaned
off, a second type of polishing solution, one that is better suited
to polishing of the barrier layer than the first type of polishing
solution, is supplied for barrier layer 15 polishing (block 140).
The second type of polishing solution is disposed on the polishing
pad and the polishing of the barrier layer is performed. The
polishing of the barrier layer using the second type of polishing
solution continues until the endpoint of the barrier layer 15 is
reached (checked at block 150). Once the barrier layer endpoint is
reached (once the top surface 17 of the field region 14 is
reached), the second type of polishing solution is switched off
(block 160). Removal of the polishing solution from the pad may be
achieved by a high pressure rinse and/or air blow method similar or
identical with that used to clean off the first type of polishing
solution. The wafer 11 is then rinsed and spun top remove excess
solution.
[0043] The chemical mechanical polishing of the wafer 11 is
considered complete and the wafer is ready for the next processing
step. The next wafer (or group of wafers) can then be loaded (block
170). The process 10 then repeats with the new wafer (or group) in
accordance with blocks 100 through 160.
[0044] In one embodiment, a novel feature of the invention is that
the same pad is used for both the copper and barrier layers 12 and
15, respectively. Furthermore, a cleaning step is performed in
between to avoid complications of non-compatibility between a first
polishing solution and a second polishing solution. The types of
pads available for such polishing may vary widely. Such pads
include fixed abrasive pads and nonabrasive pads, depending on the
desired polishing effect and chemical solution used. Either pad may
be used for polishing both the copper and barrier layers, but in
each case, the composition of the polishing solutions used may or
not be the same.
[0045] In the example of process 10, the copper layer 12 may be a
planar copper film. Note that in this context, "planarized thin"
copper film may indicate a film that is planar with a thickness on
the order of less than 3000 angstroms. The polishing pad may be a
fixed abrasive type pad such as MWR66 pad from 3M Corporation. For
such a fixed abrasive pad, the polishing solution for polishing
copper could be an abrasive free solution such as the CPS-08
solution also from 3M Corporation, although a solution with an
abrasive therein can also be used. In order to polish tantalum on
the same pad, a modified polishing solution available from EKC
(Polishing solution 9030) together with a reduced abrasive of 2% or
less (down from the typical 5%) may be used, although other
polishing solutions, with or without abrasives can be used. The
modification of the EKC 5 solution includes an increase in the pH
of the solution from 4.0 to 5.5. The increased pH may be achieved,
for instance, by adding ammonium hydroxide or hydroxylamine. If the
pad used is to be a regular polymeric pad, such as Thomas West 711,
then the same polishing solutions, CPS-08 solution and a modified
EKC with 2% abrasive, for copper and tantalum, respectively, can
still be used. One advantage of using a small amount of to abrasive
(2% rather than 5%) is that the by products left on the pad can be
cleaned relatively easily. A very high abrasive content can cause
handling problems in terms of slurry left on the pad. If particles
and chemicals cannot be cleaned off the pad properly, it may affect
the copper polishing step that follows the barrier polishing step.
Further, a polishing solution with no abrasive particles can also
be used with a nonabrasive 15 polymeric pad in situations where the
polishing solution is very active.
[0046] The above process can also be performed using more than two
polishing solutions, for example using two different polishing
solutions for the copper polishing and one polishing solution for
the barrier layer polishing. This process can also be implemented
using the CMP apparatus shown in FIGS. 6A-B. FIG. 1F is a flowchart
20 describing a CMP process embodiment using three polishing
solutions on the same pad. In the chemical mechanical polishing
process 70 of semiconductor wafers, an individual wafer (or even, a
group of wafers if a parallel polishing system is implemented) must
first be positioned for polishing (block 700) on the pad as
described above. Next in process 70, a first type of copper
polishing solution is supplied for fast copper layer polishing
(block 710). Chemical mechanical polishing with the first type of
copper polishing solution (which rapidly polishes the copper)
continues until the endpoint of the copper layer 12 is reached
(checked at block 720). The first type of copper polishing solution
is turned off and subsequently the cleaning of the wafer and the
pad is carried out (block 730). The cleaning of the polishing
solution from the pad is achieved using a high pressure rinse with
DI water and/or air blow method Block. Also, the wafer 11 itself
may be cleaned by rinsing with DI water and then spinning the
wafer. After the use of first type of copper polishing solution, a
second type of copper polishing solution is delivered onto the pad
to remove the remaining copper residues left on the barrier layer
that is on the top surface of the field (block 740). Alternately,
the first polishing step may be timed to remove most of the copper
using the first type of copper polishing solution, leaving behind
only 500-2000 angstrom thick layer, which is then polished off
using the second type of copper polishing solution. The second type
of copper polishing solution typically has a lower polishing rate
than the first type of copper polishing solution, and it leaves
behind a smoother copper surface with less number of defects.
[0047] Once the second type of copper polishing solution is turned
off and cleaned off (block 750), a third type of polishing solution
for the polishing of the barrier layer 15 is delivered on the pad
(block 760) and the polishing of the barrier layer is performed.
The polishing of the barrier layer using the third type of
polishing solution continues until the endpoint of the barrier
layer 15 is reached (checked at block 770). Once the barrier layer
endpoint is reached (once the top surface 17 of the field region 14
is reached), the third type of polishing solution is turned off,
and the pad and the wafer are cleaned (block 780). Removal of the
remains of the polishing solution from the pad may be achieved by a
high pressure rinse with DI water and following air blow method
similar or identical with that used to clean off the copper
polishing solutions. The wafer 11 may also be rinsed and spun. With
barrier removed, the chemical mechanical polishing of the wafer 11
is considered complete and the wafer ready for the next processing
step. The next wafer (or group of wafers) can then be loaded (block
790). The process 70 then repeats with the new wafer (or group) in
accordance with blocks 700 through 790 shown in FIG. 1F. As seen
from the given description, in this approach, the same pad is used
to remove both the copper 12, and the barrier 15, layers by using
multiple polishing solutions. As in the previous approach fixed
abrasive pads and regular pads or polymeric pads can be used for
this purpose. Either pad may be used for polishing both the copper
and barrier layers, but in each case, the composition of the
polishing solutions used may or not be the same.
[0048] In the example of process 70, the polishing pad may be a
fixed abrasive type of pad such as MWR66 pad from 3M Corporation.
The first type of copper polishing solution may be an abrasive free
solution with high removal rate, such as the CPS-11 solution also
from 3M Corporation. The copper removal rate of the CPS-11 solution
is approximately 4000 .ANG. per minute at about 1 psi of pressure
applied to the wafer surface by the pad. After polishing with the
CPS-11, there maybe some copper residues left on the barrier layer
or certain thickness of copper may be intentionally left on the
surface. Such residues may be polished off using the second type of
copper polishing solution that should work mainly on the remaining
residues but should have minimum etching effect on the copper that
is in the features. This way dishing may be minimized.
[0049] The second type of copper polishing solution may be an
abrasive free solution with low copper removal rate, such as the
CPS-12 solution from 3M Corporation. The copper removal rate of the
CPS-12 solution is approximately 1000 .ANG. per minute and removes
copper residues from the top of the barrier layer. In order to
polish tantalum on the same pad, the modified polishing solution
available from EKC together with a reduced abrasive of 2% or less
may be used as discussed before. As in the previous case, the
modification of the EKC solution includes an increase in the pH of
the to solution from 4.0 to about 5.5. The increase of pH may be
achieved, for instance, by adding ammonium hydroxide or
hydroxylamine. Again, if the pad used is to be a regular polymeric
pad, such as Thomas West 711, then the same polishing solutions,
CPS-11, CPS-12 and a modified EKC with 2% abrasive, for copper and
tantalum polishing, respectively, can still be used. FIG. 2
illustrates another beginning substrate to exemplify the process of
the present invention. FIG. 2 exemplifies a beginning substrate 11'
having a conformal copper layer that may be produced using a
conventional electrodeposition process such as ECD (Electro
Chemical Deposition). FIG. 2 illustrates a portion of an exemplary
substrate 11' that usually includes a silicon wafer. The
illustrated portion of substrate 11' includes a patterned
insulating layer 14' or a dielectric material. Cavities 16' or
features such as trenches and vias are formed in the insulating
layer 14' by etching away portions of the insulating layer using
well known techniques. A barrier layer 15' such as Ta or TaN or
Ta/TaN stacked layer is formed in the cavities 16' and on top
surface 17' of the insulating layer 14'. The barrier layer may have
a thickness on the order of 100-300 .ANG. or even less. Although it
is not shown, the barrier layer 15' is lined with a thin copper
seed layer to initiate copper growth on the barrier layer.
[0050] Copper layer 12' is formed, using a conventional conformal
deposition process, over the copper seed layer. For example in a
typical semiconductor device, the conductive layer 12' is formed by
depositing copper to a thickness that is about 1.5-2.00 times the
depth of the features 16'. In accordance with the principles of the
present invention, the copper layer 12' and the barrier layer 15'
of the wafer 11' may be polished away using the above or below
described embodiments as in the case of polishing the wafer 11 with
planar copper layer 12. Various stages of the polishing process
also progresses as exemplified in FIGS. 1C and 1D above. For the
purpose of clarification, the following embodiments will be
described in connection with the FIGS. 1A-D for the case of
polishing planar copper layer and the underlying Ta-barrier layer.
However, the same embodiments can be applied to the copper layer
12' and the underlying Ta barrier layer described in connection
with FIG. 2. The only difference is the thickness of the copper
layer in the latter case, in which the described processes may take
more time than the polishing of the thinner planar layer.
Considering the difference between the thicknesses of copper layers
in FIGS. 1B and 2, it will be appreciated that a processing
approach shown in FIG. 3 using two different polishing solutions
would be better suited for processing the thin copper layer and the
barrier layer of FIG. 1B, and a processing approach using three
polishing solution chemistries would be more appropriate for the
removal of the thicker copper layer and barrier layer of FIG. 2.
Alternately, two polishing solutions may be used for the thicker
copper, but pressure on the wafer may be increased to increase the
removal rate of the first solution until a certain thickness of
copper (such as two thirds) is removed. Then the pressure may be
reduced, still using the first solution to remove the remaining
copper. The second solution is then used to polish the barrier
layer.
[0051] FIG. 3 is a flowchart of at least one embodiment of the
invention using separate polishing solution lines. Process 20 is
one way of implementing process 10 (of FIG. 1E) using two separate
polishing solution lines. A wafer (or group of wafers) is
positioned for polishing (block 200). Then, a first polishing
solution line, polishing solution line #1, is turned on in order to
supply polishing solution to the polishing pad (block 210), see
also FIGS. 6A-B. The polishing solution supplied by the polishing
solution line #1 (for instance, CPS-08) would be used to polish the
copper layer 12 down to its endpoint. The polishing solution line
#1 would be turned (kept) on until the copper endpoint is reached
(checked at block 220). Once the copper endpoint is reached,
polishing solution line #1 is turned off (block 230). In order to
clean the pad off the polishing solution from line #1, the head
holding the wafer may be lifted above the pad and a de-ionized (DI)
water rinse is applied to the wafer which then bounces off the
wafer surface and falls onto the pad (block 235). Also, the wafer
11 is spun and, if desired, excess solution removed by blowing a
fluid such as air (block 235).
[0052] Once the pad and wafer 11 are cleaned, polishing solution
line #2 is turned on (block 240). The polishing solution supplied
by the polishing solution line #2 would be used to polish the
barrier layer 15 (such as tantalum) from the wafer. The polishing
solution line #2 would be turned (kept) on until the barrier layer
15 endpoint is reached (checked at block 250). Once the endpoint is
reached, polishing solution line #2 is turned off (block 255) in
order to clean the pad and wafer 11 of the polishing solution from
line #2, the head holding the wafer is now lifted above the pad and
a DI water rinse is applied to the wafer 11 (block 260). Then wafer
can be spun to remove excess solution. The water from the rinse
bounces off the wafer 11 and falls onto the pad thereby cleaning
it. Then the pad is blown to remove excess solution. Once the pad
and wafer 111 are cleaned, the next wafer (or group) is loaded
(block 270) and process 20 is repeated from block 200 on for the
newly loaded wafer(s).
[0053] FIG. 4 is a flowchart of at least one embodiment of the
invention using separate polishing solution lines. Process 30 is
another polishing process using the same pad and two separate
polishing solution lines. A wafer (or group of wafers) such as
wafer 11 is positioned for polishing (block 300). Then, both
polishing solution lines, polishing solution line #1 and polishing
solution line #2, are turned on in order to supply polishing
solution to the polishing pad (block 310), see also FIGS. 6A-B. The
components supplied by the polishing solution lines 1 and 2 would
be used to polish the copper layer 12 from the wafer 11. The
polishing solution line #1 supplies an oxidizer (such as hydrogen
peroxide), a complexing reagent and inhibitor. Polishing solution
line #2 supplies a complexing reagent and inhibitor but no
oxidizer.
[0054] Complexing reagents include chemicals such as organic acids
and amines while the inhibitor is typically benzotriazole (BTA).
Complexing reagents work to increase the rate of etching/polishing,
while the inhibitor decreases this rate. The inhibitor settles in
the region of the features 16. The inhibitor protects the surface
of the copper in the features so that the complexing reagent does
not exceedingly polish into these regions. This helps to prevent
dishing by ensuring a low static etching rate of the polishing
solution even in the absence of mechanical action by the pad. Even
though both polishing solution lines are on, the components
supplied by polishing solution line #2 would not have adverse
impact on the polishing of copper since the components of each line
share many commonalties. There is thus limited chance of
interactions between the polishing solutions of the two lines. The
removal (polishing) rate of copper increases with the concentration
of oxidizer in the polishing solution and reaches a peak. The
removal of barrier layer material such as tantalum however, is less
dependent on oxidizer concentration and depends more upon
mechanical abrasion.
[0055] The above rinse step between copper and tantalum polishing
for the same wafer is to ensure minimum interaction between the two
types of the polishing solutions. However, if the two polishing
solutions are compatible, no rinse or clean is needed between
copper and tantalum polishing, that is, the same wafer is polished
all the way from copper to tantalum without a rinse step in
between, except that the polishing solution line is switched from
copper polishing solution to tantalum polishing solution. In
another option when single step polishing solution is used to
polish both copper and tantalum, the two polishing solutions can be
simplified into a single polishing solution line.
[0056] The polishing solution lines #1 and #2 would be turned
(kept) on until the copper endpoint is reached (checked at block
320). Once the endpoint is reached, polishing solution line #1 is
turned off (block 330). Since the polishing solutions in polishing
solution lines #1 and #2 are somewhat compatible, a DI rinse
cleaning and then spinning of the wafer or air blowing on the pad
to remove the previous solution and DI rinse are optional but may
not be needed. Polishing solution line #2 would thus remain on. The
polishing solution supplied by the polishing solution line #2 would
be used to polish the barrier (tantalum) layer 15 from the wafer
11. Once the tantalum endpoint is reached, polishing solution line
#2 is turned off (block 355). In order to clean the wafer of the
polishing solution from line #2, a Dl water rinse and subsequent
spinning to remove excess solution is applied (block 360). Once the
wafer and pad are cleaned, the next wafer (or group) is loaded
(block 370) and process 30 is repeated from block 300 on for the
newly loaded wafer(s).
[0057] FIG. 5 is a flowchart of at least one embodiment of the
invention using a component line and oxidizer line. Process 40 is
another polishing process using the same pad and two separate
lines, one containing polishing solution and the other, an
oxidizer. A wafer (or group of wafers) is positioned for polishing
(block 400). Then, both lines, the polishing solution line and
oxidizer line, are turned on in order to supply polishing solution
and oxidizer to the polishing pad (block 410). The components
supplied by the polishing solution line and the oxidizer line would
be used to polish the copper layer 12 from the wafer. The polishing
solution line supplies a complexing reagent and inhibitor. The
oxidizer line supplies an oxidizer such as hydrogen peroxide. The
removal (polishing) of copper increases with the increasing
oxidizer concentration and reaches a peak. The removal of tantalum
however, is less dependent on oxidizer concentration and depends
more upon mechanical abrasion.
[0058] The polishing solution line and oxidizer line would be
turned (kept) on until the copper endpoint is reached (checked at
block 420). Once the endpoint is reached, the oxidizer line is
turned off (block 430). Since the solutions in the polishing
solution and oxidizer lines are somewhat compatible, a DI rinse and
spin of the wafer and air blowing of the pad may not be needed. The
polishing solution line would still remain on. The polishing
solution supplied by the polishing solution line would then be used
to polish the tantalum layer down to its endpoint (the top of the
field). Once the tantalum endpoint is reached, polishing solution
line is turned off (block 455). Some over-polishing beyond the
endpoint may be used to clear possible residue. In order to clean
the wafer, a DI water rinse is applied to the wafer while the wafer
is spinning (block 460). This also impacts upon and cleans the pad.
Once the pad and wafer are cleaned, the next wafer (or group) is
loaded (block 470) and process 40 is repeated from block 400 on for
the newly loaded wafer(s).
[0059] FIGS. 6A-B illustrate a side view and a plan view of a
polishing station configured in accordance with one or more
embodiments of the invention. The wafer polishing station 50
includes a number of polishing components and a wafer housing 540
or wafer carrier head. The wafer housing 540 securely positions a
wafer 550 so that a front face 560 of the wafer is fully exposed.
The polishing station 50 includes a polishing pad 510 for polishing
the front face 560, a mechanism (not shown) for driving the
polishing pad 510 in a bi-directional linear or reciprocating
(forward and reverse) motion, and a support plate 520 for supplying
a fluid support to the back side of the pad 510 as the pad 510
polishes the exposed wafer surface 560. Bi-directional linear
motion is also known as reverse linear motion. The underside of the
polishing pad 510 may be additionally attached to a flexible but
firm material (not shown) for supporting the pad 510. The polishing
pad 510 is used to polish both copper and barrier (e.g. tantalum)
layers of face 560. The use of a single pad for both layers of
exposed wafer surface 560 eliminates the need for separate use of
multiple pads and also, perhaps, of multiple polishing stations.
The polishing pad 510 may be abrasive free such as a polymeric pad
or may be a fixed abrasive pad. Since tantalum and copper layers
have differing characteristics, if the same pad is to be used for
polishing both, different polishing solutions would have to be
used. It is noted that a bi-directional linear polisher as
described is preferably used as the polishing station 50, such as
described in U.S. Pat. No. 6,103,628 and U.S. patent application
Ser. No. 09/684,059, both of which are hereby expressly
incorporated herein by reference. When used as such, the polishing
pad is preferably a belt that has a portion of the belt in the
processing area that moves in a bi-directional direction, which may
or may not contain fixed abrasives thereon, and which is preferably
levitated in a polishing area above a platen support. Further, the
belt may be incrementally moved, so that the same belt, but a
different portion of the belt (which different portion may or may
not overlap with the previously used portion in the processing
area) is used at different times, which different times may or may
not be distinguished by the type of processing solution being
used.
[0060] Though the above-described type of polishing station is
presently preferred, the present invention, however, is not limited
to using such a polishing station. Rather, the processes described
herein can be used with other CMP polishing stations, including
those that use a linearly rotating belt, a stationary polishing pad
with a moving wafer, a rotating polishing pad that moves against a
stationary or rotating wafer, or others. Further, pads that are
thin with little rigidity, as well as pads that are thicker or more
rigid can be used, depending upon the desired effect. There may or
may not be supporting plates behind the pads.
[0061] The polishing solutions and rinsing solution used during the
polishing are preferably supplied to both sides of the polishing
station 50 that uses a bi-directional linear polisher by two or
more polishing solution lines, such as line #1 and line #2. In at
least one embodiment of the invention, polishing solution line #1
comprises a left-side supply line 512 and right side supply line
511. Similarly, polishing solution line #2 comprises a left-side
supply line 514 and right side supply line 513. Supply lines 511
and 513 supply the right side of the polishing station 50 while
supply lines 512 and 514 supply the left-side of the polishing
station 50. Although not shown in the FIGS. 6A-B and 7A-B, it will
be appreciated that the polishing station may have more than two
polishing solution lines such as line #3 (not shown) that is
similarly configured and furnished with separate supply lines as
the other lines #1 and #2. This configuration having the line #3
may be used with the embodiment described in connection with FIG.
1F. Alternately, the number of nozzles may be kept the same but
valves may be used to bring different polishing solutions through
the same nozzles. Various ways of achieving this are apparent to
those skilled in the art.
[0062] Polishing of the wafer 550 will now be described in
accordance with various embodiments of the invention. In one
embodiment, after the wafer 550 is loaded into housing 540 and
positioned over-polishing station 50, polishing solution line #1 is
turned on to supply polishing solution to the right and left sides
of the pad 510. In turning on polishing solution line #1, right
side supply line 511 and left side supply line 512 will be actively
providing polishing solution to the pad 510. Right side supply line
513 and left side supply line 514 would be off. The pad 510 is
driven by mechanism 530 and this motion, coupled with the chemical
reactiveness of the polishing solution from polishing solution line
#1 upon the surface 560 of wafer 550, serves to polish copper from
surface 560. It should be noted that for the system of FIGS. 6A and
6B the polishing solution delivery can also be coupled with the
motion of the pad. For example, polishing solution may be delivered
from nozzle 511 as the pad moves to the left and delivered from
nozzle 512 when the pad is moving to the right. In this way, the
delivered polishing solution is always moved towards the wafer by
the moving pad. Waste of polishing solution is minimized. Once the
copper endpoint is reached, the polishing solution line #1 will be
turned off. This entails cutting off or deactivating supply lines
511 and 512.
[0063] To remove the remaining polishing solution from the front
surface 560 of the wafer 550 and the pad 510, a de-ionized water
nozzle injects water to the wafer surface when the wafer is lifted
above the pad. The water is bounced off the wafer onto the pad
surface and cleans both the wafer and pad surface. Wafer may
preferably be rotated during this cleaning step. After water spray,
a blower 580 blows air onto the pad 510 to remove excess solution.
Next, polishing solution line #2 will be turned on, and thus right
side supply line 513 and left side supply line 514 would be
actively providing polishing solution to the right and left sides,
respectively, of pad 510. The polishing solution supplied in
polishing solution line #2 is designed for the polishing of the
barrier (e.g. tantalum) layer. The motion of pad 510 and polishing
solution from polishing solution line #2 against the surface 560
serves to polish tantalum from the surface 560 of wafer 550. Once
the tantalum endpoint is reached, polishing solution line #2 is
turned off (supply lines 513 and 514 are deactivated), the pad is
cleaned (using rinser 570) and excess solution is removed using
blower 580) and the next wafer is loaded into housing 540 for
polishing. Rinser 570 and blower 580 may be implemented in a
variety of ways including by use of high-pressure nozzles.
[0064] Exemplary types of polishing solutions and pads suitable for
such polishing have been discussed above. In some embodiments of
the invention, polishing solution line #1 would supply a complexing
reagent, an inhibitor and an oxidizer. Polishing solution line #2
would supply a complexing reagent and inhibitor, but no oxidizer or
very low concentration of oxidizer. In such embodiments, both
polishing solution lines #1 and #2 could be turned on (and hence
all four supply lines 511, 512, 513 and 514 would be on) during the
polishing of copper. After copper polishing, polishing solution
line #1 could be turned off, leaving active (on) only supply lines
513 and 514 of polishing solution line #2. In yet other
embodiments, polishing solution line #2 would carry the complexing
reagent and inhibitor while polishing solution line #1 would carry
just the oxidizer. Again, both lines #1 and #2 could be turned on
during copper polishing and then polishing solution line #1 could
be turned off for tantalum polishing.
[0065] FIGS. 7A-B illustrate a detailed view of wafer polishing
using a pad as described in the above embodiments. Referring back
to FIG. 1B wafer 11 that is to be polished has plurality of layers,
including a copper layer 12 and a barrier layer 15. Prior to
polishing, an exposed front face 645 will expose the copper layer
12 to polishing first. After the copper layer 12 has been polished,
the resulting wafer 11 will expose the barrier layer 15 laying
underneath (see FIG. 1C). The wafer 11 is positioned so that its
front face 645 abuts against the surface of a polishing pad
640.
[0066] With reference to FIG. 7A, which shows the polishing station
in polishing mode, the polishing solutions are supplied on both
sides of the polishing pad 640 by two polishing solution lines,
line #1 and line #2. In at least one embodiment of the invention,
polishing solution line #1 comprises a left side supply line 612
and right-side supply line 611. Similarly, polishing solution line
#2 comprises a left side supply line 614 and right-side supply line
613. Supply lines 611 and 613 supply the right-side of the
polishing pad 640 while supply lines 612 and 614 supply the left
side of the polishing pad 640.
[0067] In one embodiment, a polishing solution from line #1
containing a chemicals that oxidize and chemically mechanically
remove copper layer 12 of surface 645 is supplied between the wafer
11 and the polishing pad 640. After copper layer 12 is polished,
polishing solution line #1 is turned off. The wafer 11 is raised
above the pad 640 as shown in FIG. 7B. While the wafer 11 is in the
position shown in FIG. 7B, a deionized water rinse (containing
0-0.01% corrosion inhibitor) from rinser 670 cleans the polishing
solution from the wafer 11 and then cleans the polishing solution
from the pad 640 by bouncing off of the wafer 11 (upon its front
surface 645) and onto the pad. The water which cleans the pad may
remain on the pad which may adversely dilute the next polishing
solution. The blower 680 blows air onto the pad to minimize the
dilution of the next polishing solution.
[0068] After cleaning, the wafer 11 returns to the position shown
in FIG. 7A. Then polishing solution line #2 is turned on supplying
polishing solution to polish barrier layer 15, which becomes
exposed after copper layer 12 is polished off. The action of pad
640 together with polishing solution from polishing solution line
#2 acts to polish layer 15 from wafer 11. The wafer may then be
returned to the position of FIG. 7A for a final rinse to the wafer
11 and pad 640. In other embodiments of the invention, polishing
solution line #1 and polishing solution line #2 may be both turned
on initially. In such a case, polishing solution line #1 would
contain the same components carried by polishing solution #2 but
would also carry an additional oxidizer component. Both polishing
solution lines #1 and #2 would polish copper layer 12. After copper
layer 12 is polished, polishing solution line #1 is turned off
leaving polishing solution line #2 on. Polishing solution line #2,
which carries no oxidizer or very low concentration of oxidizer,
would polish barrier layer 15. In still other embodiments of the
invention, polishing solution line #2 would carry the components
for polishing (such as complexing reagent and an inhibitor) while
polishing solution line #1 carries only the oxidizer. Again, in
such a case, polishing solution lines #1 and #2 would be on during
the polishing of copper layer 12, and then the oxidizer line
(polishing solution line #1) would be turned off during polishing
of barrier layer 15 thereafter. When both lines are on in this
manner, good mixing on the pad of the oxidizer from polishing
solution line #1 and the components from line #2 would be needed in
order to ensure a uniform distribution of the whole solution on the
pad.
[0069] In one or more embodiments of the invention, the polishing
pad is described as being composed of one type, either fixed
abrasive or polymeric. In alternate embodiments of the invention,
it may be possible to also partition or section a single pad into
one or more fixed abrasive sections and one or more polymeric
sections. As each section of the pad is needed for best process
performance for chemical mechanical polishing of a specific layer
on the wafer, the pad may be advanced or retracted to place the
appropriate section of the pad in position to polish the wafer.
Thus, a fixed abrasive section could be used when polishing the
copper layer while a softer polymeric sections could be used in
polishing the barrier layer. The reciprocal motion and the specific
design of the preferred system in FIG. 6A allows such
flexibility.
[0070] As previously stated, the polishing techniques described
herein may be performed using a single polishing pad in a single
CMP station or using multiple polishing pads in multiple CMP
stations. As described above, in one embodiment, copper layer and
barrier layer removal may be performed in the same CMP station. In
the embodiment, removal of the copper layer may be performed before
barrier layer removal. According to this process sequence, in a
first step, bulk copper may be removed down to barrier layer using
a fixed abrasive polishing pad. In this copper removal step the
polishing solution may or may not contain particles. In a second
step, the fixed abrasive polishing pad may be used in combination
with a polishing solution with solid particles to remove the
remaining copper layer from the surface of the barrier layer while
a down force is applied to the workpiece. This downforce may be a
relatively low down force. Following these steps, the barrier layer
is removed. Removal of the barrier layer may utilize a portion of
the polishing pad that is made a soft polymer. That is, the
polishing pad may have one portion that has a fixed abrasive and a
second portion that is made of a soft polymer. A tantalum selective
polishing solution may be delivered to the polishing pad to remove
the barrier layer while a low down force is applied to the work
piece.
[0071] In another embodiment, removal of the copper and barrier
layers may be performed using an integrated CMP system (integrated
CMP tool) on separate polishing pads. In an embodiment of the
invention, the different pads are located in separate CMP stations
within the same one tool. An exemplary CMP station suitable for use
in the integrated CMP system is described above with reference to
FIG. 6A and also with reference to "Advanced Chemical Mechanical
Polishing System with Smart Endpoint Detection", U.S. Ser. No.
10/346,425 filed Jan. 17, 2003 (NT-278-US), incorporated herein by
reference. By incorporating multiple CMP stations into one
integrated tool it is possible to make improvements in differential
polishing of copper and barrier layers.
[0072] FIG. 8 depicts a block diagram of an integrated CMP system
800 having multiple CMP stations, according to an embodiment of the
invention. In the embodiment depicted, the integrated CMP system
800 has a first CMP station 810 and a second CMP station 820. In
the first CMP station 810, in a first polishing sequence, the
copper layer is removed using a first polishing pad (not shown) and
a first polishing solution. In one aspect of the invention, the
first polishing pad is a fixed abrasive polishing pad and the first
polishing solution contains abrasive and/or lubricating particles.
In this aspect, the abrasive particles may act as a lubricant for
polishing when combined with the fixed abrasive polishing pad.
Abrasive particles are solid particles in a slurry. During the
first polishing sequence, the wafer is lowered onto the first
polishing pad and the first polishing solution is delivered onto
the first polishing pad. The first polishing pad is moved over the
support plate (see FIG. 6A) while a fluid pressure is applied under
the first polishing pad. Once the copper layer is removed down to
the barrier layer on the surface of the wafer (see FIG. 1C), a
barrier layer removal process (second polishing sequence) is
performed in the second CMP station 820. The second CMP station 820
has a second polishing pad (not shown) and uses a second polishing
solution. The second polishing pad may be a polymeric/non-fixed
abrasive polishing pad. For example, the second polishing pad may
be made of a soft polymeric material such as polyurethane. In one
aspect of the invention, a selective polishing solution is used as
the second polishing solution during the barrier layer removal
process. In this aspect, the selective polishing solution is
delivered onto a polymeric polishing pad suitable for barrier
material removal and the pad is moved for polishing. A fluid
pressure may be applied under the second polishing pad. Using these
techniques may minimize the stress on the wafer and resulting
delamination. These techniques also may minimize dishing and
scratches. The use of two CMP stations in the integrated CMP system
is exemplary only. Integrated CMP systems with additional CMP
stations are also contemplated.
[0073] FIG. 9 is a flowchart of an embodiment of a method of
polishing copper and barrier layers of a semiconductor wafer using
an integrated CMP system having multiple CMP stations, such as the
CMP system described with reference to FIG. 8. At step 910, a first
layer of a semiconductor wafer is polished using a polishing
solution on a first portion of polishing pad. In one embodiment,
the first layer is comprised of copper. At step 920, a second layer
of the semiconductor wafer is polished using a polishing solution
on a second portion of polishing pad. In one embodiment, the second
layer is comprised of tantalum. It shall be understood that more
than two layers can be polished, and more than two portions of
polishing pad may be used. The polishing solutions used to polish
the different layers may be the same polishing solution or
different polishing solutions. The different portions of polishing
pad may be located on the same polishing pad or on different
polishing pads. The respective polishing solution and polishing pad
are preferably designed and/or suited for polishing a particular
layer of the wafer. For example, the solution and pad may be suited
to polish copper, or suited to polish a barrier layer, such as
tantalum.
[0074] In accordance with the present invention, only one wafer is
generally polished during a single time. Although the present
invention is adapted to polish a single wafer at one time, one
skilled in the art may modify the preferred embodiment of the
invention in order to polish multiple wafers at one time. It is to
be understood that in the foregoing discussion and appended claims,
the terms "wafer surface" and "surface of the wafer" include, but
are not limited to, the surface of the wafer prior to processing
and the surface of any layer formed on the wafer, including
oxidized metals, oxides, spun on glass, ceramics, etc. Further,
while the above discusses primarily the polishing of two layers,
one metal layer (such as copper) and barrier layer such as Ta, any
number and manner of to layers may be polished using the techniques
described herein such as a fixed abrasive pad by supplying number
of polishing solutions as appropriate for each of those layers. It
shall be understood that removing a layer from the surface of a
semiconductor wafer is synonymous with polishing a layer on the
surface of the semiconductor wafer. In the various methods
described herein, the terms "block" and "step" both refer to a
processing step.
[0075] Although various preferred embodiments of the present
invention have been disclosed for illustrative purposes, those
skilled in the art will appreciate that various modifications,
additions and/or substitutions are possible without departing from
the scope and spirit of the present invention as disclosed in the
claims.
* * * * *