U.S. patent application number 10/185403 was filed with the patent office on 2002-12-05 for si-rich surface layer capped diffusion barriers.
Invention is credited to Faust, Richard A., Hong, Qi-Zhong, Hsu, Wei-Yung, Lu, Jiong-Ping.
Application Number | 20020180044 10/185403 |
Document ID | / |
Family ID | 22536886 |
Filed Date | 2002-12-05 |
United States Patent
Application |
20020180044 |
Kind Code |
A1 |
Lu, Jiong-Ping ; et
al. |
December 5, 2002 |
Si-rich surface layer capped diffusion barriers
Abstract
A copper interconnect having a transition metal-nitride barrier
(106) with a thin metal-silicon-nitride cap (108). A transition
metal-nitride barrier (106) is formed over the structure. Then the
barrier (106) is annealed in a Si-containing ambient to form a
silicon-rich capping layer (108) at the surface of the barrier
(106). The copper (110) is then deposited over the silicon-rich
capping layer (108) with good adhesion.
Inventors: |
Lu, Jiong-Ping; (Dallas,
TX) ; Hsu, Wei-Yung; (Dallas, TX) ; Hong,
Qi-Zhong; (Dallas, TX) ; Faust, Richard A.;
(Austin, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
22536886 |
Appl. No.: |
10/185403 |
Filed: |
June 28, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10185403 |
Jun 28, 2002 |
|
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09645157 |
Aug 24, 2000 |
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60150996 |
Aug 27, 1999 |
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Current U.S.
Class: |
257/751 ;
257/E21.169; 257/E21.579; 438/627; 438/653 |
Current CPC
Class: |
H01L 21/76846 20130101;
H01L 21/76843 20130101; H01L 21/76856 20130101; H01L 21/76807
20130101; H01L 21/2855 20130101 |
Class at
Publication: |
257/751 ;
438/653; 438/627 |
International
Class: |
H01L 029/40; H01L
021/44; H01L 023/48 |
Claims
In the claims:
1. A method of fabricating a diffusion barrier, comprising the
steps of: forming a transition metal nitride film; and annealing
said transition metal nitride film in a silicon-containing ambient
to form a silicon-rich capping layer at a surface of said
transition metal nitride film.
2. The method of claim 1, wherein said transition metal nitride
film comprises TaN, TiN, WN or MoN.
3. The method of claim 1, wherein said annealing step is performed
using silane at a temperature on the order of 360.degree. C.
4. The method of claim 1, wherein said silicon-rich capping layer
has a thickness on the order of 5-20 .ANG..
5. A method of fabricating an integrated circuit, comprising the
steps of: forming a dielectric layer over a semiconductor body;
etching a trench in said dielectric layer; forming a transition
metal nitride over said dielectric layer including within said
trench; annealing said transition metal nitride in a
silicon-containing ambient to incorporate silicon in a surface of
said transition metal nitride to form a transition metal silicon
nitride capping layer at said surface of said transition metal
nitride; and forming a copper layer on said transition metal
silicon nitride capping layer.
6. The method of claim 5, wherein said transition metal nitride
film comprises TaN, TiN, WN or MoN.
7. The method of claim 5, wherein said annealing step is performed
using silane at a temperature on the order of 360.degree. C.
8. The method of claim 5, wherein said transition metal silicon
nitride capping layer has a thickness on the order of 5-20
.ANG..
9. The method of claim 5, wherein said annealing step is performed
using SiH4 or Si.sub.2H.sub.6.
10. The method of claim 5, wherein said annealing step is performed
using Si(CH.sub.3)4.
11. An integrated circuit, comprising: a dielectric layer; a
diffusion barrier layer located within said dielectric layer, said
diffusion barrier having a silicon-rich capping layer at a surface
thereof; a copper layer located adjacent said silicon-rich capping
layer.
12. The integrated circuit of claim 11, wherein said diffusion
barrier comprises a transition metal nitride.
13. The integrated circuit of claim 11, wherein said silicon-rich
capping layer comprises a transition metal silicon nitride.
14. The integrated circuit of claim 11, wherein said silicon-rich
capping layer has a thickness on the order of 5-20 .ANG..
15. The integrated circuit of claim 11, wherein said diffusion
barrier comprises TaN, TiN, WN or MoN.
16. The integrated circuit of claim 11, wherein said diffusion
barrier comprises WN.
Description
FIELD OF THE INVENTION
[0001] The invention is generally related to the field of
interconnect layers in semiconductor devices and more specifically
to diffusion barriers for copper interconnect layers.
BACKGROUND OF THE INVENTION
[0002] As the density of semiconductor devices increases, the
demands on interconnect layers for connecting the semiconductor
devices to each other also increases. Therefore, there is a desire
to switch from the traditional aluminum metal interconnects to
copper interconnects. Unfortunately, suitable copper etches for a
semiconductor fabrication environment are not readily available. To
overcome the copper etch problem, damascene processes have been
developed.
[0003] In a damascene process, the IMD is formed first. The IMD is
then patterned and etched. The barrier layer 14 and a copper seed
layer are then deposited over the structure. The barrier layer 14
is typically tantalum nitride or some other binary transition metal
nitride. The copper layer is the formed using the seed layer over
the entire structure. The copper is then chemically-mechanically
polished (CMP'd) to remove the copper from over the IMD 16, leaving
copper interconnect lines 18 as shown in FIG. 1. A metal etch is
thereby avoided.
[0004] Barrier layer 14 is required because copper has high
diffusivity into dielectrics. Unfortunately, conventional diffusion
barriers have limited wettability (adhesion) with copper. This
causes voids in the copper during the via fill and negatively
impacts the electromigration performance. Metal-silicon-nitrides
have better wetting properties. Unfortunately, current methods of
forming these metal-silicon-nitrides are difficult to perform and
result in a film having high resistivity.
[0005] Another approach is to combine a layer of TaN with a layer
of Ta. TaN provides good adhesion to FSG (fluorine-doped silicate
glass) but poor adhesion to copper. Ta provides a good adhesion to
copper but poor adhesion to FSG. Unfortunately, when the TaN/Ta
stack is used, fluorine dopants diffuse through the TaN to react
with the Ta to form TaF. TaF is volatile and tends to peel off.
Thus, an improved barrier for copper interconnects is desired.
SUMMARY OF THE INVENTION
[0006] The invention is a copper interconnect having a transition
metal-nitride barrier with a(thin metal-silicon-nitride cap. A
transition metal-nitride barrier is formed over the structure. Then
the barrier is annealed in a Si-containing ambient to form a
silicon-rich capping layer at the surface of the barrier. The
copper is then deposited over the silicon-rich capping layer.
[0007] An advantage of the invention is providing a diffusion
barrier with improved adhesion with copper with low resistance.
[0008] This and other advantages will be apparent to those of
ordinary skill in the art having reference to the specification in
conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
[0009] FIG. 1 is a cross-sectional diagram of a prior art copper
interconnect layer;
[0010] FIG. 2 is a cross-sectional diagram of a copper interconnect
layer having a diffusion barrier with silicon-rich capping layer
according to the invention;
[0011] FIGS. 3A-3E are cross-sectional diagrams of the interconnect
of FIG. 2 at various stages of fabrication, according to the
invention;
[0012] FIG. 4 is a XPS graph of a WN film with SiH.sub.4 anneal;
and
[0013] FIG. 5 is a XPS graph of a TiN film with SiH.sub.4
anneal.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0014] The invention will now be described in conjunction with a
copper interconnect layer. Those of ordinary skill in the art will
realize that the benefits of the invention may be applied to
diffusion barriers in general where improved wetting property is
desired without a significant increase in resistance.
[0015] A silicon-rich surface layer capping a diffusion barrier
106, according to the invention, is shown in FIG. 2. An interlevel
dielectric (ILD) 102 and intrametal dielectric (IMD) 104 are
located over a semiconductor body 100. Semiconductor body 100
comprises transistors (not shown) and isolation structures (not
shown) formed herein. Semiconductor body 100 may also comprise
other devices and structures as are known in the art. Semiconductor
body 100 may include additional interconnect layers (not shown)
and/or additional interconnect layers may be formed over IMD
104.
[0016] Suitable materials for ILD 102 and IMD 104 are known in the
art. ILD 102 and IMD 104 may comprise the same or differing
materials. For example, ILD 102 and IMD 104 may comprise a PETEOS
(Plasma Enhanced TetraEthyOxySilane) oxide or a low-k material such
as xerogel, FSG (fluorine-doped silicate glass), HSQ (hydrogen
silsesquioxane), organic low-k materials, or a combination
thereof.
[0017] Diffusion barrier 106 is located within in ILD 102 and IMD
104. Diffusion barrier 106 comprises a transition metal nitride
with a silicon-rich capping layer 108. For example, diffusion
barrier 106 may comprise TaN or WN with a Ta--Si--N or W--Si--N
capping layer 108, respectively. Copper 110 is located over surface
layer 108 of barrier 106. The transition metal-nitride portion of
diffusion barrier 106 has low resistance and excellent wettability
to dielectrics such as FSG. However, the transition metal-nitrides
have poor wettability to copper. The metal-silicon-nitrides, on the
other hand, have good wettability to copper, but much higher
resistance. By having a thin capping layer 108 of
metal-silicon-nitride and the bulk of the barrier 106 being
metal-nitride, both low resistance and good wettability to copper
are obtained.
1TABLE I Table 1 is a comparison of Ta, TaN and TaSiN for copper
metallization. Barrier Ta TaN TaSiN Crystallinity strong weak
amorphous Stress -2100 -2100 -500 Sidewall small islands large
islands near continuous Agglomeration RMS (.ANG.) 35 400 8
[0018] As shown in Table I, TaSiN is amorphous. Amorphous layers
tend to be good barriers for copper because they do not have grain
boundaries for the copper to diffuse through. The sidewall
agglomeration for copper is also very good for TaSiN. On TaN,
copper forms large islands and thus, voids in the copper which are
bad for electromigration. On Ta, copper forms small islands, which
are better, but not as good as the near continuous layer on TaSiN.
The improved properties of TaSiN can be achieved with a very thin
layer. Thus, a thin surface layer of TaSiN is all that is needed to
provide good adhesion for copper.
[0019] A method for forming diffusion barrier 106, according to the
invention, will now be discussed with reference to FIGS. 3A-E.
Referring to FIG. 3A, semiconductor body 100 is processed through
the formation of ILD 102 and IMD 104. This includes the formation
of isolation structures, transistors and other desired devices, as
is known in the art. Suitable methods for forming ILD 102 and IMD
104 are known in the art. ILD 102 and IMD 104 may comprise the same
or differing materials. For example, ILD 102 and IMD 104 may
comprise a PETEOS (Plasma Enhanced TetraEthyOxySilane) oxide or a
low-k material such as xerogel, FSG (fluorine-doped silicate
glass), HSQ (hydrogen silsesquioxane), organic low-k materials, or
a combination thereof. IMD 104 may be part of the first
interconnect layer or any subsequent interconnect layer.
[0020] Referring to FIG. 3B, a trench 120 is etched in IMD 104. If
vias are desired and have not already been formed, a dual damascene
process may be used to form both trench 102 in IMD 104 and a via
122 in ILD 102. If via connections have already been fabricated,
only trench 120 is etched.
[0021] Next, a diffusion barrier 106 is formed on the surface of
IMD 104 and on the surface of trench 120, as shown in FIG. 3C.
Diffusion barrier 106 is also formed on the surface of via 122, if
a via connection has not already been formed. Diffusion barrier 106
comprises a transition metal-nitride. For example, diffusion
barrier 106 may comprise TaN, TiN, WN, or MoN. The thickness of
diffusion barrier 106 is on the order of 50-500 .ANG.. A conformal
deposition process is desirable in order to provide a sufficient
barrier on the sidewalls of the trench and via. As an example,
diffusion barrier 106 may be deposited using a thermal CVD
(chemical vapor deposition) process or ionized sputtering
process.
[0022] Referring to FIG. 3D, a silicon-rich cap layer 108 is formed
at the surface of diffusion barrier 106. Silicon-rich cap layer 108
may be formed by subjecting diffusion barrier 106 to an anneal in a
silicon-containing ambient. Exemplary gases for use during the
anneal include silane (SiH.sub.4), Si.sub.2H.sub.6, and
Si(CH.sub.3)4. Silicon decomposes at low temperatures (e.g., on the
order of 360.degree. C.) and is incorporated into the surface of
diffusion barrier 106. The low temperature anneal incorporates
silicon in a thin layer at the surface of barrier 106 and creates a
silicon-rich capping layer 108. Silicon is not incorporated into
the bulk of the film. Silicon-rich capping layer 108 has a
thickness on the order of 5-20 .ANG..
[0023] The silicon-rich capping layer 108 improves the copper
adhesion properties of the diffusion barrier 106. Because silicon
incorporation is limited to the near surface, silicon-rich capping
layer 108 does not significantly impair the resistance of the
barrier 106. The process for forming barrier 106 with silicon-rich
capping layer 108 is easy to implement. the process is based on
current barrier technology combined with a simple anneal step.
[0024] Referring to FIG. 3E, a copper layer 110 is formed on the
silicon-rich capping layer 108 of barrier layer 106. Copper layer
110 may be formed by first forming a copper seed layer and then
using an electroplating process to deposit the remaining copper.
The silicon in silicon-rich capping layer 108 may form a
copper-silicide at the interface. The copper-silicide further
improves adhesion.
[0025] The copper layer 110 and barrier layer 106 are then removed
back, for example by CMP (chemical-mechanical polish) to
substantially planar with IMD 104, as shown in FIG. 2.
[0026] The feasibility of forming a silicon-rich capping layer on a
transition metal-nitride is illustrated in FIGS. 4 and 5. FIG. 4 is
a XPS depth profile of film composition versus sputtering time for
a WN film with SiH.sub.4 anneal. A WN film was deposited on a
silicon substrate and then subject to an anneal in SiH.sub.4 at a
360.degree. C. susceptor temperature. Significant levels of silicon
are incorporated In the film only at the surface. The XPS depth
profile indicates silicon presence in the first 5 minutes of
sputtering time. Sputtering time is an indication of depth as the
surface is slowly removed. The cross-over point after 30 minutes
indicates the silicon substrate on which the WN was deposited.
[0027] FIG. 5 is a similar XPS graph for a TiN film with SiH.sub.4
anneal. A TiN film was deposited on a silicon substrate and then
subject to an anneal in SiH.sub.4 at a 360.degree. C. susceptor
temperature. Again, silicon is incorporated in the film only at the
surface. The XPS depth profile indicates silicon presence in the
first minute of sputtering time. The cross-over point after 8
minutes indicates the silicon substrate on which the TiN was
deposited.
[0028] The diffusion barrier 106 with silicon-rich capping layer
108 may be applied to the first or any subsequent copper
interconnect layer. Furthermore, it may be applied to one, some, or
all of the copper interconnect layers.
[0029] While this invention has been described with reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. Various modifications and
combinations of the illustrative embodiments, as well as other
embodiments of the invention, will be apparent to persons skilled
in the art upon reference to the description. It is therefore
intended that the appended claims encompass any such modifications
or embodiments.
* * * * *