| Patent | Date |
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IC with thin film resistor with metal walls
Grant 11,424,183 - Hong , et al. August 23, 2 | 2022-08-23 |
Thin Film Resistor With Punch-through Vias
App 20210343642 - Kande; Dhishan ; et al. | 2021-11-04 |
Thin film resistor with punch-through vias
Grant 11,101,212 - Kande , et al. August 24, 2 | 2021-08-24 |
Ic With Thin Film Resistor With Metal Walls
App 20200381358 - HONG; Qi-Zhong ; et al. | 2020-12-03 |
IC with thin film resistor with metal walls
Grant 10,784,193 - Hong , et al. Sept | 2020-09-22 |
Ic With Thin Film Resistor With Metal Walls
App 20200035598A1 - | 2020-01-30 |
In-situ plasma treatment for thin film resistors
Grant 10,439,020 - Ali , et al. O | 2019-10-08 |
Thin Film Resistor With Punch-through Vias
App 20190295948 - Kande; Dhishan ; et al. | 2019-09-26 |
Metal interconnect processing for an integrated circuit metal stack
Grant 10,361,095 - Ali , et al. | 2019-07-23 |
Thin Film Resistor With Punch-through Vias
App 20190221516 - Kande; Dhishan ; et al. | 2019-07-18 |
Thin film resistor with punch-through vias
Grant 10,354,951 - Kande , et al. July 16, 2 | 2019-07-16 |
In-situ Plasma Treatment For Thin Film Resistors
App 20190198603 - ALI; ABBAS ; et al. | 2019-06-27 |
High Voltage Capacitors And Methods Of Manufacturing The Same
App 20190108943 - Liu; Gang ; et al. | 2019-04-11 |
Multilevel via placement with improved yield in dual damascene interconnection
Grant 10,242,147 - Hong | 2019-03-26 |
Metal Interconnect Processing For An Integrated Circuit Metal Stack
App 20190074193 - ALI; Abbas ; et al. | 2019-03-07 |
Device and method for a thin film resistor using a via retardation layer
Grant 10,211,278 - Ali , et al. Feb | 2019-02-19 |
Device And Method For A Thin Film Resistor Using A Via Retardation Layer
App 20190019858 - Ali; Abbas ; et al. | 2019-01-17 |
Metal interconnect processing for a non-reactive metal stack
Grant 10,002,774 - Ali , et al. June 19, 2 | 2018-06-19 |
Multilevel Via Placement With Improved Yield In Dual Damascene Interconnection
App 20170177783 - HONG; Qi-Zhong | 2017-06-22 |
Multilevel via placement with improved yield in dual damascene interconnection
Grant 9,589,093 - Hong March 7, 2 | 2017-03-07 |
Multilevel Via Placement With Improved Yield In Dual Damascene Interconnection
App 20150186588 - HONG; Qi-Zhong | 2015-07-02 |
Method of eliminating etch ridges in a dual damascene process
Grant 7,192,863 - Zhijian , et al. March 20, 2 | 2007-03-20 |
Plasma Treatment of an Etch Stop Layer
App 20060194447 - Ruan; Ju-Ai ; et al. | 2006-08-31 |
Plasma treatment of an etch stop layer
App 20060081965 - Ruan; Ju-Ai ; et al. | 2006-04-20 |
Method of eliminating etch ridges in a dual damascene process
App 20060024956 - Zhijian; Lu ; et al. | 2006-02-02 |
System for improving thermal stability of copper damascene structure
App 20050186788 - Lu, Jiong-Ping ; et al. | 2005-08-25 |
System for improving thermal stability of copper damascene structure
Grant 6,903,000 - Lu , et al. June 7, 2 | 2005-06-07 |
Integrated circuit capacitor in multi-level metallization
App 20050048762 - Hong, Qi-Zhong | 2005-03-03 |
Semiconductor PMD layer dielectric
Grant 6,835,648 - Hong , et al. December 28, 2 | 2004-12-28 |
Semiconductor Pmd Layer Dielectric
App 20040238853 - Hong, Qi-Zhong ; et al. | 2004-12-02 |
Method to improve silicide formation on polysilicon
Grant 6,777,300 - Kittl , et al. August 17, 2 | 2004-08-17 |
Si-rich surface layer capped diffusion barriers
Grant 6,680,249 - Lu , et al. January 20, 2 | 2004-01-20 |
Method for fabricating metal conductors and multi-level interconnects in a semiconductor device
Grant 6,677,232 - Hong , et al. January 13, 2 | 2004-01-13 |
Selective aluminum plug formation and etchback process
Grant 6,660,650 - Konecni , et al. December 9, 2 | 2003-12-09 |
System for improving thermal stability of copper damascene structure
App 20030124828 - Lu, Jiong-Ping ; et al. | 2003-07-03 |
Si-rich surface layer capped diffusion barriers
App 20020192950 - Lu, Jiong-Ping ; et al. | 2002-12-19 |
Si-rich surface layer capped diffusion barriers
App 20020180044 - Lu, Jiong-Ping ; et al. | 2002-12-05 |
Yield improvement of dual damascene fabrication through oxide filling
Grant 6,461,955 - Tsu , et al. October 8, 2 | 2002-10-08 |
Process for isolating an exposed conducting surface
App 20020086522 - Lu, Jiong-Ping ; et al. | 2002-07-04 |
Method to improve silicide formation on polysilicon
App 20020086485 - Kittl, Jorge Adrian ; et al. | 2002-07-04 |
Method for fabricating metal conductors and multi-level interconnects in a semiconductor device
App 20020081837 - Hong, Qi-Zhong ; et al. | 2002-06-27 |
Method Of Forming A Silicide Layer Using Metallic Impurities And Pre-amorphization
App 20020045307 - KITTL, JORGE ; et al. | 2002-04-18 |
Method of forming a silicide layer using metallic impurities and pre-amorphization
Grant 6,372,566 - Kittl , et al. April 16, 2 | 2002-04-16 |
Integrated circuit interconnect and method
Grant 6,358,849 - Havemann , et al. March 19, 2 | 2002-03-19 |
Passivation of inlaid metallization
Grant 6,355,559 - Havemann , et al. March 12, 2 | 2002-03-12 |
Method of improving the texture of aluminum metallization for tungsten etch back processing
Grant 6,329,282 - Hsu , et al. December 11, 2 | 2001-12-11 |
Reduced temperature contact/via filling
Grant 6,323,553 - Hsu , et al. November 27, 2 | 2001-11-27 |
Using An Elevated Silicide As Diffusion Source For Deep Sub-micron And Beyond Cmos
App 20010038131 - HU, JERRY CHE-JEN ; et al. | 2001-11-08 |
Multi-stage semiconductor cavity filling process
Grant 6,150,252 - Hsu , et al. November 21, 2 | 2000-11-21 |
TiN+Al films and processes
Grant 6,120,842 - Lu , et al. September 19, 2 | 2000-09-19 |
Method to improve the texture of aluminum metallization
Grant 6,077,782 - Hsu , et al. June 20, 2 | 2000-06-20 |
Method of forming ultra-thin and conformal diffusion barriers encapsulating copper
Grant 6,077,774 - Hong , et al. June 20, 2 | 2000-06-20 |
Method of improving texture of metal films in semiconductor integrated circuits
Grant 6,054,382 - Hsu , et al. April 25, 2 | 2000-04-25 |
Transistor having an improved salicided gate and method of construction
Grant 6,048,784 - Hong , et al. April 11, 2 | 2000-04-11 |
Method of forming diffusion barriers encapsulating copper
Grant 6,008,117 - Hong , et al. December 28, 1 | 1999-12-28 |
Method for producing barrier-less plug structures
Grant 5,985,763 - Hong , et al. November 16, 1 | 1999-11-16 |
Method for controlling tensile and compressive stresses and mechanical problems in thin films on substrates
Grant 5,834,374 - Cabral, Jr. , et al. November 10, 1 | 1998-11-10 |
Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits
Grant 5,668,411 - Hong , et al. September 16, 1 | 1997-09-16 |
Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen
Grant 5,624,869 - Agnello , et al. April 29, 1 | 1997-04-29 |
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