U.S. patent application number 09/497390 was filed with the patent office on 2002-06-06 for single step process for blanket-selective cvd aluminum deposition.
Invention is credited to Chen, Liang-Yuh, Guo, Ted, Mosely, Roderick C., Naik, Mehul.
Application Number | 20020068427 09/497390 |
Document ID | / |
Family ID | 24485795 |
Filed Date | 2002-06-06 |
United States Patent
Application |
20020068427 |
Kind Code |
A1 |
Guo, Ted ; et al. |
June 6, 2002 |
Single step process for blanket-selective cvd aluminum
deposition
Abstract
The present invention relates generally to an improved apparatus
and process for providing uniform step coverage on a substrate and
planarization of metal layers to form continuous, void-free
contacts or vias in sub-half micron aperture width applications. In
one aspect of the invention, a dielectric layer is formed over a
conducting member. A thin nucleation layer is then deposited onto
the dielectric layer prior to etching high aspect ratio apertures
through the nucleation and dielectric layers to expose the
underlying conducting member on the aperture floor. A CVD metal
layer is then deposited onto the structure to achieve selective
deposition within the apertures, while preferably also forming a
blanket layer on the field. The present apparatus and process
reduce the number of steps necessary to fabricate CVD metal
interconnects and layers that are substantially void-free and
planarized. The metallization process is preferably carried out in
an integrated processing system that includes both a PVD and CVD
processing chamber so that once the substrate is introduced into a
vacuum environment, the metallization of the apertures to form vias
and contacts occurs without the formation of oxides between the
layers.
Inventors: |
Guo, Ted; (Palo Alto,
CA) ; Chen, Liang-Yuh; (San Jose, CA) ; Naik,
Mehul; (Sunnyvale, CA) ; Mosely, Roderick C.;
(Pleasanton, CA) |
Correspondence
Address: |
Patent Counsel
Applied Materials
PO Box 450A
Santa Clara
CA
95052
US
|
Family ID: |
24485795 |
Appl. No.: |
09/497390 |
Filed: |
February 3, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09497390 |
Feb 3, 2000 |
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08620405 |
Mar 22, 1996 |
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08620405 |
Mar 22, 1996 |
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08561605 |
Nov 21, 1995 |
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Current U.S.
Class: |
438/618 ;
257/E21.585; 257/E21.586 |
Current CPC
Class: |
H01L 21/76879 20130101;
H01L 21/76843 20130101; H01L 21/32051 20130101; C23C 16/54
20130101; C23C 14/568 20130101; H01L 21/76877 20130101; H01L
21/76876 20130101 |
Class at
Publication: |
438/618 |
International
Class: |
H01L 021/4763 |
Claims
We claim:
1. A method of forming an interconnect on a substrate having a
nonconducting layer covering a conducting member, comprising the
steps of: a) forming a nucleation layer over the surface of the
nonconducting layer; b) etching an interconnect through the
nucleation layer and nonconducting layer to form a floor exposing a
portion of the conducting member; and c) chemical vapor depositing
a metal layer selectively on the interconnect floor and nucleation
layer.
2. The method of claim 1 further comprising the step of: d)
physical vapor depositing a metal layer over the chemical vapor
deposited metal layer at a temperature below about 660.degree. C.
to cause the physical vapor deposited metal layer and chemical
vapor deposited metal layer to flow into the via without voids
forming therein.
3. The method of claim 1 wherein the nucleation layer is comprised
of TiN.
4. The method of claim 3, wherein the nucleation layer has a
thickness of between about 10 and about 900 Angstroms.
5. The method of claim 1, wherein the chemical vapor deposited
metal is aluminum.
6. The method of claim 1, wherein the physical vapor deposited
metal comprises aluminum, and wherein the physical vapor deposition
of aluminum occurs at a temperature below about 400.degree. C.
7. The method of claim 1, wherein the steps a through c are
performed in an integrated processing chamber.
8. The method of claim 6, wherein the physical vapor deposited
aluminum comprises a dopant, the method further comprising the step
of: (d) annealing at a temperature of between about 250.degree. C.
and about 350.degree. C.
9. The method of claim 1, wherein the nonconducting layer is a
dielectric.
10. In a selective chemical vapor deposition process for forming
and filling interconnects through a nonconducting layer, wherein
the interconnects have a conducting floor, the improvement
comprising the steps of: a) forming a nucleation layer over the
nonconducting layer; and b) etching interconnects through the
nucleation layer and nonconducting layer.
11. The process of claim 10, wherein the nonconducting layer is a
dielectric layer.
12. The process of claim 10, wherein the nucleation layer is
comprised of TiN.
13. The method of claim 12, wherein the nucleation layer has a
thickness of between about 10 and about 900 Angstroms.
14. A method of preventing nonuniform deposits on a first surface
during selective chemical vapor deposition of metals on a second
surface, the method comprising the steps of: a) forming a
nucleation layer on the first surface so that metal chemical vapor
deposited on the first surface will be substantially
planarized.
15. The process of claim 14, wherein the first surface comprises a
dielectric.
16. The process of claim 14, wherein the nucleation layer is
comprised of TiN.
17. The method of claim 16, wherein the nucleation layer has a
thickness of between about 10 and about 900 Angstroms.
18. A method of depositing metal films on select portions of a
substrate, the method comprising the steps of: (a) providing an
electrically conducting nucleation layer over select portions of
the substrate; and (b) selectively chemical vapor depositing a
metal film on the nucleation layer.
19. The method of claim 18, wherein the step of selectively
chemical vapor depositing a metal film comprises the steps of: (c)
providing dimethyl aluminum hydride and hydrogen gas; (d) reacting
the dimethyl aluminum hydride and hydrogen gas at the nucleation
layer surface to deposit aluminum on the nucleation layer.
20. The method of claim 19, wherein the nucleation layer is
comprised of TiN.
Description
[0001] This is a continuation-in-part of pending U.S. patent
application Ser. No. 08/561,605 filed on Nov. 21, 1995 entitled
"Low Temperature Integrated Metallization Process and
Apparatus."
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a metallization method and
apparatus for manufacturing semiconductor devices, More
particularly, the present invention relates to the selective
Metallization of apertures in insulative layers to form void-free
interconnections between conducting layers, including apertures
such as contacts or vias in high aspect ratio sub-half micron
applications, while preferably also forming a blanket layer on the
insulative layer.
[0004] 2. Background of the Related Art
[0005] Sub-half micron multilevel metallization is one of the key
technologies for the next generation of very large scale
integration ("VLSI"). The multilevel interconnections that lie at
the heart of this technology require planarization of interconnect
features formed in high aspect ratio apertures, including contacts,
vias, lines or other features. Reliable formation of these
interconnect features is very important to the success of VLSI and
to the continued effort to increase circuit density and quality on
individual substrates and die.
[0006] Two conventional methods for depositing Aluminum (Al) by
chemical vapor deposition ("CVD") include a blanket process and a
selective process. CVD processes typically involve the deposition
of a film layer which occurs when a component of the chemical vapor
contacts a "nucleation site" on the substrate. The component
attaches to the nucleation site, creating a deposit surface on
which Other deposition proceeds. A blanket CVD process typically
deposits a film on the entire exposed surface of the substrate
including the sidewall and bottom of apertures, as well as on the
field because the entire substrate surface serves as a nucleation
layer. A selective process typically deposits a film only on select
nucleation surfaces provided on the substrate surface,
[0007] Blanket CVD metal deposition, such as CVD Al, where a metal
film is deposited on the entire exposed surface of the substrate,
usually requires the presence of an electrically conductive
nucleation layer. Thin metal films deposited during a blanket CVD
process are usually conformal and provide excellent step coverage,
i.e., uniform thickness of layers on the sides and base of any
aperture extending into the exposed surface of the substrate, even
for very small aperture geometries. Therefore CVD of aluminum is a
common method used to fill apertures however, there are two
difficulties associated with filling high aspect ratio (height to
width.gtoreq.2:1) apertures to form vias or contacts using blanket
CVD methods. First, CVD films grow from all sides in an aperture
and a void or key-hole may form in the filled aperture comprising
the via or contact resulting in a compromised device. The formation
of voids within these apertures is commonly referred to as crowning
because the deposited layer grows upwardly and outwardly at the
upper corners of the aperture and bridges at his location before We
aperture has been completely filled. Second, the nucleation layer
which must be deposited on the aperture walls to ensure deposition
of the CVD layer thereon layer thereon further reduces the width of
the aperture thereby increasing the difficulty of void-See filling
of the aperture without voids.
[0008] Recent transmission electron microscopy data ("TEM") reveal
that voids exist in many interconnects formed by the CVD Al process
even though standard electric tests of these interconnects do not
evidence the existence of this void, Referring to FIG. 3, a TEM
photograph shows a cross-sectional image of a 0.45 micron via
filled with CVD Al. The image clearly indicates that voids exist in
the metal layer deposited within the via structure. It should be
recognized Eat this void is very difficult to detect by regular
cross sectional standard electron microscopy ("SEM") techniques,
because some deformation occurs in soft aluminum during mechanical
polishing of the slide preparation. In addition, electric
conductivity tests many times do not detect structural
abnormalities such as voids because the metal forms a bridging
layer through at least a portion of the aperture. However, despite
the generally positive electric conductivity tests, conduction
through a contact having a void therein may, over time, compromise
the integrity of the integrated circuit devices in which the void
is formed.
[0009] A TEM study of various CVD Al layers formed on substrates
indicates that the voids typically occur in a key hole pattern
wherein the top portion of the via becomes sealed before the via
has been entirely filled, i.e., Crowning. Although a thin conformal
layer of CVD Al can typically be deposited in high aspect ratio
apertures for creating contacts and vias at low temperatures,
continued CVD deposition to completely fill the apertures typically
results in the formation of voids therein Extensive efforts have
been focused on eliminating the voids in metal layers by modifying
CVD processing steps and parameters,
[0010] Selective CVD Al deposition is based on the fact that the
decomposition of the CVD Al precursor gas to provide a deposition
film usually requires a source of electrons from a conductive
nucleation film. In accordance with a conventional selective CVD Al
deposition process, Al should grow in the bottom of an aperture
where either a metal film or doped silicon from the underlying
conductive layer has been exposed, but should not grow on the
dielectric material on the field and forming the aperture walls.
These underlying metal films and doped silicon, unlike the
dielectric aperture walls, are both conductive and supply the
electrons needed for decomposition of the Al precursor gas and
resulting deposition of Al. The result obtained trough selective
deposition is a "bottom-up" growth of CVD Al in the holes capable
of filling very small dimension (<0.25 .mu.m), high aspect ratio
(>5:1) via or contact openings.
[0011] Referring to FIG. 2, a schematic diagram of an integrated
circuit structure 10 shows a metal interconnect formed in via 14
that was selectively nucleated by the conducting member 18 and
grown uniformly upward towards the surface 20 of the dielectric
layer 16. However, in actual practice of the selective deposition
process, there are almost always defects on the surface of the
dielectric and on He sidewalls of the apertures which provide free
electrons and thus also serve as nucleation sites for CVD Al
growth, casing unwanted nodule formation on the surface 20 and the
walls of the apertures. Note that a nodule 12 was formed on the
dielectric layer by loss of selectivity during a conventional
selective CVD process to fill the via or contact 14. Various
methods have been used to the loss of selectivity that leads to
nodule formation, especially in selective tungsten (W) technology.
These methods have included, for example, preconditioning of the
wafer surface and chemical mechanical polishing (CMP) of the puce
to remove any nodules 12 which form on the wafer surface 20 during
selective deposition. However, these methods complicate the
processing steps required to form the desired circuit structure and
significantly increase the expense of the integrated circuit
manufacturing process. Likewise, some steps, such as CMP, cannot
reach the sidewalls of the apertures. In addition, adding steps to
the overall process increases the likelihood that defects may
result in the formed structures.
[0012] Therefore, there remains a need for a metallization process
for void-free filling of apertures, particularly high aspect ratio,
sub-quarter micron wide apertures for forming contacts and vias.
More particularly, it would be desirable to have a simple process
requiring fewer processing steps to accomplish selective CVD Al
deposition to create vias or contacts without nodule formation
caused by the loss of selectivity on the field. It would also be
desirable to have a single step process for both the selective CVD
Al deposition in vias or contants and the blanket CVD Al deposition
on the field.
SUMMARY OF THE INVENTION
[0013] The present invention provides a method and apparatus for
forming an interconnect on a substrate having a dielectric layer
covering at least a first conducting member, comprising the steps
of forming a nucleation layer over the surface of the dielectric,
etching an aperture through the nucleation layer and dielectric
layer to form a floor exposing a portion of a conducting member and
selectively depositing a metal by chemical vapor deposition on the
interconnect floor and nucleation layer.
[0014] Another aspect of the invention provides a method and
apparatus for preventing nodule formation on a first surface during
selective chemical vapor deposition of metals on a second surface,
the method comprising the steps of forming a nucleation layer on
the first surface to provide substantially uniform growth of a
deposited film.
[0015] Yet another aspect of the invention provides a method and
apparatus for depositing metal films on select portions of a
substrate, the method comprising the steps of providing an
electrically conducting nucleation layer over select portions of
the substrate and selectively depositing a metal film by chemical
vapor deposition on the nucleation layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] So that the manner in which the above recited features,
advantages and objects of the present invention are a ed can be
understood in detail, a more particular description of the
invention, briefly summarized above, may be had by reference to the
embodiments thereof which are illustrated in the appended
drawings.
[0017] It is to be noted, however, that the appended drawings
illustrate only typical embodiments of this invention and are
therefor not to be considered limiting of its scope, for the
invention may admit to other equally effective embodiments.
[0018] FIG. 1 is a transmission electron microscopy photograph
showing a cross-section of a semiconductor substrate via having
voids therein;
[0019] FIG. 2 is a schematic diagram showing the nodule formation
caused by loss of selectivity in conventional selective chemical
vapor deposition processes;
[0020] FIG. 3 is a cross-sectional view of a layered structure
including a dielectric layer 32 and a nucleation layer formed
sequentially over an electrically conducting member or layer;
[0021] FIG. 4 is a a cross-sectional diagram of a via or contact
etched into the nucleation layer and the dielectric layer in the
structure of FIG. 3;
[0022] FIG. 5 is a cross-sectional view of a void-free metal
interconnect and blanket metal layer as formed on the structure of
FIG. 4,
[0023] FIG. 6 is an integrated processing system configured for
sequential metallization in accordance with the present invention,
and
[0024] FIG. 7 is a schematic flow diagram of a CVD gas box delivery
system for supplying gases to the system of FIG. 6.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
[0025] The present invention provides a simple process and
apparatus for the selective deposition of material within sa
geometries, such as small apertures which will form vias or
contacts, that eliminates the loss of selectivity on the field,
This process comprises the steps of (1) depositing a thin
conducting layer, preferably titanium nitride (TiN). to serve as a
nucleation layer over a field; (2) patterning and etching the
nucleation and dielectric layers to form apertures having small
geometries; and (3) depositing CVD metal over the she to provide
selective grow of the metal within the small geometries and,
preferably, simultaneous uniform growth on the field, Accordingly,
the present invention provides a method and apparatus for void-free
filling of small geometries with a reduced number of processing
steps and preventing the formation of nodules on the field.
[0026] Referring to FIG. 3, a cross-sectional diagram of a layered
structure 30 is shown including a dielectric layer 32 and a
nucleation layer 34 formed sequentially over an electrically
conducting member or layer 36. The electrically conducting member
36 may take the form of a doped silicon substrate or it may be a
first or subsequent conducting layer formed on a substrate. The
electrically conducting member 36 will typically be either a metal
or doped silicon layer that has been previously patterned to form
part of an electronic device. A dielectric layer 32 is formed over
the conducting member 36 in accordance with procedures known in the
art to form a part of the overall integrated circuit.
[0027] According to presently used selective deposition techniques,
the next step in the process typically includes etching the
dielectric layer to form interconnecting vias or contacts. However,
according to the present invention, a thin nucleation layer 34 is
deposited to form a substantially continuous film over the
dielectric layer 32. This nucleation layer facilitates the process
by which the deposited CVD metal begins to form a solid crystalline
state of matter comprising a definite arrangement of atoms, ions or
molecules on the substrate.
[0028] The preferred nucleation layer 34 includes such layers as a
TiN layer formed by (PVD TiN) or conductive or other refractory
film (Nb, Al, Ti, Ta, aluminum silicates, silica, high alumina,
etc.), TiN formed by CVD or PVD (CVI) TiN or PVD TiN), or a
combination of these layers. Titanium nitride is a preferred
nucleation material because titanium nitride provides good
nucleation of aluminum, has good electromigration resistance and
can be etched easily in applications where a dielectric layer is
disposed therebelow. It is also preferred e nucleation layer have a
thickness of between about 10 and about 900 Angstroms, with the
most preferred thickness being between about 100 and about 200
Angstroms.
[0029] Following formation of the nucleation layer 34, the
nucleation layer 34 and dielectric layer 32, both shown in FIG. 3,
are patterned and etched to open apertures for forming vias or
contacts down to a conducting layer 36.
[0030] Now referring to FIG. 4, a cross-sectional diagram of a via
or contact 38 etched into the nucleation layer 34 and the
dielectric layer 32 of FIG. 3 is shown. The patterning and etching
of the vias or contacts 38 may be accomplished with any
conventional method known to one of ordinary skill in the art. The
via 38 has walls 40 formed in the dielectric layer 32 that extend
downward a sufficient distance to expose a surface or floor 42 of a
conducing member or layer 36.
[0031] The portion of the nucleation layer 34 that remains after
the etch may be described as a self-aligned layer which covers the
dielectric layer 32 to form a field upon which uniform blanket
deposition can occur. In this manner, the presence of the
nucleation layer 34 prevents the formation of unwanted nodules 12
on the dielectric surface and eliminates the need for chemical
mechanical polishing of the dielectric surface to remove any
nodules formed thereon,
[0032] Now referring to FIG. 5, a cross-sectional view of a
void-free metal interconnect 44 and blanket metal layer 46 is
shown. Chemical vapor deposition of a metal on the patterned
substrate provides simultaneous selective deposition within the via
or contact 38 and blanket deposition on the nucleation layer 34 to
provide conformal coverage of the via or contact structure without
forming voids (See FIG. 1) in the interconnect or nodules on the
field. Due to the uniform deposition of CVD Al over the nucleation
layer 34, the top surface 48 of the CVD Al is substantially
planed.
[0033] While the CVD Al may be deposited under various conditions,
a typical process involves wafer temperatures of between about
150.degree. C. and about 300.degree. C. and a deposition rate of
between about 20 .ANG./sec and about 130 .ANG./sec. The CVD Al
deposition may be performed at chamber pressures of between about 1
torr and about 80 torr, with the preferred chamber pressures being
about 25 torr. The preferred deposition reaction for CVD Al
involves the reaction of dimethyl aluminum hydride ("DMAH") with
hydrogen gas (H.sub.2) according to the following equation:
6(CH.sub.3).sub.2Al-H+3H.sub.2 - - - 6Al(CH.sub.4).sub.2
[0034] The deposition within the via or contact 38 (See FIG. 4) to
form metal interconnect 44 is selective because surface 42 of the
underlying conductive layer 36 has been exposed to the CVD Al at
the floor of the via or contact 38. Therefore, the CVD Al is
deposited from the floor 42 upward to fill the via or contact 38
without any substantial CVD Al deposition on the via or contact
walls 40 (See FIG. 4).
[0035] Furthermore, since the nucleation layer 34 was deposited on
the dielectric layer 32 prior to etching of the via or contact 38,
the walls and floor of the via or contact 38 are the exposed
surfaces of the dielectric layer 32 and the exposed underlying
nucleation layer 36, respectively As discussed above, substantially
non-conducting dielectric materials, including silicon, are not
good electron donors and, therefore, do not provide good nucleation
for decomposition of the CVD metal precursor. Rather, a metal film
begins to form on the via or contact floor because the exposed
conducting member 36 underlying the via or contact 38 nucleates the
decomposition. After an initial layer of the metal has been
deposited on the via or contact floor 42, subsequent deposition
occurs more easily so that the metal grows from the via or contact
floor 42 outward to fill the hole 38.
[0036] Although defects on the dielectric wall 40 of the via or
contact 38 may cause the formation of scattered nodules within the
via or contact, these nodules will usually not block the via or
contact and cause voids therein. Because the conducting via or
contact floor exposes a large surface area of a nucleation
material, the via or contact will be filled with metal from the
floor upward before a nodule has an opportunity to grow across the
via or contact and form a void therein.
[0037] In another aspect of the present invention, the substrate
may be moved to a PVD Al chamber following the selective CVD
process to deposit a PVD Al layer 50 over the CVD layer previously
formed at temperatures below the melting point of the CVD Al and
PVD Al. Where the CVD metal layer 46 is aluminum, it is preferred
that the PVD Al layer 50 be deposited at a wafer temperature below
about 660.degree. C., preferably below about 400.degree. C. The
aluminum layer 46 will star to flow during the PVD deposition
process at about 400.degree. C., with the TiN nucleation layer 34
remaining firmly in place as a solid metal layer.
[0038] It is preferred that the PVD Al layer include at least trace
amounts of copper (Cu). This can be accomplished by using an AlCu
target to form PVD AlCu layer. When the PVD AlCu sequentially
follows CVD Al in an integrated process having a PVD and CVD
chamber on the same cluster tool, an oxide layer cannot form
therebetween and the PVD AlCu layer 50 grows epitaxially on the CVD
Al layer 46 without grain boundaries, i.e., uniform crystal
structure throughout both layers. Furthermore, the sequential CVD
Al/PVD AlCu process allows the intermixed layer (elements 46 and 50
combined) to be annealed at about 300.degree. C. for about 15
minutes to achieve substantially uniform distribution of Cu in the
CVD/PVD layers. It is also preferred that the top surface 52 of the
intermixed CVD/PVD Al layer receive a PVD TiN anti-reflection
coating ("ARC") (not shown) for reducing the reflectivity of the
surface and improving the photolitographic performance of the
layer. Finally, a most preferred method of the present invention
for metallization of a substrate aperture includes the sequential
steps of covering a conducting member 36 with a dielectric layer
32, depositing a nucleation layer 34 of titanium nitride through a
PVD TiN process, etching vias or contacts 38 to expose a portion of
the conducting member 36, depositing selective/blanket CVD Al layer
44,46, depositing a PVD AlCu layer 50 and depositing a TiN ARC (not
shown).
[0039] Referring now to FIG. 6, a schematic diagram of an
integrated cluster tool 60 is shown. Typically, substrates are
introduced and withdrawn from the cluster tool 60 through a
cassette loadlock 62. A robot 64 having a blade 67 is located
within the cluster tool 60 to move the substrates through the
cluster tool 60. One robot 64 is typically positioned in a buffer
chamber 68 to transfer substrates between the cassette loadlock 62,
degas wafer orientation chamber 70, preclean chamber 72, PVD TiN
chamber 74 and cooldown chamber 76. A second robot 78 is located in
transfer chamber 80 to transfer substrates to and from the cooldown
chamber 76, coherent Ti chamber 82, CVD TN chamber 84, CVD Al
chamber 86 and PVD AlCu processing chamber 88. The transfer chamber
80 in the integrated system is preferably maintained at low/high
pressure vacuum in the range of 10.sup.-3 to 10.sup.-8 torr. This
specific configuration of the chambers in FIG. 6 comprise an
integrated processing system capable of both CVD and PVD processes
in a single cluster tool. The chamber configuration is merely
illustrative and should not be taken as limiting the application of
the present invention.
[0040] Typically, a substrate processed in the cluster tool 60 is
passed from the cassette loadlock 62 to the buffer chamber 68 where
the robot 64 first moves the substrate into a degas chamber 70. The
substrate may then be transferred into preclean chamber 72, PVD TiN
chamber 74, and then into a cooldown chamber 76. From the cooldown
chamber 76, the robot 78 typically moves the substrate into and
between one or more processing chambers 32,31, before returning the
substrate back to the cooldown chamber 76. It is anticipated that
the substrate may be processed or cooled in one or more chambers
any number of times in any order to accomplish fabrication of a
desired structure on the substrate. The substrate is removed from
the cluster tool 60, following processing, through the buffer
chamber 68 and then to the loadlock 62. A microprocessor controller
80 is provided to control the sequence and formation of the desired
film layers on the substrates.
[0041] In accordance with the present invention, the cluster tool
60 passes a substrate through loadlock 62 into de-gas chamber 10
wherein the substrates are introduced to outgas contaminants.
Substrate is then moved into a preclean chamber 72 where the
surface of the substrate is cleaned to remove any contaminants
thereon. The substrate is then moved by the robot 64 into cooldown
chamber 76 in preparation of processing. The robot 78 transfers the
substrate to either a CVD TiN chamber 84, or a Ti chamber 82 having
a collimator, i.e., a plurality of cells extending substantially
parallel to the substrate, located between the substrate and the
target, to deposit a nucleation layer on the substrate. In the case
where the substrate first receives deposition of a collimated Ti
layer, the substrate is then typically processed in the CVD TiN
chamber 84. Following deposition of the CVD TiN layer, the
substrate is moved into an etch chamber for patterning and plasma
etching of the layers formed thereon to form the desired apses
which will for the vias or contacts.
[0042] The substrate, with apertures extending through the TiN
nucleation layer and dielectric layer down to the exposed
conducting member surface defining the floor of the via or contact,
then receives a layer of CVD metal, such as CVD Al, in a CVD Al
chamber 86. The substrate may then be processed in a PVD AlCu
chamber 88 and, optionally, in a PVD TiN chamber 74 located on the
integrated system.
[0043] Cu dispersion throughout the CVD Al layer is accomplished
because the integrated system allows the substrate to be processed
continually in a single processing tool having both a CVD Al
chamber and a PVD Al chamber. This prevents exposure of the
processed substrate to the outside environment which may result in
the formation of oxide layers on the exposed surface, i.e., the CVD
Al layer. Oxide layers allowed to form on the CVD Al layers will
inhibit even distribution of the Cu provided by the PVD Al layer
throughout the CVD Al layer.
[0044] One staged-vacuum wafer processing system is disclosed in
U.S. Pat. No. 5,186,718, entitled "Staged-Vacuum Wafer Processing
System and Method," Tepman et al., issued on Feb. 16, 1993, which
is hereby incorporated herein by reference.
[0045] Referring now to FIG. 7, a gas box system for supplying
gases to the CVD chamber of the system in FIG. 6 is illustrated.
The TiN gas box is supplied with N.sub.2, Ar, He, O.sub.2, H.sub.2,
and NF.sub.3. The reaction product tetracus dimethyl amino titanium
("TDMAT"), along with the inert gas Ar and N.sub.2, are passed into
the CVD TiN chamber for processing. Similarly, a CVD Al gas box is
supplied with N.sub.2, Ar and H. The reaction product dimethyl
aluminum hydride ("DMAH"), H.sub.2 and the inert gas Ar are passed
into the CVD Al chamber for deposition of aluminum. Both chambers
are equipped with a turbo pump for providing a vacuum in the
chamber and a blower/dry pump.
[0046] While the foregoing is directed to the preferred embodiment
of the present invention, other and further embodiments of the
invention may be devised without departing from the basic scope
thereof. The scope of the invention is determined by the claims
which follow.
* * * * *