U.S. patent application number 09/510102 was filed with the patent office on 2002-04-25 for vertical source/drain contact semiconductor.
Invention is credited to Ang, Ting Cheong, Loong, Sang Yee, Ong, Puay Ing, Quek, Shyue Fong.
Application Number | 20020048884 09/510102 |
Document ID | / |
Family ID | 24029388 |
Filed Date | 2002-04-25 |
United States Patent
Application |
20020048884 |
Kind Code |
A1 |
Quek, Shyue Fong ; et
al. |
April 25, 2002 |
Vertical source/drain contact semiconductor
Abstract
A semiconductor device and manufacturing process therefor is
provided in which angled dopant implantation is followed by the
formation of vertical trenches in the silicon on insulator
substrate adjacent to the sides of the semiconductor gate. A second
dopant implantation in the exposed the source/drain junctions is
followed by a rapid thermal anneal which forms the semiconductor
channel in the substrate. Contacts are then formed which connect
vertically to the exposed source/drain junctions either directly or
through salicided contact areas.
Inventors: |
Quek, Shyue Fong; (Petaling
Jaya, MY) ; Ang, Ting Cheong; (Singapore, SG)
; Loong, Sang Yee; (Singapore, SG) ; Ong, Puay
Ing; (Kluang Johor, MY) |
Correspondence
Address: |
THE LAW OFFICES OF MIKIO ISHIMARU
1110 SUNNYVALE-SARATOGA ROAD
SUITE A1
SUNNYVALE
CA
94087
US
|
Family ID: |
24029388 |
Appl. No.: |
09/510102 |
Filed: |
February 22, 2000 |
Current U.S.
Class: |
438/268 ;
257/E21.415; 257/E21.422; 257/E21.431; 257/E21.564; 257/E27.112;
257/E29.117; 257/E29.147; 257/E29.278; 438/151 |
Current CPC
Class: |
H01L 21/76281 20130101;
H01L 29/41733 20130101; H01L 29/66825 20130101; H01L 21/76264
20130101; H01L 29/66636 20130101; H01L 29/66772 20130101; H01L
29/78621 20130101; H01L 27/1203 20130101; H01L 29/458 20130101 |
Class at
Publication: |
438/268 ;
438/151 |
International
Class: |
H01L 021/00; H01L
021/336; H01L 021/84 |
Claims
The invention claimed is:
1. A semiconductor device comprising: a semiconductor substrate; a
gate dielectric having two opposite sides disposed over the
semiconductor substrate, the gate dielectric having an edge
adjacent the semiconductor substrate; a gate having two opposite
sides disposed over the gate dielectric, the gate having an edge
over the edge of the gate dielectric; source/drain junctions
disposed adjacent the sides of the gate dielectric in the
semiconductor substrate; the semiconductor substrate having contact
trenches provided therein adjacent the sides of the gate dielectric
and exposing the source/drain junctions; and conductive contacts
disposed in the contact trenches conductively connected to the
source/drain junctions.
2. The semiconductor device as claimed in claim 1 wherein the
conductive contacts completely fill the contact trenches.
3. The semiconductor device as claimed in claim 1 including
saliciding with a metal silicide around and in the contact trenches
and wherein the conductive contacts fill a portion of the contact
trenches.
4. The semiconductor device as claimed in claim 1 wherein the
source/drain junctions have vertical areas exposed by the contact
trenches.
5. The semiconductor device as claimed in claim 1 wherein the
conductive contacts have vertical conductive connections.
6. The semiconductor device as claimed in claim 1 wherein the
source/drain junctions include extension source/drain junctions in
the semiconductor substrate around the contact trenches, the
extension source/drain junctions are closest together below the
surface of the semiconductor substrate.
7. The semiconductor device as claimed in claim 1 including an
insulator layer disposed below the semiconductor substrate; and a
further semiconductor substrate disposed below the insulator
layer.
8. The semiconductor device as claimed in claim 1 including an
isolation insulator disposed around the source/drain junctions and
the contact trenches, the isolation insulator disposed in the
semiconductor substrate.
9. A semiconductor device comprising: a silicon substrate; a gate
oxide layer having two opposite sides disposed over the silicon
substrate, the gate oxide layer having an edge adjacent the silicon
substrate; a polysilicon gate having two opposite sides disposed
over the gate oxide layer, the polysilicon gate having an edge over
the edge of the gate oxide layer; source/drain junctions disposed
adjacent the sides of the gate oxide layer in the silicon
substrate; the silicon substrate having contact trenches provided
therein adjacent the sides of the gate oxide layer and exposing the
source/drain junctions; and conductive contacts disposed in the
contact trenches conductively connected to the source/drain
junctions.
10. The semiconductor device as claimed in claim 9 wherein the
conductive contacts completely fill the contact trenches.
11. The semiconductor device as claimed in claim 9 including
saliciding with a metal silicide around and in the contact trenches
and wherein the conductive contacts fill portions of the contact
trenches.
12. The semiconductor device as claimed in claim 9 wherein the
source/drain junctions have vertical areas exposed by the contact
trenches.
13. The semiconductor device as claimed in claim 9 wherein the
conductive contacts have vertical conductive connections.
14. The semiconductor device as claimed in claim 9 wherein the
source/drain junctions include extension source/drain junctions in
the silicon substrate around the contact trenches, the extension
source/drain junctions are closest together below the surface of
the silicon substrate.
15. The semiconductor device as claimed in claim 9 including an
insulator layer disposed below the silicon substrate; and a further
silicon substrate disposed below the insulator layer.
16. The semiconductor device as claimed in claim 9 including an
isolation trench disposed around the source/drain junctions and the
contact trenches, the isolation trench disposed in the silicon
substrate.
17. A method of manufacturing a semiconductor device, comprising
the steps of: providing a semiconductor substrate; forming a gate
dielectric layer over the semiconductor substrate; forming a gate
layer over the gate dielectric layer; etching the gate dielectric
layer and the gate layer to form a gate stack; implanting
source/drain junctions adjacent the sides of the gate stack;
forming contact trenches in the semiconductor substrate to expose
the source/drain junctions, the contact trenches adjacent the
opposite sides of the gate stack; and forming conductive contacts
in the contact trenches conductively connected with the
source/drain junctions.
18. The method of manufacturing a semiconductor device as claimed
in claim 17 wherein the step of forming the conductive contacts
completely fills the contact trenches.
19. The method of manufacturing a semiconductor device as claimed
in claim 17 including a step of saliciding with a metal silicide
around and in the contact trenches and wherein the step of forming
conductive contacts fills portions of the contact trenches.
20. The method of manufacturing a semiconductor device as claimed
in claim 17 wherein the step of forming the source/drain junctions
implanting dopant into the exposed source/drain junctions in the
contact trenches.
21. The method of manufacturing a semiconductor device as claimed
in claim 17 wherein the step of forming the conductive contacts
forms vertical conductive connections.
22. The method of manufacturing a semiconductor device as claimed
in claim 17 wherein the step of forming the source/drain junctions
include forming extension source/drain junctions in the
semiconductor substrate around the contact trenches and forming the
extension source/drain junctions closest together below the surface
of the semiconductor substrate.
23. The method of manufacturing a semiconductor device as claimed
in claim 17 including the steps of forming the semiconductor
substrate on an insulator layer and. of forming the insulator layer
on a further semiconductor substrate.
24. The method of manufacturing a semiconductor device as claimed
in claim 17 including a step of forming an isolation insulator
around the source/drain junctions and the contact trenches, the
isolation insulator formed in the semiconductor substrate.
25. A method of manufacturing a semiconductor device, comprising
the steps of: providing a silicon substrate; forming a gate oxide
layer over the silicon substrate; forming a polysilicon gate layer
over the gate oxide layer; etching the gate oxide layer and the
polysilicon gate layer to form a gate stack; implanting
source/drain junctions adjacent the sides of the gate stack;
forming contact trenches in the silicon substrate to expose the
source/drain junctions, the contact trenches adjacent the opposite
sides of the gate stack; and forming conductive contacts in the
contact trenches in conductive connection with the source/drain
junctions.
26. The method of manufacturing a semiconductor device as claimed
in claim 25 wherein the step of forming the conductive contacts
completely fills the contact trenches.
27. The method of manufacturing a semiconductor device as claimed
in claim 25 including the step of saliciding with a metal silicide
around and in the contact trenches and wherein the step of forming
the conductive contacts fills portions of the contact trenches.
28. The method of manufacturing a semiconductor device as claimed
in claim 25 wherein the step of forming the source/drain junctions
forms vertical areas exposed by the contact trenches.
29. The method of manufacturing a semiconductor device as claimed
in claim 25 wherein the step of forming the conductive contacts
forms vertical conductive connections.
30. The method of manufacturing a semiconductor device as claimed
in claim 25 wherein the step of forming the source/drain junctions
include forming extension source/drain junctions in the silicon
substrate around the contact trenches, the extension source/drain
junctions are formed closest together below the surface of the
silicon substrate.
31. The method of manufacturing a semiconductor device as claimed
in claim 25 including the step of providing an insulator layer
disposed below the silicon substrate and providing a further
silicon substrate disposed below the insulator layer.
32. The method of manufacturing a semiconductor device as claimed
in claim 25 including the step of forming an isolation trench
around the source/drain junctions and the contact trenches, the
isolation trench formed in the silicon substrate.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to semiconductor
devices, and more particularly to silicon on insulator
transistors.
BACKGROUND ART
[0002] Semiconductor devices such as transistors, resistors,
capacitors, and other circuit elements, are formed in and upon
semiconductor substrates. These circuit elements are interconnected
by contacts and vias, which connect to patterned conductor layers
which are separated by various dielectric layers.
[0003] A critical objective of the semiconductor industry has been
to continually decrease the size of semiconductor devices to
increase performance and reduce cost.
[0004] The ability to reduce performance degrading parasitic
capacitances resulting from diffusion of junction dopants into
semiconductor substrates has been accomplished through the use of
silicon on insulator (SOI) technology. The SOI technology consists
of forming the desired semiconductor devices in a layer of silicon
which overlies an insulator layer deposited on a conventional
semiconductor substrate.
[0005] As semiconductor technology has advanced, there has been a
continuing concentration on reducing the size of the semiconductor
devices to allow for increased levels of circuit integration,
improved performance, and higher density.
[0006] However, when the length and width of a semiconductor device
are reduced, the length and width of the contacts connected to the
semiconductor device must also be reduced. When the length and
width of the contacts are reduced, the cross-sectional area is
reduced by the square of the length or width and the resistance
generally increases by the square (power of 2). The industry is
currently reaching the point where the size is so small that the
relative resistance is so high as to render connection to small
devices impossible.
[0007] As devices continue to be reduced in size, it is clear that
a breakthrough solution to this problem is required for continued
success in reducing semiconductor device size and thus increasing
device integration, performance, and function while at the same
time reducing cost.
DISCLOSURE OF THE INVENTION
[0008] The present invention provides a semiconductor device and
manufacturing process therefor in which vertical trenches are
formed in the semiconductor or the silicon on insulator substrate
adjacent to the sides of the semiconductor gate to expose the
source/drain junctions. The contacts connect vertically to the
exposed source/drain junctions either directly or through salicided
contact areas to provide a smaller semiconductor device
(transistor) footprint.
[0009] The present invention further provides a semiconductor
device and manufacturing process therefor in which vertical
trenches are formed in the semiconductor or the silicon on
insulator substrate adjacent to the sides of the semiconductor gate
to expose the source/drain junctions. The contacts connect
vertically to the exposed source/drain junctions either directly or
through salicided contact areas to provide a contact to silicon
connection.
[0010] The present invention further provides a semiconductor
device and manufacturing process therefor in which angled
implantation of dopant followed by formation of vertical trenches
which are also implanted with dopant. A rapid thermal anneal forms
source/drain extension junctions in the semiconductor or the
silicon on insulator substrate which are below the surface thereof
to provide reduced junction parasitic capacitance.
[0011] The present invention further provides a semiconductor
device and manufacturing process therefor in which vertical
trenches are formed in the semiconductor or the silicon on
insulator substrate adjacent to the sides of the semiconductor gate
to expose the source/drain junctions. The contacts connect
vertically to the exposed source/drain junctions either directly or
through salicided contact areas to provide increased area vertical
electrical connections between the contact and the silicon.
[0012] The present invention further provides a semiconductor
device and manufacturing process therefor in which vertical
trenches are formed in the semiconductor or the silicon on
insulator substrate adjacent to the sides of the semiconductor gate
to expose the source/drain junctions. The contacts connect
vertically to the exposed source/drain junctions either directly or
through salicided contact areas to provide a new method of forming
contact to silicon connections.
[0013] The above and additional advantages of the present invention
will become apparent to those skilled in the art from a reading of
the following detailed description when taken in conjunction with
the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a cross section of a semiconductor device in an
initial stage of formation;
[0015] FIG. 2 is the structure of FIG. 1 after a sacrificial layer
(not shown) is deposited on the semiconductor layer and patterned
for the formation and growth of an insulator layer;
[0016] FIG. 3 is the structure of FIG. 2 after successive
depositions of a gate dielectric, a floating gate electrode, an
inner gate layer, and a control gate electrode.
[0017] FIG. 4 is the structure of FIG. 3 after a photoresist is
deposited, patterned, and developed in a conventional manner
followed by an etch process to remove unprotected portions of the
layers above the substrate to form a gate stack;
[0018] FIG. 5 is the structure of FIG. 4 undergoing source/drain
(S/D) extension junction implantation to form S/D extension
junctions;
[0019] FIG. 6 is the structure of FIG. 5 having a barrier layer and
a spacer layer deposited thereon;
[0020] FIG. 7 is the structure of FIG. 6 after an anisotropic etch
to remove portions of the spacer layer and a subsequent etch to
remove portions of the barrier layer to expose the SOI layer and to
form a sidewall spacer;
[0021] FIG. 8 is the structure of FIG. 7 during a low-angle,
four-quadrant implantation;
[0022] FIG. 9 is the structure of FIG. 8 after a rapid thermal
anneal (RTA) which causes enhanced thermal diffusion (TED) of the
S/D junctions and the S/D extension junctions;
[0023] FIG. 10 is the structure of FIG. 9 after the deposition,
patterning, developing, and etching of a contact interlayer
dielectric (ILD) and a channel layer ILD;
[0024] FIG. 11 is a top view of the structure of FIG. 10;
[0025] FIG. 12 is an alternate embodiment to the structure shown in
FIG. 10; and
[0026] FIG. 13 is a top view of the structure of FIG. 12.
BEST MODE FOR CARRYING OUT THE INVENTION
[0027] The present invention as hereinafter described is embodied
in a silicon on insulator (SOI) transistor device, but it should be
understood that it is applicable to many different semiconductor
devices which require reduced length and widths without a
corresponding decrease in the contact area.
[0028] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizontal as just defined. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over", and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate.
[0029] Referring now to FIG. 1, therein is shown a semiconductor
device 10 in an initial stage of formation. A semiconductor
substrate, such as a silicon substrate 12, has an insulator layer,
such as a silicon oxide layer 14, and a second semiconductor
substrate, such as a doped silicon on insulator (SOI) layer 16,
successively deposited thereon.
[0030] Referring now to FIG. 2, therein is shown the structure of
FIG. 1 after a sacrificial layer (not shown) is deposited on the
SOI layer 16 and patterned for the formation and growth of an
insulator layer, a field oxide 18. The sacrificial layer is removed
and a chemical mechanical polishing process planarizes the field
oxide and the SOI layer 16.
[0031] Chemical-mechanical polishing (referred to as "CMP")
typically involves mounting a wafer face down on a holder and
rotating the wafer face under pressure against a polishing pad
mounted on a polishing platen, which in turn is rotating or is in
orbital state. A slurry containing a chemical that chemically
interacts with the facing wafer layer and an abrasive that
physically removes that layer is flowed between the wafer and the
polishing pad or on the pad near the wafer. A combination of the
chemical reaction between the slurry and the layer being polished
and the mechanical interaction between abrasives within the slurry
and the layer being polished cause the planarization of the layer.
During integrated circuit fabrication, this technique is commonly
applied to planarize various wafer layers, such as dielectric
layers, metallization, etc.
[0032] Referring now to FIG. 3, therein is shown the structure of
FIG. 2 after successive depositions of a gate dielectric, a
floating gate electrode, an inner gate layer, and a control gate
electrode. In the preferred embodiment, the gate dielectric layer
is a gate oxide (GOX) layer 20, the floating gate electrode is a
polysilicon (Si) layer 22, the inner gate layer is a tungsten (W)
layer 24, and the control gate electrode is a silicon oxynitride
(SiON) layer 26.
[0033] Referring now to FIG. 4, therein is shown the structure of
FIG. 3 after a photoresist (not shown) is deposited, patterned, and
developed in a conventional manner followed by an etch process to
remove unprotected portions of the layers above the substrate to
form a gate stack 28. The photoresist mask is then removed to
provide the structure shown in FIG. 4.
[0034] Referring now to FIG. 5, therein is shown the structure of
FIG. 4 undergoing source/drain (S/D) extension junction
implantation 30 to form S/D extension junctions 32 and 34 adjacent
to the sides of the gate stack 28. The implantation 30 is a
high-angle implantation to cause the dopant being implanted to be
implanted under the GOX layer 20 as well as in the SOI layer
16.
[0035] Referring now to FIG. 6, therein is shown the structure of
FIG. 5 having a barrier layer 38, generally an oxide layer, and a
spacer layer 40, generally of an oxide or oxynitride deposited
thereon. The barrier layer 38 tends to be much thinner than the
spacer layer 40.
[0036] Referring now to FIG. 7, therein is shown the structure of
FIG. 6 after an anisotropic etch to remove portions of the spacer
layer 40 and a subsequent etch to remove portions of the barrier
layer 38 to expose the SOI layer 16 and to form the sidewall spacer
44.
[0037] The sidewall spacer 44 is then used during an over-etch
process of the SOI layer 16, which exposes the oxide layer 14 to
form S/D contact trenches 46 and 48.
[0038] Referring now to FIG. 8, therein is shown the structure of
FIG. 7 during a low-angle, four-quadrant implantation 50. The
implantation 50 implants dopants which form S/D junctions 52 and 54
in the SOI layer 16.
[0039] Referring now to FIG. 9, therein is shown the structure of
FIG. 8, after a rapid thermal anneal (RTA) which causes enhanced
thermal diffusion (TED) of the S/D junctions 52 and 54 and the S/D
extension junctions 32 and 34. The S/D junctions 52 and 54 extend
vertically and the S/D extension junctions 32 and 34 extend
horizontally.
[0040] The TED causes the closest point of the S/D extension
junctions 32 and 34 to be below the surface of the SOI layer 16
rather than just at the surface of the SOI layer 16 and under the
GOX layer 20. This closest distance is called the "channel" and is
conventionally at the surface of the silicon just below the GOX
layer 20. By having the closest point of the channel in the SOI
layer 16, the capacitance effect caused by the overlap of the S/D
extension junctions 32 and 34 under the GOX layer 20 and the
polysilicon layer 22 are reduced. By reducing these parasitic
capacitances, the performance of the semiconductor device 10 will
be improved.
[0041] Also shown in FIG. 9 are salicided S/D contact areas 56 and
58 and a gate contact area 60. The contact areas are generally
vertical and are of such materials as tungsten silicide (WSi) or
titanium silicide (TiSi) which form in the presence of silicon.
Thus, the SOI layer 16 is completely salicided.
[0042] Referring now to FIG. 10, therein is shown the structure of
FIG. 9 after the deposition, patterning, developing, and etching of
a contact interlayer dielectric (ILD) 62 and a channel layer ILD
64. Also shown is the deposition of a conductive metal channel 68
and a conductive metal contact 70 to the salicided contact area 56
and of a channel 72 and its contact 74 to the salicided contact
area 58. The channel 68 and its contact 70 can be deposited at one
time as can the channel 72 and its contact 74, which can be metals
such as aluminum (Al) and tungsten (W). The conductive metal
contacts 70 and 74 make and form vertical S/D contacts with the
salicided contact areas 56 and 58.
[0043] Referring now to FIG. 11, therein is shown a top view of the
structure of FIG. 10. A top view of the gate stack 28 is shown with
the contacts 70 and 74 and the salicided contact areas 56 and 58 in
the contact trenches 46 and 48. It should be noted that the
contacts 70 and 74 are generally square in cross section and are
not of equal length to the salicided contact areas 56 and 58,
respectively. This is because the saliciding provides a
sufficiently low resistance surface that a large cross-sectional
contact area is not required.
[0044] Referring now to FIG. 12, therein is shown an alternate
embodiment to the structure shown in FIG. 10. The same numbers are
used to describe the same elements as in FIG. 10. In FIG. 12, the
saliciding step is eliminated which means that contacts 70' and 74'
will be in conductive contact directly with the SOI layer 16. Where
there is direct contact between the contact metal and silicon, the
conductivity will be reduced. Thus, the resistance between the
contacts 70' and 74' and the SOI layer 16 is relatively large.
[0045] Referring now to FIG. 13, therein is shown a top view of the
structure of FIG. 12. To increase the conductivity and reduce the
resistance, 70' and 74' are made rectangular to cover as much of
the S/D junctions 52 and 54, and the S/D extension junctions 32 and
34 as possible. Thus, the conductive metal contacts 70' and 74'
make and form vertical S/D contacts.
[0046] While the invention has been described in conjunction with a
specific best mode, it is to be understood that many alternatives,
modifications, and variations will be apparent to those skilled in
the art in light of the aforegoing description. Accordingly, it is
intended to embrace all such alternatives, modifications, and
variations which fall within the spirit and scope of the included
claims. All matters set forth herein or shown in the accompanying
drawings are to be interpreted in an illustrative and non-limiting
sense.
* * * * *