Loong; Sang Yee

Patent Applications and Registrations

Patent applications and USPTO patent grants for Loong; Sang Yee.The latest application filed is for "via electromigration improvement by changing the via bottom geometric profile".

Company Profile

0.22.12

Loong; Sang Yee - Singapore SG
Loong; Sang Yee - SG SG
Loong, Sang Yee - Sigapore SG
Loong; Sang Yee - Kuala Lumpur MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Via electromigration improvement by changing the via bottom geometric profile Grant 7,781,895 - Zhang , et al. August 24, 2	2010-08-24
Via electromigration improvement by changing the via bottom geometric profile Grant 7,691,739 - Zhang , et al. April 6, 2	2010-04-06
Via Electromigration Improvement By Changing The Via Bottom Geometric Profile App 20090250818 - Zhang; Bei Chao ; et al.	2009-10-08
Via electromigration improvement by changing the via bottom geometric profile App 20060160354 - Zhang; BeiChao ; et al.	2006-07-20
Via electromigration improvement by changing the via bottom geometric profile Grant 7,045,455 - Zhang , et al. May 16, 2	2006-05-16
Method of body contact for SOI MOSFET Grant 6,963,113 - Ang , et al. November 8, 2	2005-11-08
Via electromigration improvement by changing the via bottom geometric profile App 20050090097 - Zhang, Beichao ; et al.	2005-04-28
Novel method of body contact for SOI MOSFET App 20050014294 - Ang, Ting Cheong ; et al.	2005-01-20
Method of body contact for SOI mosfet Grant 6,787,422 - Ang , et al. September 7, 2	2004-09-07
Method of forming a high K metallic dielectric layer Grant 6,764,914 - See , et al. July 20, 2	2004-07-20
Method of vacuum packaging a semiconductor device assembly Grant 6,737,739 - Quek , et al. May 18, 2	2004-05-18
Vertical source/drain contact semiconductor Grant 6,653,674 - Quek , et al. November 25, 2	2003-11-25
Method of forming PID protection diode for SOI wafer Grant 6,611,024 - Ang , et al. August 26, 2	2003-08-26
Method of forming a high K metallic dielectric layer App 20030104673 - See, Alex ; et al.	2003-06-05
Method of vacuum packaging a semiconductor device assembly App 20030052403 - Quek, Shyue-Fong ; et al.	2003-03-20
Method for selective oxide etching in pre-metal deposition Grant 6,530,380 - Zhou , et al. March 11, 2	2003-03-11
Vertical source/drain contact semiconductor App 20030006462 - Quek, Shyue Fong ; et al.	2003-01-09
Method of forming of high K metallic dielectric layer Grant 6,492,242 - See , et al. December 10, 2	2002-12-10
Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection Grant 6,492,726 - Quek , et al. December 10, 2	2002-12-10
Vertical Source/drain Contact Semiconductor App 20020151108 - Quek, Shyue Fong ; et al.	2002-10-17
Vertical source/drain contact semiconductor Grant 6,465,296 - Quek , et al. October 15, 2	2002-10-15
Esd Protection Network Used For Soi Technology App 20020115239 - Jun, Song ; et al.	2002-08-22
Novel method of body contact for SOI mosfet App 20020089031 - Ang, Ting Cheong ; et al.	2002-07-11
Triple-layered low dielectric constant dielectric dual damascene approach Grant 6,406,994 - Ang , et al. June 18, 2	2002-06-18
Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate Grant 6,406,948 - Jun , et al. June 18, 2	2002-06-18
Vertical source/drain contact semiconductor App 20020048884 - Quek, Shyue Fong ; et al.	2002-04-25
Method of hard mask patterning Grant 6,376,379 - Quek , et al. April 23, 2	2002-04-23
Method of forming PID protection diode for SOI wafer App 20020022328 - Ang, Ting Cheong ; et al.	2002-02-21
Method of forming PID protection diode for SOI wafer Grant 6,303,414 - Ang , et al. October 16, 2	2001-10-16
High-K MOM capacitor Grant 6,261,917 - Quek , et al. July 17, 2	2001-07-17
Method of fabricating wedge isolation transistors Grant 6,258,677 - Ang , et al. July 10, 2	2001-07-10
Method to form, and structure of, a dual damascene interconnect device Grant 6,252,290 - Quek , et al. June 26, 2	2001-06-26
Method of fabrication of dual gate oxides for CMOS devices Grant 6,248,618 - Quek , et al. June 19, 2	2001-06-19
Method for fabricating a MOS device Grant 6,110,787 - Chan , et al. August 29, 2	2000-08-29

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