Quek; Shyue Fong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Quek; Shyue Fong.The latest application filed is for "etch failure prediction based on wafer resist top loss".

Company Profile

0.25.17

Quek; Shyue Fong - Singapore SG
Quek; Shyue Fong - Petaling Jaya MY
Quek, Shyue Fong - Petaline Jaya MY
Quek; Shyue Fong - Jaya MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Topography driven OPC and lithography flow Grant 9,064,084 - Katakamsetty , et al. June 23, 2	2015-06-23
Etch failure prediction based on wafer resist top loss Grant 8,898,597 - Yang , et al. November 25, 2	2014-11-25
Etch Failure Prediction Based On Wafer Resist Top Loss App 20140282286 - YANG; Qing ; et al.	2014-09-18
Topography Driven Opc And Lithography Flow App 20140282300 - KATAKAMSETTY; Ushasree ; et al.	2014-09-18
System And Method For Generating Care Areas For Defect Inspection App 20130252350 - LEE; Hun Chow ; et al.	2013-09-26
Method of body contact for SOI MOSFET Grant 6,963,113 - Ang , et al. November 8, 2	2005-11-08
Novel method of body contact for SOI MOSFET App 20050014294 - Ang, Ting Cheong ; et al.	2005-01-20
Double-layered low dielectric constant dielectric dual damascene method Grant 6,803,314 - Quek , et al. October 12, 2	2004-10-12
Method of body contact for SOI mosfet Grant 6,787,422 - Ang , et al. September 7, 2	2004-09-07
Method of forming a high K metallic dielectric layer Grant 6,764,914 - See , et al. July 20, 2	2004-07-20
Method of vacuum packaging a semiconductor device assembly Grant 6,737,739 - Quek , et al. May 18, 2	2004-05-18
Vertical source/drain contact semiconductor Grant 6,653,674 - Quek , et al. November 25, 2	2003-11-25
Method of forming PID protection diode for SOI wafer Grant 6,611,024 - Ang , et al. August 26, 2	2003-08-26
Method of forming a high K metallic dielectric layer App 20030104673 - See, Alex ; et al.	2003-06-05
Method of vacuum packaging a semiconductor device assembly App 20030052403 - Quek, Shyue-Fong ; et al.	2003-03-20
Vertical source/drain contact semiconductor App 20030006462 - Quek, Shyue Fong ; et al.	2003-01-09
Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection Grant 6,492,726 - Quek , et al. December 10, 2	2002-12-10
Double-layered low dielectric constant dielectric dual damascene method App 20020160604 - Quek, Shyue Fong ; et al.	2002-10-31
Vertical Source/drain Contact Semiconductor App 20020151108 - Quek, Shyue Fong ; et al.	2002-10-17
Vertical source/drain contact semiconductor Grant 6,465,296 - Quek , et al. October 15, 2	2002-10-15
Esd Protection Network Used For Soi Technology App 20020115239 - Jun, Song ; et al.	2002-08-22
Novel method of body contact for SOI mosfet App 20020089031 - Ang, Ting Cheong ; et al.	2002-07-11
Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate Grant 6,406,948 - Jun , et al. June 18, 2	2002-06-18
Triple-layered low dielectric constant dielectric dual damascene approach Grant 6,406,994 - Ang , et al. June 18, 2	2002-06-18
Vertical source/drain contact semiconductor App 20020048884 - Quek, Shyue Fong ; et al.	2002-04-25
Process to fabricate a source-drain extension Grant 6,376,319 - Ang , et al. April 23, 2	2002-04-23
Method of hard mask patterning Grant 6,376,379 - Quek , et al. April 23, 2	2002-04-23
Method of forming PID protection diode for SOI wafer App 20020022328 - Ang, Ting Cheong ; et al.	2002-02-21
Process to fabricate a novel source-drain extension App 20020019102 - Ang, Ting Cheng ; et al.	2002-02-14
Process to fabricate a novel source-drain extension App 20020013032 - Ang, Ting Cheong ; et al.	2002-01-31
Thick oxide MOS device used in ESD protection circuit Grant 6,329,253 - Song , et al. December 11, 2	2001-12-11
Method of forming PID protection diode for SOI wafer Grant 6,303,414 - Ang , et al. October 16, 2	2001-10-16
Low voltage controllable transient trigger network for ESD protection Grant 6,275,089 - Song , et al. August 14, 2	2001-08-14
High-K MOM capacitor Grant 6,261,917 - Quek , et al. July 17, 2	2001-07-17
Method of fabricating wedge isolation transistors Grant 6,258,677 - Ang , et al. July 10, 2	2001-07-10
Method to form, and structure of, a dual damascene interconnect device Grant 6,252,290 - Quek , et al. June 26, 2	2001-06-26
Method of fabrication of dual gate oxides for CMOS devices Grant 6,248,618 - Quek , et al. June 19, 2	2001-06-19
ESD protection device for STI deep submicron technology Grant 6,177,324 - Song , et al. January 23, 2	2001-01-23
Method for forming a raised source and drain without using selective epitaxial growth Grant 6,090,691 - Ang , et al. July 18, 2	2000-07-18

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