Ang; Ting Cheong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ang; Ting Cheong.The latest application filed is for "method of eliminating micro-trenches during spacer etch".

Company Profile

0.40.27

Ang; Ting Cheong - Shanghai CN
Ang; Ting Cheong - Beijing CN
Ang; Ting Cheong - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor trench structure having a silicon nitride layer overlaying an oxide layer Grant 9,029,978 - Ang May 12, 2	2015-05-12
Method and system for metal barrier and seed integration Grant 8,309,456 - Ang November 13, 2	2012-11-13
Method Of Eliminating Micro-trenches During Spacer Etch App 20120211863 - Ang; Ting Cheong	2012-08-23
Method of eliminating micro-trenches during spacer etch Grant 8,187,950 - Ang May 29, 2	2012-05-29
Method of improving adhesion strength of low dielectric constant layers Grant 8,110,502 - Ang February 7, 2	2012-02-07
Method with high gapfill capability for semiconductor devices Grant 8,026,151 - Ang September 27, 2	2011-09-27
Method Of Improving A Shallow Trench Isolation Gapfill Process App 20110198734 - Ang; Ting Cheong	2011-08-18
Method of improving a shallow trench isolation gapfill process Grant 7,989,309 - Ang August 2, 2	2011-08-02
Method for forming low dielectric constant fluorine-doped layers Grant 7,910,475 - Ang March 22, 2	2011-03-22
Method Of Eliminating Micro-trenches During Spacer Etch App 20100006975 - Ang; Ting Cheong	2010-01-14
Method For Forming Low Dielectric Constant Fluorine-doped Layers App 20090280653 - ANG; TING CHEONG	2009-11-12
Method for forming low dielectric constant fluorine-doped layers Grant 7,579,271 - Ang August 25, 2	2009-08-25
Method and High Gapfill Capability for Semiconductor Devices App 20090075454 - Ang; Ting Cheong	2009-03-19
Method with high gapfill capability for semiconductor devices Grant 7,456,067 - Ang November 25, 2	2008-11-25
Method with High Gapfill Capability for Semiconductor Devices App 20070275538 - Ang; Ting Cheong	2007-11-29
Method of Improving a Shallow Trench Isolation Gapfill Process App 20070254453 - Ang; Ting Cheong	2007-11-01
Method for forming low dielectric constant fluorine-doped layers App 20070190769 - Ang; Ting Cheong	2007-08-16
Method with high gapfill capability and resulting device structure App 20070161203 - Ang; Ting Cheong	2007-07-12
Method of improving adhesion strength of low dielectric constant layers App 20070134900 - Ang; Ting Cheong	2007-06-14
Method and apparatus for improving breakdown voltage of integrated circuits formed using a dielectric layer process App 20070128860 - Hou; Kuan Cheng ; et al.	2007-06-07
Method and system for metal barrier and seed integration App 20060110902 - Ang; Ting Cheong	2006-05-25
Method of body contact for SOI MOSFET Grant 6,963,113 - Ang , et al. November 8, 2	2005-11-08
Novel method of body contact for SOI MOSFET App 20050014294 - Ang, Ting Cheong ; et al.	2005-01-20
Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor Grant 6,833,606 - Nakamura , et al. December 21, 2	2004-12-21
Copper metal structure for the reduction of intra-metal capacitance Grant 6,815,823 - Teh , et al. November 9, 2	2004-11-09
Double-layered low dielectric constant dielectric dual damascene method Grant 6,803,314 - Quek , et al. October 12, 2	2004-10-12
Method of body contact for SOI mosfet Grant 6,787,422 - Ang , et al. September 7, 2	2004-09-07
Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor App 20040169197 - Nakamura, Hiroshi ; et al.	2004-09-02
Method of forming a high K metallic dielectric layer Grant 6,764,914 - See , et al. July 20, 2	2004-07-20
Method of vacuum packaging a semiconductor device assembly Grant 6,737,739 - Quek , et al. May 18, 2	2004-05-18
Novel copper metal structure for the reduction of intra-metal capacitance App 20040065956 - Teh, Young-Way ; et al.	2004-04-08
Vertical source/drain contact semiconductor Grant 6,653,674 - Quek , et al. November 25, 2	2003-11-25
Copper metal structure for the reduction of intra-metal capacitance Grant 6,649,517 - Teh , et al. November 18, 2	2003-11-18
Method of forming PID protection diode for SOI wafer Grant 6,611,024 - Ang , et al. August 26, 2	2003-08-26
Method of forming a high K metallic dielectric layer App 20030104673 - See, Alex ; et al.	2003-06-05
Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor App 20030085412 - Nakamura, Hiroshi ; et al.	2003-05-08
Method of vacuum packaging a semiconductor device assembly App 20030052403 - Quek, Shyue-Fong ; et al.	2003-03-20
Vertical source/drain contact semiconductor App 20030006462 - Quek, Shyue Fong ; et al.	2003-01-09
Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection Grant 6,492,726 - Quek , et al. December 10, 2	2002-12-10
Method of forming of high K metallic dielectric layer Grant 6,492,242 - See , et al. December 10, 2	2002-12-10
Novel copper metal structure for the reduction of intra-metal capacitance App 20020175414 - Teh, Young-Way ; et al.	2002-11-28
Double-layered low dielectric constant dielectric dual damascene method App 20020160604 - Quek, Shyue Fong ; et al.	2002-10-31
Vertical Source/drain Contact Semiconductor App 20020151108 - Quek, Shyue Fong ; et al.	2002-10-17
Vertical source/drain contact semiconductor Grant 6,465,296 - Quek , et al. October 15, 2	2002-10-15
Esd Protection Network Used For Soi Technology App 20020115239 - Jun, Song ; et al.	2002-08-22
Novel method of body contact for SOI mosfet App 20020089031 - Ang, Ting Cheong ; et al.	2002-07-11
Triple-layered low dielectric constant dielectric dual damascene approach Grant 6,406,994 - Ang , et al. June 18, 2	2002-06-18
Method for fabricating an air gap shallow trench isolation (STI) structure Grant 6,406,975 - Lim , et al. June 18, 2	2002-06-18
Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate Grant 6,406,948 - Jun , et al. June 18, 2	2002-06-18
Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures Grant 6,380,106 - Lim , et al. April 30, 2	2002-04-30
Vertical source/drain contact semiconductor App 20020048884 - Quek, Shyue Fong ; et al.	2002-04-25
Process to fabricate a source-drain extension Grant 6,376,319 - Ang , et al. April 23, 2	2002-04-23
Method of hard mask patterning Grant 6,376,379 - Quek , et al. April 23, 2	2002-04-23
Method of forming PID protection diode for SOI wafer App 20020022328 - Ang, Ting Cheong ; et al.	2002-02-21
Process to fabricate a novel source-drain extension App 20020013032 - Ang, Ting Cheong ; et al.	2002-01-31
Thick oxide MOS device used in ESD protection circuit Grant 6,329,253 - Song , et al. December 11, 2	2001-12-11
Process to fabricate a novel source-drain extension Grant 6,319,783 - Ang , et al. November 20, 2	2001-11-20
Method of forming PID protection diode for SOI wafer Grant 6,303,414 - Ang , et al. October 16, 2	2001-10-16
Low voltage controllable transient trigger network for ESD protection Grant 6,275,089 - Song , et al. August 14, 2	2001-08-14
High-K MOM capacitor Grant 6,261,917 - Quek , et al. July 17, 2	2001-07-17
Method of fabricating wedge isolation transistors Grant 6,258,677 - Ang , et al. July 10, 2	2001-07-10
Method to form, and structure of, a dual damascene interconnect device Grant 6,252,290 - Quek , et al. June 26, 2	2001-06-26
Method of fabrication of dual gate oxides for CMOS devices Grant 6,248,618 - Quek , et al. June 19, 2	2001-06-19
ESD protection device for STI deep submicron technology Grant 6,177,324 - Song , et al. January 23, 2	2001-01-23
Method for fabricating a MOS device Grant 6,110,787 - Chan , et al. August 29, 2	2000-08-29
Method for forming a raised source and drain without using selective epitaxial growth Grant 6,090,691 - Ang , et al. July 18, 2	2000-07-18