U.S. patent application number 09/795241 was filed with the patent office on 2002-02-14 for control of removal rates in cmp.
Invention is credited to Burke, Peter A., Gettman, David, Koinkar, Vilas N., Lack, Craig D., Langlois, Elizabeth A., Lavoie, Raymond Lee JR., Nishida, Yoshikazu, Pierce, Keith G., Sachan, Vikas, Senoo, Hiroyuki, So, Joseph K., Thomas, Terence M., Ye, Qianqiu (Christine), Yoshida, Kouchi.
Application Number | 20020019202 09/795241 |
Document ID | / |
Family ID | 27574645 |
Filed Date | 2002-02-14 |
United States Patent
Application |
20020019202 |
Kind Code |
A1 |
Thomas, Terence M. ; et
al. |
February 14, 2002 |
Control of removal rates in CMP
Abstract
A two-step method for chemical mechanical polishing of a
semiconductor substrate having successive layers, comprised of, a
metal layer, an underlying barrier film and an underlying
dielectric layer. The first polishing step is performed utilizing a
slurry composition selective to the metal in the metal layer, to
remove the metal at a high removal rate during polishing, and the
second polishing step is performed utilizing a slurry composition
selective to the barrier film and least selective to the metal
layer and the underlying dielectric layer. In an alternate
embodiment, the second polishing step is performed with a slurry
equally selective to the barrier layer and the underlying
dielectric layer and least selective to the metal of the metal
layer, to remove the barrier layer at a high removal rate during
polishing, and level a surface of the dielectric layer to the
surface of the metal interconnection structure in the underlying
dielectric layer.
Inventors: |
Thomas, Terence M.; (Newark,
DE) ; Ye, Qianqiu (Christine); (Wilmington, DE)
; So, Joseph K.; (Newark, DE) ; Burke, Peter
A.; (Vancouver, WA) ; Sachan, Vikas;
(Richardson, TX) ; Langlois, Elizabeth A.;
(Wilimington, DE) ; Pierce, Keith G.; (Colorado
Springs, CO) ; Lack, Craig D.; (Wilmington, DE)
; Gettman, David; (Fresno, CA) ; Senoo,
Hiroyuki; (Kohriyama-Shi, JP) ; Yoshida, Kouchi;
(Yamato Kohriyama-Shi, JP) ; Nishida, Yoshikazu;
(Yamato Kohriyama-shi, JP) ; Koinkar, Vilas N.;
(Wilmington, DE) ; Lavoie, Raymond Lee JR.;
(Chesapeake City, MD) |
Correspondence
Address: |
Rodel Holdings, Inc.
1105 North Market Street Suite 1300
Wilmington
DE
19899
US
|
Family ID: |
27574645 |
Appl. No.: |
09/795241 |
Filed: |
February 28, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09795241 |
Feb 28, 2001 |
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09693211 |
Oct 20, 2000 |
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09795241 |
Feb 28, 2001 |
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09329225 |
Jun 10, 1999 |
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09795241 |
Feb 28, 2001 |
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09420682 |
Oct 19, 1999 |
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09795241 |
Feb 28, 2001 |
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09439461 |
Nov 15, 1999 |
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60161242 |
Oct 22, 1999 |
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60088849 |
Jun 10, 1998 |
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60104876 |
Oct 20, 1998 |
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60108656 |
Nov 16, 1998 |
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Current U.S.
Class: |
451/57 ;
257/E21.244; 257/E21.304 |
Current CPC
Class: |
C09G 1/02 20130101; H01L
21/31053 20130101; H01L 21/3212 20130101 |
Class at
Publication: |
451/57 |
International
Class: |
B24B 007/22 |
Claims
What is claimed is:
1. A method for chemical mechanical polishing (CMP) of a
semiconductor substrate having a metal layer, an underlying barrier
film and an underlying dielectric layer with metal interconnection
structures, comprising the steps of: removing the metal layer by
first step CMP utilizing a first step slurry that is highly
selective to the metal of the metal layer and less selective to the
barrier material of the barrier film to remove the metal of the
metal layer with a maximized rate of metal removal by polishing,
and to minimize removal of the barrier material of the barrier
film; and removing the barrier material by second step CMP
utilizing a second step slurry that is highly selective to the
barrier material and is least selective to the metal layer and the
dielectric layer, to remove the barrier film with a maximized rate
by polishing, with minimized removal of the metal of the metal
layer and minimized removal of the dielectric layer to provide the
height of the dielectric layer at a surface level with the metal
interconnection structures; wherein said second step slurry has a
pH greater than 7.
2. The method as recited in claim 1, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having a pH greater than 7, and a dispersion of colloidal silica
having a Zeta Potential of negative (20 millivolts or greater) at
said pH.
3. The method as recited in claim 1, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having a pH greater than 7, and submicron abrasive particles of
colloidal silica comprising up to about 30% by weight of said
second step slurry.
4. The method as recited in claim 1, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having a pH greater than 7, a dispersion of colloidal silica having
a zeta potential of negative (20 millivolts or greater) at said pH,
and submicron abrasive particles of colloidal silica comprising up
to about 30% by weight of said second step slurry.
5. The method as recited in claim 1, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry;
wherein said second step slurry comprises: submicron abrasive
partices of colloidal silica comprising up to about 30% by weight
of said second step slurry; a complexing agent up to about 5,000
ppm by weight of said second step slurry; a corrosion inhibitor up
to about 110 ppm by weight of said second step slurry; a biocide up
to about 200 ppm by weight of said second step slurry; an oxidizing
agent up to about 15,000 ppm by weight of said second step slurry;
an oxide suppressant up to about 5,000 ppm by weight of said second
step slurry; and a chloride salt up to about 200 ppm by weight of
said second step slurry.
6. The method as recited in claim 5, wherein the step of removing
the barrier film by second step CMP utilizes said second step
slurry having a Zeta Potential of negative (20 millivolts or
greater) at said pH.
7. The method as recited in claim 5, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having a complexing agent selected from the group consisting of:
malic acid, tartaric acid, gluconic acid, glycolic acid, citric
acid, phthalic acid, pyrocatechol, pyrogallol, gallic acid, and
tannic acid.
8. The method as recited in claim 5, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having a copper corrosion inhibitor.
9. The method as recited in claim 5, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having hydrogen peroxide as the oxidizing agent.
10. The method as recited in claim 5, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having ammonium chloride as the chloride salt.
11. The method as recited in claim 5, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having polyvinylpyrrolidone as the oxide suppressant.
12. A method for polishing a semiconductor substrate having a metal
layer, an underlying barrier film and an underlying dielectric
layer with metal interconnect structures, comprising the steps of:
removing the metal layer by first step CMP utilizing a first step
slurry that is highly selective to the metal of the metal layer and
less selective to the barrier film to remove the metal of the metal
layer with a maximized rate of metal removal by polishing, and to
minimize removal of the barrier film; and removing the dielectric
layer and barrier film by second step CMP utilizing a second step
slurry that is equally highly selective to the barrier material and
the dielectric material and least selective to the metal in the
metal layer; wherein said second step slurry comprises a pH greater
than 7; submicron abrasive partices of colloidal silica comprising
up to about 30% by weight of said second step slurry; a complexing
agent up to about 5,000 ppm by weight of said second step slurry; a
corrosion inhibitor up to about 110 ppm by weight of said second
step slurry; a biocide up to about 200 ppm by weight of said second
step slurry; and an oxidizing agent up to about 15,000 ppm by
weight of said second step slurry.
13. The method as recited in claim 12, wherein the step of removing
the barrier film or alternately the dielectric material by second
step CMP utilizes said second step slurry having a Zeta potential
of negative (20 millivolts or greater) at said pH.
14. The method as recited in claim 12, wherein the step of removing
the barrier film or alternately the dielectric material by second
step CMP utilizes a second step slurry having a complexing agent
selected from the group consisting of: malic acid, tartaric acid,
gluconic acid, glycolic acid, citric acid, phthalic acid,
pyrocatechol, pyrogallol, gallic acid, and tannic acid.
15. The method as recited in claim 12, wherein the step of removing
the barrier film or alternately the dielectric material by second
step CMP utilizes a second step slurry having a copper corrosion
inhibitor.
16. The method as recited in claim 12, wherein the step of removing
the barrier film by second step CMP utilizes a second step slurry
having hydrogen peroxide as the oxidizer.
17. An aqueous polishing composition for polishing semiconductor
substrates comprising: a pH greater than 7; submicron abrasive
partices of colloidal silica comprising up to about 30% by weight
of said second step slurry; a complexing agent up to about 5,000
ppm by weight of said second step slurry; a corrosion inhibitor up
to about 110 ppm by weight of said second step slurry; a biocide up
to about 200 ppm by weight of said second step slurry; an oxidizing
agent up to about 15,000 ppm by weight of said second step slurry;
an oxide suppressant up to about 5,000 ppm by weight of said second
step slurry; and a chloride salt up to about 200 ppm by weight of
said second step slurry.
18. A polishing composition according to claim 17 wherein said
complexing agent is citric acid.
19. A polishing composition according to claim 17 wherein said
corrosion inhibitor is selected from a group consisting of
benzotriazole, tolyltriazole and mixtures thereof.
20. A polishing composition according to claim 17 wherein the
oxidizing agent is hydrogen peroxide.
21. A polishing composition according to claim 17 wherein the
chloride salt is ammonium chloride.
22. An aqueous polishing composition for polishing semiconductor
substrates comprising a pH greater than 7; submicron abrasive
partices of colloidal silica comprising up to about 30% by weight
of said second step slurry; a complexing agent up to about 5,000
ppm by weight of said second step slurry; a corrosion inhibitor up
to about 110 ppm by weight of said second step slurry; a biocide up
to about 200 ppm by weight of said second step slurry; and an
oxidizing agent up to about 15,000 ppm by weight of said second
step slurry.
23. A polishing composition according to claim 22 wherein said
complexing agent is citric acid.
24. A polishing composition according to claim 22 wherein said
corrosion inhibitor is selected from a group consisting of
benzotriazole, tolyltriazole and mixtures thereof.
25. A polishing composition according to claim 22 wherein the
oxidizing agent is hydrogen peroxide.
Description
[0001] This application is a continuation-in-part of application
Ser. No. 09/693,211, filed Oct. 20, 2000, which claims the benefit
of Provisional Application 60/161,242, filed Oct. 22, 1999. This
application is a continuation-in-part of application Ser. No.
09/329,225 filed Jun. 10, 1999, which claims the benefit of
Provisional Application 60/088,849 filed Jun. 10, 1998. This
application is a continuation-in-part of application Ser. No.
09/420,682 filed Oct. 19, 1999, which claims the benefit of
Provisional Application 60/104,876 filed Oct. 20, 1998. This
application is a continuation-in-part of application Ser. No.
09/439,461 filed Nov. 15, 1999, which claims the benefit of
Provisional Application serial number 60/108,656 filed Nov. 16,
1998. This application also claims the benefit of Provisional
Application 60/188,421 filed Mar. 10, 2000.
[0002] This invention pertains to polishing methods and slurry
compositions or formulations that are used in polishing a
semiconductor substrate having successive layers, comprised of, a
metal layer, an underlying barrier film or layer, and an underlying
dielectric layer.
[0003] Landers et al. in U.S. Pat. No. 5,676,587 discloses a
two-step chemical mechanical polishing process for polishing a
semiconductor substrate. The first polishing step utilizes an
alumina-based slurry to remove a metal layer from an underlying
barrier film. The second polishing step utilizes a silica-based
slurry to remove the barrier film of tantalum(Ta), tantalum nitride
(TaN), titanium (Ti), or titanium nitride (TiN). The silica-based
slurry used in the second polishing step is pH neutral and is
selective to Ta, TaN, Ti, or TiN to remove the barrier film.
[0004] Chemical mechanical polishing (CMP) is an enabling
technology for the production of complex and dense semiconductor
structures and is an effective method for the removal and
planarization of thin films or layers on semiconductor substrates
during the production of semiconductor structures containing
integrated circuits such as multi-chip modules, capacitors and the
like. During the CMP process, a chemical slurry or polishing fluid
(referred to herein as slurry) is used along with a polishing pad.
The mechanical motion of the polishing pad relative to the
semiconductor substrate in combination with chemical reaction of
the polishing fluid with the substrate surface results in material
removal from the semiconductor substrate surface. The "damascene"
CMP process is employed for forming interconnect lines and vias for
multi-layer metal structures that provide the "wiring" of an
integrated circuit and involves etching trenches in a planar
dielectric (insulator) layer and filling the trenches with a
conductive material. The conductive material is typically a metal
such as aluminum, copper, or tungsten. To ensure complete filling
of trenches, an overlayer of metal, about 10,000 to 15,000 Angstrom
in thickness, is required. The dielectric is typically silicon
dioxide (SiO.sub.2), silicon dioxide derived from tetraethyl
orthosilicate (TEOS), phosphosilicate glass (PSG), boron
phosphosilicate glass (BPSG), or a low-k dielectric. A technique
called "dual-damascene" adds etched vias for providing contact to a
lower level as the upper damascene structure is filled. More
details are found in "Making the Move to Dual Damascene
Processing," Semiconductor International, August 1997. Typically a
layer of another material is first deposited to line the trenches
and vias to prevent the migration of metal ions into the dielectric
layer. This migration barrier or barrier layer (also referred to as
a liner layer) typically comprises tantalum, tantalum nitride,
titanium and/or titanium nitride. One or more barrier layers may be
provided depending on the specific application. The barrier layer
has a thickness up to about 1,000 Angstroms. CMP of such a
substrate is performed in two steps to obtain a polished structure
with metal circuit interconnect lines in the dielectric layer to
generate an integrated circuit.
[0005] As described above, semiconductor substrates used to make
integrated circuits typically contain three different layers: a
conductive metal layer, a barrier (or liner) film between the
conductive metal layer and the underlying dielectric layer, and an
underlying dielectric layer. While polishing a semiconductor
substrate by CMP, it is desirable for the removal rates of each
layer to differ significantly from each other in order to induce
planarity and maintain the integrity of the semiconductor substrate
during polishing. This difference in removal rates is characterized
by a parameter termed the selectivity ratio. For example, the ratio
of metal removal rate to the dielectric removal rate is termed the
metal-dielectric selectivity ratio. It is also critical to maintain
the cross section and planarity of underlying conducting metal
interconnect structures (trenches or lines) that provide metal
circuit interconnect structures for the integrated circuit,
especially when polishing to attain high removal rates of the
various layers. Excessive removal of metal from the conducting
metal lines is observed as cavities (known as "dishing") and is
undesirable, since it affects the electrical performance of the
semiconductor structure (integrated circuit) resulting from CMP of
the semiconductor substrate. Similarly, excessive removal of the
dielectric layer surrounding the metal lines is observed as
cavities (known as "erosion") and is undesirable, since the
dielectric layer should be flawless and free of cavities, adjacent
to the side geometry of the metal lines to ensure optimal
electrical performance of the semiconductor structure (integrated
circuit) resulting from CMP of the semiconductor substrate.
Further, CMP polishing is required to polish the semiconductor
substrate with a smooth planar polished surface on which are
manufactured successive layers, which themselves are polished by
CMP. Thus, excessive dishing and erosion in the underlying layers
manifests as defects in the upper layers.
[0006] During known CMP, the semiconductor substrate (substrate) to
be polished is mounted on a carrier or polishing head of a
polishing machine. The exposed surface of the substrate is placed
against a rotating polishing pad. The surface of the polishing pad
that is in contact with the semiconductor substrate is referred to
as the polishing layer. The polishing pad may be a standard pad
(without any abrasive in the polishing layer) also referred to as a
non fixed-abrasive pad or a fixed-abrasive pad (containing abrasive
in the polishing layer). The carrier head provides a controllable
pressure (or downforce), on the substrate to bias it towards the
polishing pad. A polishing fluid with or without abrasive particles
is then dispensed at the interface of the wafer and the polishing
pad to enhance removal of the target layer (for e.g., metal layer
in first-step CMP or barrier layer in second-step CMP). The
polishing fluid is preferably water based and may or may not
require the presence of abrasive particles, depending on the
composition of the polishing layer of the polishing pad. An
abrasive-free polishing fluid also referred to as a reactive liquid
is typically used with a fixed-abrasive pad while a polishing fluid
containing abrasive particles is typically used with a non
fixed-abrasive pad. For polishing softer metal interconnects, such
as copper, the polishing fluid can contain up to 3% by weight of
abrasive particles.
[0007] A need exists for a method of polishing by CMP to
selectively remove (1) the metal layer and the barrier film while
minimizing erosion of the dielectric layer in a semiconductor
substrate; or (2) selectively remove the barrier film and
dielectric layer while minimizing dishing of metal in metal lines
(trenches) in a semiconductor substrate.
[0008] A method according to this invention, comprises a two-step
CMP process for polishing a semiconductor substrate containing a
conducting metal layer, a dielectric layer, and a barrier film or
layer between the two. In the first step of the CMP process, the
metal layer is removed from the substrate without removing
significant amounts of either the barrier film or the underlying
dielectric layer. In the second step of the CMP process, the
barrier film is removed selectively from an underlying dielectric
layer, with minimal removal of metal providing metal lines in the
underlying dielectric layer, utilizing a slurry according to this
invention, resulting in a smooth planar polished surface.
[0009] In an alternate embodiment, the second step of the CMP
process is performed utilizing a slurry according to this invention
that is equally highly selective for removal of the barrier film
and the dielectric layer but relatively much less selective for
removal of the metal providing metal lines in the underlying
dielectric layer. In this alternate embodiment, the method of this
invention removes any scratches or defects in the underlying
dielectric layer.
[0010] The method of this invention is applicable to any
semiconductor substrate containing: a conductive metal (such as Cu,
Al, W, Pt, Pd, Au, or Ir), a barrier or liner layer (such as Ta,
TaN, Ti, or TiN), and an underlying dielectric layer (such as
SiO.sub.2, TEOS, PSG, BPSG, or any low-k dielectric). Metal line
widths, or features, on semiconductor substrates are often around 5
.mu.. However, new technologies are allowing the size of features
to decrease to about 0.18 .mu.. Such newer, smaller features along
with higher feature densities will require more sophisticated and
specialized slurries. The method of this invention is suitably
performed on a substrate with line widths of about 0.1, 0.13, 0.15,
0.2, 0.25, 0.3, 0.35, 0.4, 0.45 to 0.5 .mu.. Suitably, the present
method is performed on a substrate with line widths of less than
0.4 .mu., suitably less than 0.3 .mu., suitably less than 0.2 .mu.,
and suitably about 0.18 .mu..
[0011] In an embodiment, the method of this invention is used to
polish a substrate containing a Cu metal layer, an underlying Ta or
TaN barrier layer, and a SiO.sub.2 dielectric layer, by a two-step
CMP process. In the first step, the Cu overburden layer is removed
while removing minimal amounts of the Ta /TaN liner or SiO.sub.2.
The slurry used in the first step of this process is any
conventional slurry that is capable of removing the copper metal
overburden layer covering the semiconductor structure, and has a
very low rate of material removal on the Ta/TaN barrier film layer
and underlying SiO.sub.2 layer. Typically, a conventional first
step slurry has an acidic pH, and contains oxidizers that enhance
the chemical-mechanical removal of Cu at accelerated rates (about
2,000 Angstroms per minute or greater). The second step is
performed utilizing a selective slurry according to this invention
whereby the barrier layer is removed without removing any remaining
metal in metal lines and without removing the underlying dielectric
material. In an alternate embodiment, the second step of the method
of this invention is performed utilizing a slurry of this invention
that removes the barrier layer and the dielectric layer without
removing any remaining metal in the metal lines on the
semiconductor substrate. This alternate embodiment is utilized to
remove scratches and other defects in the dielectric layer to
obtain a smooth polished substrate surface.
[0012] The slurry of this invention is alkaline with a pH in a
range from about 7.1, 7.3, 7.5, 8.0, 8.5, 9.0, 9.5, 10, 10.5 to 12.
In an embodiment, the pH of the slurry is in a range from about
8.0, 8.1, 8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8, 8.9, 9.0, 9.1, 9.2 to
9.5, preferably in a range from about 8.5, 8.6, 8.7, 8.9 to 9.0. In
another embodiment, the pH of the slurry is in a range from about
9.5, 9.6, 9.7, 9.8, 9.9, 10, 10.1, 10.2, 10.3, 10.4, 10.5, 10.6,
10.7, 10.8 to 11.5, preferably in a range from about 10, 10.1,
10.2, 10.3, 10.4, 10.5, 10.6, 10.7, 10.8 to 11.
[0013] The slurry of this invention contains submicron abrasive
particles with a particle size up to about 50 nm. Preferably the
abrasive particles are non-agglomerated and have a particle size
from about 5, 10, 15, 20, 25, 30, 35, 40, 45 to 50 nm. In an
embodiment, the submicron abrasive is silica, preferably, colloidal
silica.
[0014] Generally, abrasive particles are present in the slurry of
this invention at about 0.01, 0.1, 0.2, 0.3, 0.4, 0.5, 1, 2, 3, 4,
5, 6, 7, 8, 9, 10, 15, 20, 25 to 30% by weight of the slurry. In an
embodiment, the abrasive particles are present at about 5, 6, 7, 8,
9, to 9.5% by weight of the slurry, preferably at about 8, 8.1,
8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8, 8.9, to 9% by weight of the
slurry. In an alternate embodiment, the abrasive particles are
present at about 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25 to
30% by weight of the slurry, preferably at about 10, 11, 12, 13,
14, 15, 16, 17, 18, 19 to 20% by weight of the slurry.
[0015] In an embodiment, the slurry of this invention contains a
complexing agent at about 0.5, 1, 10, 20, 30, 50, 75, 100, 125,
150, 175, 200, 300, 400, 500, 600, 700, 1,000, 1,250, 1,500, 1,750,
2,000, 2,500, 3,000, 3,500, 4,000, 4,500 to about 5,000 parts per
million (ppm) by weight of the slurry, preferably at about 3,000,
3,100, 3,200, 3,300, 3,400, 3,500, 3,600, 3,700, 3,800, 3,900,
4,000, 4,500 to about 5,000 ppm by weight of the slurry. In an
alternate embodiment, the complexing agent is present at about 10,
20, 30, 50, 75, 100, 125, 150, 175, 200, 300, 400 to 500 ppm by
weight of the slurry, preferably at about 100, 125, 150, 175, 200
to 300 ppm by weight of the slurry.
[0016] In an embodiment, a corrosion inhibitor is added to the
slurry of this invention at about 1, 5, 10, 15, 20, 25, 30, 40, 50,
60, 70, 80, 90, 100 to 110 ppm by weight of the slurry, preferably
at about 70, 75, 80, 85, 90, 95, 100, 105 to 110 ppm by weight of
the slurry.
[0017] In an embodiment, an oxidizing agent is added to the slurry
of this invention at about 1, 100, 500, 750, 1,000, 2,000, 3,000,
4,000, 5,000, 6,000, 7,000, 8,000, 9,000, 10,000, 11,000, 12,000,
13,000, 14,000 to 15,000 ppm by weight of the slurry, preferably at
about 5,000, 6,000, 7,000, 8,000, 9,000 to 10,000 ppm by weight of
the slurry.
[0018] In an embodiment, the slurry of this invention contains an
oxide suppressant present at about 1, 10, 20, 30, 40, 50, 75, 100,
125, 150, 200, 250, 300, 350, 400, 450, 500, 600, 700, 800, 900,
1,000, 1,500, 2,000, 2,500, 3,000, 3,500, 4,000, 4,500 to 5,000 ppm
by weight of the slurry, preferably at about 1,000, 1,100, 1,200,
1,300, 1,400, 1,500, 1,600, 1,700, 1,800, 1,900, 2,000, 2,100,
2,200, 2,300, 2,400, to 2,500 ppm by weight of the slurry.
[0019] In an embodiment, the slurry of this invention contains
chloride ions at about 0.01, 0.15, 0.2, 0.25, 1, 2, 3, 4, 5, 10,
15, 20, 25, 30, 35, 40, 45, 50, 75, 150, 175 to 200 ppm by weight
of the slurry, more preferably at about 50, 75, 100, 125 to 150 ppm
by weight of the slurry.
[0020] In an embodiment, the slurry of this invention contains a
biocide present at about 10, 20, 30, 40, 50, 60, 70, 80, 90, 100,
110 to 200 ppm by weight of the slurry, preferably at about 90,
100, 110 to 150 ppm by weight of the slurry.
[0021] The method of this invention utilizes a two-step CMP process
for polishing a semiconductor substrate containing a conducting
metal layer, a dielectric layer, and a barrier film or layer
between the two. In the first step of the CMP process, the metal
layer is removed from the substrate without removing significant
amounts of either the barrier film or the underlying dielectric
layer. In the second step of the CMP process, the barrier layer is
removed selectively utilizing a slurry of this invention without
removing the dielectric material or the metal of the metal lines in
the underlying dielectric layer. In an alternate embodiment, the
second step of the CMP process is performed utilizing a slurry
according to this invention that is equally highly selective for
removal of the barrier film and the dielectric layer but relatively
less selective for removal of the metal providing metal lines in
the underlying dielectric layer. In this alternate embodiment, the
method of this invention removes any scratches or defects in the
dielectric layer. The second polishing step is performed at an
alkaline pH since the barrier metal removal rate is enhanced in the
alkaline range. Typically, barrier metal removal rates above 1000
Angstroms per minute are desired during the second polishing step
with relatively low dielectric and metal removal rates. Second-step
polishing slurries that are basic and contain fumed silica are
disclosed in U.S. application Ser. No. 09/420,682 filed Oct. 19,
1999, which is herein incorporated by reference.
[0022] Abrasives used in CMP slurries include alumina, silica,
ceria, germania, titania, zirconia, diamond, boron nitride, boron
carbide, silicon carbide and combinations thereof. Preferably, the
slurry used in the method of this invention contains abrasive
colloidal silica particles. As disclosed in U.S. application Ser.
No. 09/439,461 filed Nov. 15, 1999, slurries comprised of colloidal
silica particles with a primary particle size of about 10 to about
50 nanometers and a surface area of about 40 to about 600 m.sup.2/g
provide high selectivity for removal of the barrier layer versus
the dielectric layer. U.S. application Ser. No. 09/439,461 is
herein incorporated by reference.
[0023] The abrasive used in the slurry of this invention has a Zeta
Potential of negative (20 millivolts or greater) at the pH of use,
i.e. pH>7. Zeta Potential is a measure of surface charge density
of abrasive particles in dispersion in an aqueous solution of
alkaline pH, i.e. pH>7. A more negative Zeta Potential value,
typically about -70 millivolts to about -20 millivolts is
indicative of a better dispersed slurry with none to extremely low
levels of agglomeration of abrasive particles.
[0024] Typical dielectric materials used in composite semiconductor
substrates include SiO.sub.2, TEOS, phosphosilicate glass (PSG),
boron phosphosilicate glass (BPSG), or a low-k dielectric. Low-k
dielectrics include porous silica, organic low-k dielectrics such
as fluoro polymers and copolymers. Suppression of the dielectric
layer removal rate is achieved through passivation of the
dielectric layer surface. U.S. Pat. No. 5,614,444, "Method of Using
Additives with Silica-Based Slurries to Enhance Selectivity in
Metal CMP," teaches an additive comprising at least one polar and
one apolar component to suppress oxide removal. However, the patent
claims the necessity of both a polar and an apolar group to be
present. U.S. Pat. No. 5,391,258 and U.S. Pat. No. 5,738,800 teach
the use of various compounds to suppress the rate of dielectric
removal during chemical-mechanical polishing of semiconductor
substrates and are herein incorporated by reference for all useful
purposes. U.S. Pat. No. 5,770,103 teaches the use of mono-, di-, or
tri-substituted phenols for removing a titanium barrier layer from
a semiconductor substrate and is herein incorporated by reference
for all useful purposes.
[0025] As disclosed in U.S. application Ser. No. 09/329,225 filed
Jun. 10, 1999, polishing compositions (i.e. slurries) containing an
organic polymer with a degree of polymerization of 3 and a
molecular weight greater than 10,000 provide a selectivity between
the metal and the dielectric layer in excess of 20:1. Exemplary
organic polymers for use as oxide suppressants in the slurry of
this invention include but are not limited to poly vinyl alcohol,
polyvinyl pyrrolidone, polymethyl methacrylate, poly formaldehyde,
poly ethylene glycol and polymethacrylic acid. U.S. application
Ser. No. 09/329,225 is herein incorporated by reference.
[0026] A complexing agent is added to the slurry of this invention
to increase the solubility of metal residuals on the semiconductor
substrate at the start of the second CMP polishing step and the
barrier metal during the remainder of the second CMP polishing
step. U.S. application Ser. No. 09/329,225 provides additional
details on the mechanism of interaction of complexing agents with
metal atoms and a list of compounds for use as complexing agents.
Exemplary complexing agents for use in the polishing composition of
this invention include acetic acid, citric acid, ethyl
acetoacetate, glycolic acid, lactic acid, malic acid, oxalic acid,
salicylic acid, sodium diethyl dithiocarbamate, succinic acid,
tartaric acid, thioglycolic acid, glycine, alanine, aspartic acid,
ethylene diamine, trimethylene diamine, malonic acid, gluteric
acid, 3-hydroxybutyric acid, propionic acid, phthalic acid,
isophthalic acid, 3-hydroxy salicylic acid, 3,5-dihydroxy salicylic
acid, gallic acid, gluconic acid, pyrocatechol, pyrogallol, gallic
acid, tannic acid and salts thereof. Preferably, the complexing
agent used in the slurry of this invention is citric acid.
[0027] In an embodiment, the polishing composition of this
invention contains a choride salt. Chloride ions are highly mobile
species that bond to the semiconductor substrate being polished at
high surface energy sites such as edges and defects to minimize the
local surface energy. Attainment of a uniform surface energy
greatly minimizes localized non-uniform processes and variations in
the surface of the semiconductor substrate being polished.
[0028] Often oxidizing agents, such as hydrogen peroxide, are added
to CMP slurries so that any metal in the substrate being polished
is converted to an oxide during the CMP process thereby enhancing
metal removal rates. A general review of this art is provided by F.
Kaufman et al., J. Electrochem. Soc., vol. 138, p. 3460, 1991,
incorporated by reference herein. Common oxidizing agents used in
slurries are nitrates, iodates, chlorates, perchlorates, chlorites,
sulfates, persulfates, peroxides, ozonated water and oxygenated
water. Oxidizing agents are typically used in CMP slurries at about
0.01% (1,000 ppm by weight of the slurry) to about 7% (7,000 ppm by
weight of the slurry) by weight of the slurry. An oxidizing agent
is used in the slurry of this invention to remove metal residuals
from the substrate surface and to enhance barrier layer metal
removal rates. Preferably, hydrogen peroxide is used as the
oxidizing agent in the slurry of this invention.
[0029] Corrosion inhibitors are also added to the slurry of this
invention to prevent static etching of metal in the semiconductor
substrate. Corrosion inhibitors are typically effective at
concentrations in a range from about 0.001% (100 ppm) to about 4%
(40,000 ppm) by weight of the slurry. Suitable corrosion inhibitors
for use in the slurry of this invention include benzotriazole
(BTA), mercaptobenzotriazole (MBT), tolyltriazole and other
inhibitors typically used with the metal present in the
semiconductor substrate being polished. Preferably, the corrosion
inhibitor used in the slurry of this invention is
benzotriazole.
[0030] Biocides are added to the slurry of this invention to
prevent bacterial and fungal growth. An exemplary biocide being
Neolone.TM. Microbicide (major ingredients:
2-methyl-4-isothiazolin-3-one and propylene glycol) available from
Rohm and Haas Company, Philadelphia, Pa. Further information,
pertaining to compounds that are suitable for use as biocides in
the polishing composition of this invention, is found in US Utility
Application filed on Feb. 2, 2001 (awaiting a filing receipt/Serial
No. from the US PTO) which claims the benefit of US Provisional
Patent Application Serial No. 60/182,960 filed on Feb. 16, 2000
which is incorporated herein by reference.
[0031] The ionic strength of the slurry of this invention is
adjusted through the use of agents such as acids, bases and salts.
Exemplary agents include ammonium hydroxide, ammonium chloride,
ammonium bromide, ammonium acetate, ammonium sulfate, citric acid,
etc. A suitable ionic strength is necessary to prevent
agglomeration of abrasive particles in the slurry of this
invention. A suitable range of ionic strength in the context of
this invention is from about 0.01M to 10 M. A lower ionic strength,
up to about 0.01M, is desired in an embodiment of the slurry of
this invention having a high abrasive content from about 8 to 30%
by weight of the slurry.
[0032] Various embodiments of this invention are illustrated in the
following examples.
EXAMPLE 1
[0033] Method 1 in Table 1 refers to a second step method trial
that was performed utilizing a slurry of this invention and shows
high barrier removal rates with low metal and dielectric removal
rates. Method 2 in Table 1 refers to a second step method trial
that was performed utilizing a slurry of this invention, and shows
high barrier removal rates while metal removal rates are moderate,
between high (about 400 A/min) and low (about 150 A/min), with a
low dielectric removal rate (<250 A/min).
1TABLE 1 (.ANG. = Angstroms) TaN RR Method (A/min) Ta RR
(.ANG./min) Cu RR (.ANG./min) SiO.sub.2RR (.ANG./min) 1 >700
>400 <150 <250 2 >700 >400 <150-400 <250
[0034] In each method trial, a Ta removal rate above 400 .ANG./min
and a TaN removal rate above 700 .ANG./min was observed. The two
methods trials of Table 1 resulted in good planarity without
significant dishing or erosion. The method trials utilized a
slurry, according to this invention, highly selective to the
barrier film (illustrated by high removal rates of Ta or TaN) and
least selective to the metal and the dielectric layer, to provide
the first method trial with desired minimized removal rates of both
Cu and SiO.sub.2. The removal rates of Ta or TaN were maximized
(>700 .ANG./min) with a minimized lower removal rate of Cu
(<150 .ANG./min) and SiO.sub.2 (<250 .ANG./min).
[0035] With proper application of the slurry of this invention,
semiconductor substrates can be polished with low observed dishing
or recess of the interconnect structures (metal lines), in
particular Cu, as well as low erosion of the underlying dielectric
layer (i.e., SiO.sub.2). For example, the second step slurry can be
selected according to this invention to compensate for any dishing
resulting from the first step, by selecting a slurry with an
increased selectivity to SiO.sub.2 which removes the SiO.sub.2 to
the level of the Cu interconnect structures that have undergone
dishing during the first step polishing.
EXAMPLE 2
[0036] Polishing of 6" wafers containing Cu, TaN, and SiO.sub.2
(TEOS) films was performed on a WESTECH 372U polisher (available
from IPEC/Planar). An IC1000 XY-grooved primary polishing pad, a
Politex Regular Embossed secondary polishing pad, and a DF200
carrier film were used (all available from Rodel, Inc.). A TBW 100
Grit Diamond conditioner was employed. The IC grooved pad was
mounted on the primary platen of the polishing machine and 20
precondition sweeps were carried out with deionized (DI) water to
precondition the polishing pad. The conditioning parameters for the
primary polishing pad were a downforce (DF) of 7 psi, 3 platen
sweeps (post with DI water), 70 rpm platen speed, and 75 rpm disk
speed. The Politex pad was mounted to the secondary table and
preconditioned with a 6" stiff bristle hand brush and DI water with
8 scrapes and 8 brushes performed manually. The following
conditions were used during the polishing tests depending on the
semiconductor substrate being polished:
2TABLE 2 Polishing Test Conditions Parameter First Step Second Step
Time (seconds) 60 10 DF (psi) 2 0.5 Back Pressure (psi) 1 0 DF Ramp
(sec) 5 5 Carrier (rpm) 60 40 Table (rpm) 60 40 Slurry Flow
(ml/min) 150 0 Rinse Off On Notes: Duration of primary polishing on
sheet Cu wafers is 120 seconds, TaN is 60 seconds and silicon
dioxide (TEOS) is 120 seconds, respectively. Three Cu dummy wafers
were polished using control slurry for 60 seconds followed by
wafers used for monitoring the removal rates during the polishing
test. For each test slurry, 2 dummy oxide wafers were polished.
Removal Rate analysis was performed using a 25-point # polar
measurement site map on the CDE and SM-300. Edge exclusion was 10
mm for Cu and 10 for TaN and TEOS.
[0037]
3TABLE 3 Slurry Formulations Colloidal Particle Silica (wt
Slurry.sup.1 Diameter % of Tested CA BTA (nm) slurry) pH 1 0.192
0.1 12 8 to 9 8.0 2 0.192 0.1 12 8 to 9 8.5 3 0.192 0.1 12 8 to 9 9
4 0.192 0.1 12 8 to 9 9.5 5 0.192 0.1 12 8 to 9 10 6 0.192 0.1 12 8
to 9 10.5 .sup.1All concentrations are expressed as weight
percentages. Water comprises the remaining weight of the slurries.
CA = citric acid; BTA = benzotriazole.
[0038] The slurry formulations listed in Table 3 were utilized to
polish 6" wafers containing Cu, TaN, and SiO.sub.2(TEOS). The
metal, barrier and dielectric removal rates are summarized in Table
4, along with calculated selectivity ratios based on the observed
removal rates.
4TABLE 4 Removal Rates and Selectivity Ratios SiO.sub.2 Selectivity
Selectivity Slurry (TEOS) Ratio Ratio Tested Cu RR TaN RR RR
(TaN:Cu) (TaN:TEOS) 1 55 983 220 17.9:1 4.5:1 2 84 1260 245 15:1
5.1:1 3 86 1411 140 16.4:1 10.1:1 4 106 1126 175 10.6:1 6.4:1 5 123
1189 187 9.7:1 6.4:1 6 194 1305 156 6.7:1 8.4:1 Note: RR = Removal
Rate. All removal rates are in Angstroms per min.
[0039] Slurry formulations, A and B, of this invention are provided
in Table 5, with suitable and preferred ranges for various
additives, in % or ppm by weight by the slurry.
5TABLE 5 Slurry Formulations of This Invention Preferred Preferred
Additive A Range for A B Range for B pH .gtoreq.7 10-11 .gtoreq.7
8.5-9.5 Colloidal .ltoreq.30 10-20 .ltoreq.30 8-9 Silica (%)
Complexing .ltoreq.500 100-300 .ltoreq.5,000 3,000-5,000 Agent
(ppm) Corrosion .ltoreq.110 70-110 .ltoreq.110 70-110 Inhibitor
Oxidizing .ltoreq.15,000 5,000-10,000 -- -- Agent (ppm) Chloride
Salt -- -- .ltoreq.200 50-150 (ppm) Oxide -- -- .ltoreq.5,000
1,000-2,500 Suppressant Biocide (ppm) .ltoreq.200 90-150
.ltoreq.200 90-150
[0040] Although preferred embodiments are disclosed, other
embodiments and modifications of this invention are intended to be
covered by the spirit and scope of the appended claims.
* * * * *