U.S. patent application number 09/833949 was filed with the patent office on 2002-01-24 for reflow of low melt solder tip c4's.
Invention is credited to Cotte, John Michael, Datta, Madhav, Kang, Sung Kwon.
Application Number | 20020009869 09/833949 |
Document ID | / |
Family ID | 23412150 |
Filed Date | 2002-01-24 |
United States Patent
Application |
20020009869 |
Kind Code |
A1 |
Cotte, John Michael ; et
al. |
January 24, 2002 |
Reflow of low melt solder tip C4's
Abstract
An array of C4 solder bumps and a method for making is described
incorporating an array of conductive areas on an electrical device,
each conductive area having a layer of ball limited metalurgy at
the device surface and two layers of solder having respective
melting temperatures to form the C4 structure. The method includes
melting the second layer of solder in the down position or towards
earth to form a C4 solder ball or bump. The invention overcomes the
problem of low temperature solder from wicking over the sidewall
surfaces of the high melt solder of the C4 structure and attacking
the edges of the underlying seed layers of the ball limited
metalurgy.
Inventors: |
Cotte, John Michael; (New
Fairfield, CT) ; Datta, Madhav; (Hillsboro, OR)
; Kang, Sung Kwon; (Chappaqua, NY) |
Correspondence
Address: |
Robert M. Trepp
IBM Corporation
Intellectual Property Law Dept.
P.O. Box 218
Yorktown Heights
NY
10598
US
|
Family ID: |
23412150 |
Appl. No.: |
09/833949 |
Filed: |
April 12, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09833949 |
Apr 12, 2001 |
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09359061 |
Jul 21, 1999 |
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6258703 |
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Current U.S.
Class: |
438/612 ;
257/E21.508 |
Current CPC
Class: |
H01L 2924/01039
20130101; Y02P 70/50 20151101; H01L 2924/01047 20130101; H01L
2924/01327 20130101; H01L 2224/05023 20130101; H01L 2924/01006
20130101; H01L 2924/00013 20130101; H01L 2924/01029 20130101; H01L
2224/05568 20130101; H01L 2924/01022 20130101; H01L 2924/01024
20130101; H01L 2924/01074 20130101; H01L 2224/05001 20130101; H01L
2924/014 20130101; H01L 2224/13616 20130101; H01L 24/05 20130101;
H01L 2924/01322 20130101; H01L 2224/1357 20130101; H05K 2203/306
20130101; Y02P 70/613 20151101; H01L 2224/0508 20130101; H01L
2924/01033 20130101; H01L 2924/14 20130101; H01L 2224/13116
20130101; H05K 2201/2081 20130101; H05K 3/3436 20130101; H01L
2924/01013 20130101; H01L 24/11 20130101; H05K 3/3452 20130101;
H01L 2924/01049 20130101; H01L 2924/01082 20130101; H01L 2924/01078
20130101; H05K 2203/159 20130101; H01L 2224/1147 20130101; H01L
2224/13116 20130101; H01L 2924/0105 20130101; H01L 2224/13616
20130101; H01L 2924/0105 20130101; H01L 2924/00013 20130101; H01L
2224/13099 20130101; H01L 2924/00013 20130101; H01L 2224/29099
20130101 |
Class at
Publication: |
438/612 |
International
Class: |
H01L 021/44 |
Claims
Having thus described our invention, what we claim as new and
desire to secure as Letters Patent is:
1. A method for forming an array of C4 bumps on a first substrate
of an electrical device comprising the steps of: forming an array
of conductive areas on said first substrate, each conductive area
including a ball limited metalurgy to provide adhesion to said
first substrate and a diffusion barrier, forming a first layer of
solder having a first melting temperature on said conductive areas,
forming a second layer of solder having a second melting
temperature lower than said first melting temperature on said first
layer of solder, applying a first force on said first and second
layer of solder away from said ball limited metalurgy, and heating
said second layer of solder above said second melting temperature
to cause said molten second layer to flow into a shape determined
by said first force and a second force generated by said molten
second layer of solder to wick to the edges of said first layer of
solder, said first force adjusted to prevent said melted second
layer from wicking over exposed sidewall surfaces of said ball
limited metalurgy.
2. An array of C4 solder balls on a substrate of an electrical
device comprising: an array of conductive areas on said first
substrate, a first layer of solder having a first melting
temperature on said respective conductive areas, a second layer of
solder having a second melting temperature lower than said first
melting temperature on said first layer of solder on said
respective conductive areas.
3. The array of C4 solder balls according to claim 2 wherein said
first solder alloy is selected from the group consisting of 63% tin
37% lead, 60% indium 40% lead, 63% tin 36% lead 1% silver, 70%
indium 30% lead, 43% lead 43% tin 14% bismuth 80% indium 15% lead
5% silver, 51% tin 31% lead 18% cadmium, 97% indium 3% silver, 58%
bismuth 42% tin, 52% indium 48% tin, 46% bismuth 34% tin 20% lead
and 44% indium 42% tin 14% cadmium (by weight).
4. The array of C4 solder balls according to claim 2 wherein said
second solder alloy is selected from the group consisting of 97%
lead 3% tin, 95% lead 5% tin, 92% lead 5% indium 3% silver and 92%
lead 5% tin 3% silver (by weight).
5. A reflow method for an array of C4 bumps on a first substrate
wherein said C4 bumps includes a first layer of solder having a
first melting temperature on a second layer of solder having a
second melting temperature greater than said first melting
temperature on said first substrate comprising the steps of:
positioning said array of C4 bumps wherein said first layer of
solder is facing down with respect to said second layer of solder,
and reflowing said first layer of solder.
6. The reflow method according to claim 5, further including the
step of heating said C4 bumps to a temperature 20-40 degrees C
higher than said first melting temperature but below said second
melting temperature of said second solder.
7. The reflow method according to claim 5, wherein upon the
completion said step of reflowing, lowering the temperature of said
C4 back to below melting temperature while maintaining the
orientation of said first solder layer facing down.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the reflow of low
temperature solder interconnects, especially in microelectronics
fabrication.
BACKGROUND OF THE INVENTION
[0002] Controlled Collapse Chip Connection (C4) is an advanced
interconnect technology for microelectronic chip packaging. C4 is
also known as "flip chip," "solder bump" and "solder balls."
[0003] The basic idea of C4 is to connect chips, chip packages or
other such units by means of solder bumps partially collapsed
between the surfaces of two units. Each unit has a pad pattern
which corresponds to a mirror image pattern of the other. The bumps
of electrically conductive solder bridge the gap between respective
pairs of metal pads on the units being connected. As the units are
brought together, the solder bumps on the pads of the first unit
are pressed against the corresponding conductive pads on the second
unit, resulting in the partial collapse of the solder bump and
formation of an interconnect between respective pads. This allows
for the simultaneous formation of all interconnects between the
units in a single step, in spite of slight variations in the
surfaces of the units being joined.
[0004] In C4, the solder bumps are formed directly on the metal
pads of one unit. The pads are electrically isolated from each
other and other components by the insulating substrate that
surrounds each pad. The substrate may be un-doped silicon or some
other material. The bottom of each pad is in contact with a via,
forming electrical continuity with the chip circuitry.
[0005] A major application of C4 is in joining semiconductor
integrated circuit chips to chip packages. Integrated circuits are
fabricated from semiconductor wafers in an array of repeat
patterns, then diced into individual chips in order to minimize the
processing cost per chip. Once separated into individual units, the
chips are then assembled into packages large enough to handle. C4
bumps are placed on the chips prior to dicing, incorporating the
benefits of wafer scale processing.
[0006] Chip sizes are continually shrinking, while circuit
densities and I/O counts continue to increase, in order to enhance
performance and reduce costs. These trends place higher demands on
interconnects, making traditional bonding methods such as wire
bonding and tape automated bonding (TAB) very difficult. C4 allows
for very high density I/O with area array distribution as compared
to peripheral contacts in TAB and wire bonding.
[0007] C4 solder bumps serve two functions; first, they act as
electrical interconnects and second, they act to form a physical
bond between the semiconductor chip and package. This demands a
very precise placement of each C4 as well as uniform control of
solder volumes.
[0008] One method of forming solder bumps is by vacuum deposition.
A specially made mask with high precision vias is placed over the
wafer for locating the solder bumps. The entire assembly is then
placed into a vacuum chamber where solder is evaporated through the
mask to form solder bumps on the wafer. This deposition process is
non-selective, thereby solder deposits throughout the chamber as
well as on the mask. During deposition, the wafer and mask are
heated, therefore careful selection of mask material to match the
coefficient of thermal (CTE) expansion of the wafer is needed.
However, for this reason, the evaporation technique has limited
extendibility to larger wafers.
[0009] An alternative technique for making solder bumps is
electrodeposition, also called electrochemical plating or
electroplating. This method also uses a mask to form solder bumps
only at selected sites, but is vastly different than the
evaporation technique.
[0010] Electrodeposition of solder bumps requires a continuous
electrically conductive "seed layer" 14 adhered to the insulating
substrate. The seed layer 14 function is to carry current necessary
for electroplating the solder. FIG. 1A, labeled "prior art," shows
a wafer substrate 10 whose surface is overlaid with a conductive
layer 11 of either chromium (Cr) or a titanium tungsten alloy
(Ti--W). Metal layer 11 will function as part of the seed layer for
electrodepositing solder bumps. On top of layer 11 is deposited a
thin "phased" layer 12 of 50% chromium and 50% copper (Cr--Cu).
Finally, a third layer 13 of pure copper is deposited over the
entire wafer surface. The Cr or Ti--W, Cr--Cu and Cu layers are of
comparable thickness. Once seed layer 14 is deposited, the wafer is
coated with photoresist, patterned and then exposed. The unexposed
regions can then be developed or dissolved away to leave behind the
cured photoresist as a mask 16 shown in FIG. 1A. Photoresist mask
16 forms the desired pattern of holes or vias across the wafer.
[0011] The next step is the electrodeposition of solder into the
vias of the mask 16. All vias are filled simultaneously with the
desired volume of solder during the deposition process. An
electroplated solder bump 18 is shown in FIG. 1A. Once the solder
bumps 18 are formed, photoresist mask 16 is removed leaving behind
the solder bumps 18 and the continuous seed layer 14.
[0012] In order to electrically isolate solder bumps 18, it is
necessary to remove the seed layer 14 between solder bumps 18. This
is accomplished by etching away layers 11-13 with chemical or
electrolytic action, in either case the solder bump 18 protects the
layers 11-13 under it. FIG. 1B shows the seed layers 11-13 removed
to leave the solder bumps electrically isolated but mechanically
fixed to substrate 10. U.S. Pat. No. 5,486,282 (which is
incorporated herein by reference) discloses an invention related to
the selective removal of Cu and phased Cr--Cu by electroetching.
U.S. Pat. Nos. 5,462,638 and 5,800,726 (which are incorporated
herein by reference) disclose inventions related to the removal of
a Ti--W alloy layer by chemical etching. FIG. 1C shows solder ball
18', formed by melting or reflowing the solder bump 18 of FIGS.
1A-1B. At this stage the solder ball is ready for joining.
[0013] Solder alloys used in C4 interconnects generally consist of
lead (Pb) and tin (Sn). One characteristic used to select the
solder alloy is the melting temperature. Conventionally chips were
joined to multi-layer ceramic (MLC) substrates which could
withstand temperatures greater than 350.degree. C. However, there
is a growing need to attach chips to organic packages, as well as
direct chip attach (DCA) to organic boards such as FR4 boards,
which can generally only withstand temperatures less than
300.degree. C. A Pb--Sn alloy used for the high temperature
application may contain 97% Pb and 3% Sn by weight which melts at
353.degree. C., and for the low temperature application may contain
37% Pb and 63% Sn by weight (eutectic PbSn) which melts at
183.degree. C.
[0014] During the reflow of solder bump 18 to form solder ball 18',
Sn present in the solder reacts with the upper most Cu region of
the third layer 13 of Cu, to form an intermetallic (Cu.sub.x
Sn.sub.y) where x is 6 and y is 5 or where x is 3 and y is 1. This
intermetallic layer forms a strong bond between the solder ball 18'
and the third layer 13 of Cu. In the high temperature application,
with minimal Sn present (3 Wt. %), the degree of intermetallic
formation is self limiting. However, in the low temperature
application, with eutectic PbSn solder (63 Wt. % Sn), the excessive
amount of Sn can react with and consume the underlying third layer
13 of Cu, degrading the solder-seed layer interface.
[0015] One method of forming a low temperature C4 structure is by
capping a high temperature C4 bump with low temperature eutectic
Pb--Sn solder, such as described in U.S. Ser. No. 08/710,992 filed
Sep. 25, 1996 by Berger et al. entitled "Method for Making
Interconnect for Low Temperature Chip Attachment" (IBM Docket
YO996073) and assigned to assignee herein which is incorporated
herein by reference. However, this method does not address the
issue of low temperature solder wicking down around the high
temperature C4 structure and attacking seed layer 14 from the side
or exposed edge.
SUMMARY OF THE INVENTION
[0016] Accordingly, the present invention relates to a process of
forming a low temperature tip C4 ball with minimal attack on the
edges of the underlying seed layer by reaction with Sn from the low
melting solder tip. In particular, the invention provides a method
of reflowing a low temperature eutectic tip C4 structure with
minimal wicking of the molten low melt solder down the side wall of
the high melt solder of the C4 during intermediate reflow prior to
assembly. A low melting solder tip C4 bump, reflowed with the
molten tip facing down in the direction of the earth's
gravitational field or force, has been shown to have significantly
less wicking of the molten solder up the side wall of the high melt
C4 structure. The reduced wicking prevents the attack on the edges
of the underlying seed layers by inhibiting the interaction of Sn
along the side of the C4 structure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIGS. 1A-1C are enlarged, cross-sectional views of C4 solder
ball formation by electroplating in accordance with the prior
art.
[0018] FIG. 2A is an enlarged, cross-sectional view of an
electrochemically fabricated C4 bump made up of about half high
melt and half low melt solder.
[0019] FIG. 2B is a Scanning Electron Microscope (SEM) micro graph
of an electrochemically fabricated C4 bump made up of about half
high melt and half low melt solder.
[0020] FIG. 3A is an enlarged, cross-section view of an
electrochemically fabricated C4 ball, reflowed with molten tip
facing up with respect to earth during reflow.
[0021] FIG. 3B is an enlarged view of a portion of FIG. 3A.
[0022] FIG. 3C is an SEM micro graph of electrochemically
fabricated C4 ball, reflowed with low melt solder tip facing up
with respect to earth during reflow.
[0023] FIG. 4A is an enlarged, cross-section view of an
electrochemically fabricated C4 ball, ref lowed with the low melt
solder tip facing down with respect to earth during reflow.
[0024] FIG. 4B is an enlarged view of a portion of FIG. 4A showing
the forces on molten solder of a solder bump.
[0025] FIG. 4C is an SEM micro graph of an electrochemically
fabricated C4 ball, reflowed with molten tip facing down with
respect to earth during reflow.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0026] The present invention relates to a method of forming a low
temperature tip C4 ball, with minimal degradation of the
solder-seed layer interface during the preliminary reflow. More
specifically, the method was developed to reflow a dual solder
alloy C4 bump 24 shown in FIGS. 2A-2B, where the lower portion 26
of solder bump 24 is made of a high melt solder for example 97% Pb
and 3% Sn by Wt., and the upper portion 28 is made of a low melt
solder for example eutectic Pb--Sn, 37% Pb and 63% Sn by Wt. This
dual alloy C4 bump 24 may be electrochemically fabricated by the
process described in the related art, with the modification of
plating a dual layer solder structure as opposed to a single alloy
structure.
[0027] In order to form a uniform array of C4 solder balls, solder
bumps 24 are reflowed. In the reflow of a dual solder, low melt tip
C4 bump 24, the temperature is raised above the melting temperature
of the low melt solder (>183.degree. C. for eutectic Pb--Sn).
The high melt solder base 26 remains intact while the low melt tip
18' transforms to the liquid state.
[0028] For a liquid such as molten solder in contact with a solid,
the equilibrium shape of the liquid is defined by the minimal total
interfacial energy for all phase boundaries present. In the case of
molten low melt PbSn solder 18' in contact with solid high melt
PbSn solder 26, the stable configuration or lowest energy state
results in the spreading of the liquid solder 18' over the surface
of the solid (also known as wetting). The combination of the forces
due to wetting on liquid solder 18' on sidewall 31 is shown by
arrow 36 in FIG. 3B and the force due to gravity or acceleration,
linear or centrifugal on liquid solder 18' at sidewall 31 is shown
by arrow 38 in FIG. 3B. The forces on liquid solder 18' shown by
arrows 36 and 38 results in the encapsulation of the high melt
standoff structure 26 by the molten low melt solder 18', as shown
in FIGS. 3A-3C. As the low melt solder 18' wets sidewall 31 of high
melt base 26, it wicks down the sidewall 31 and comes into contact
with the edges of underlying seed layers 11-13. In the case of
eutectic Pb--Sn tip C4s, the Sn present reacts with the underlying
Cu, to form excessive Cu.sub.xSn.sub.y intermetallics where x is
equal to 6 and y is equal to 5 and degrades the edge of solder-seed
layers 11-13 of interface 14.
[0029] The present invention addresses the issue of the molten
solder wicking in a dual alloy C4 bump during preliminary reflow.
By reflowing the dual layer C4 structure 40 with the low melt
solder tip 42 facing down with respect to earth as shown in FIG.
4A, the wetting forces shown by arrow 36' in FIG. 4B act to cause
the molten solder 42' to wet and wick along the sidewall 31 of C4
structure 40. The wetting forces shown by arrow 36' are offset by
the force of gravity or by acceleration as shown by arrow 38' in
FIG. 4B. By controlling the volume of the molten solder 42', the
weight of the molten droplet can be used to prevent the wicking
along the sidewall 31 of high melt solder base 26 of C4 structure
40. This method of reflowing a dual alloy C4 solder bump, with the
low melt tip facing down with respect to earth in the direction of
the gravitational force, prevents the contact of the high Sn
containing molten solder 42' with the seed layers 11-13, as shown
in FIGS. 4A-4C. The combination of gravity in one direction and the
wetting force or surface tension in the opposite direction prevent
the molten low melt solder 42' from flowing down the high melt
solder standoff 26 and sidewall 31.
[0030] In FIGS. 1A through 4C of the drawing, like references are
used for elements or components corresponding to elements or
components of an earlier figure.
[0031] The reflow method of this invention is also applicable to
structures other than dual alloy C4 solder structures 40, for
instance, stud or column solder structures.
[0032] While there has been described and illustrated a method for
reflow of low temperature solder tip C4's having a high melt solder
standoff or base, it will be apparent to those skilled in the art
that modifications and variations are possible without deviating
from the broad scope of the invention which shall be limited solely
by the scope of the claims appended hereto.
* * * * *