U.S. patent application number 09/851215 was filed with the patent office on 2001-10-11 for split-gate flash cell for virtual ground architecture.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. Invention is credited to Hsieh, Chia-Ta, Kuo, Din-Son, Lin, Yai-Fen, Sung, Hung-Cheng.
Application Number | 20010028577 09/851215 |
Document ID | / |
Family ID | 23567533 |
Filed Date | 2001-10-11 |
United States Patent
Application |
20010028577 |
Kind Code |
A1 |
Sung, Hung-Cheng ; et
al. |
October 11, 2001 |
Split-gate flash cell for virtual ground architecture
Abstract
In this invention bit lines are ion implanted into a
semiconductor substrate in columns beside floating gates of an
array of flash memory cells. A control gate overlays each row
floating gates and operates as a word lines for the rows of flash
memory cells. Each bit line serves a dual purpose of providing a
drain for one cell and a source for the adjacent cell. The flash
memory cells are programmed, erased and read depending upon the
voltages applied to the buried bit lines and the word line
structured as a control gate that extends the length of each row.
By implanting the bit lines into the semiconductor substrate the
flash memory cell can be made smaller improving the density of the
flash memory.
Inventors: |
Sung, Hung-Cheng; (Hsin-chu,
TW) ; Kuo, Din-Son; (Hsin-chu, TW) ; Hsieh,
Chia-Ta; (Tainan, TW) ; Lin, Yai-Fen;
(Hsin-chu, TW) |
Correspondence
Address: |
George O. Saile
20 McIntosh Drive
Poughkeepsie
NY
12603
US
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY
|
Family ID: |
23567533 |
Appl. No.: |
09/851215 |
Filed: |
May 8, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09851215 |
May 8, 2001 |
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09396519 |
Sep 15, 1999 |
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6249454 |
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Current U.S.
Class: |
365/185.18 ;
257/E21.682; 257/E27.103 |
Current CPC
Class: |
H01L 27/115 20130101;
G11C 16/0425 20130101; H01L 27/11521 20130101 |
Class at
Publication: |
365/185.18 |
International
Class: |
G11C 016/04 |
Claims
What is claimed is:
1. A split gate flash memory array, comprising: a) a plurality of
floating gates organized in rows and columns on a semiconductor
substrate, b) a plurality of buried bit lines implanted into said
substrate and running the length of said columns of said floating
gates, c) each buried bit line laying beside and extending beneath
said columns of said floating gates, d) a plurality of control
gates patterned in polysilicon over said rows of floating gates, e)
each control gates extending the length of each row of floating
gates and forming a word line for that row of floating gates.
2. The split gate flash memory array of claim 1, wherein said
buried bit lines operate as sources and drains during memory cell
program and read cycles.
3. The split gate flash memory array of claim 1, wherein an
insulating layer of ONO (oxide-nitride-oxide) separates said
floating gates from said control gates.
4. The split gate flash memory array of claim 1, wherein voltages
applied to said control gates and said buried bit lines allows said
floating gates to be programmed and read.
5. The split gate flash memory array of claim 1, wherein said
floating gates are erased by means of Fowler-Nordheim tunneling
when a positive voltage of sufficient magnitude is applied from
said buried bit lines to said control gates.
6. A method for producing a split gate multiple storage flash cell,
comprising: a) forming gate oxide on a semiconductor substrate, b)
forming an array of floating gates on surface of said substrate
organized in rows and columns, c) patterning and ion implanting
buried bit lines between said columns of floating gates, d) forming
a layer of ONO (oxide-nitride-oxide) over said floating gates, e)
depositing a layer of polysilicon over surface of said substrate,
f) patterning and etching said layer of polysilicon to form control
gates overlaying said rows of floating gates.
7. The method of claim 6, wherein patterning and ion implanting
said buried bit lines is continuous for a length of the columns of
said floating gates where each buried bit line lies adjacent to and
extends partially under a first column of floating gates and is
separated from a second column of floating gates.
8. The method of claim 6, wherein patterning and etching said
polysilicon to form said control gates is continuous for a length
of a row of floating gates and produces a word line for each row of
said floating gates.
9. A method of programming a flash memory cell constructed with
buried bit lines used as sources and drains, comprising: a)
applying a first positive voltage of high magnitude to a control
gate overlaying a row of flash memory cells containing a first cell
to be programmed, b) applying a second voltage of moderate
magnitude to a first buried bit line laying beside and partially
extending under a first floating gate of said first cell, c)
applying zero volts to a second buried bit line laying beside and
partially extending under a second floating gate of an adjacent
second cell and separated from the first buried bit line by a
channel length, d) floating all other bit lines overlaid by said
control gate, e) connecting semiconductor substrate to zero volts,
f) maintaining voltages and connections until a predetermined
threshold voltage is reached on said cell being programmed.
10. The method of programming a flash memory cell of claim 9,
wherein said second buried bit line is operating as a source
providing a heavy flow of electrons from which ionized electrons
are injected into said first floating gate to program said first
cell.
11. The method of programming a flash memory cell of claim 9,
wherein said control gate overlaying a row of flash memory cells
operates as a word line.
12. A method of reading a flash memory cell constructed with buried
bit lines used as sources and drains, comprising: a) applying a
first positive voltage of moderate magnitude to a control gate
overlaying a row of flash memory cells containing a first cell to
be read, b) applying zero volts to a first buried bit line laying
beside and partially extending under a first floating gate of said
first cell, c) applying a second voltage of moderate magnitude less
than said first voltage to a second buried bit line laying beside
and partially extending under a second floating gate of an adjacent
second cell and separated from the first buried bit line by a
channel length, d) applying zero volts to all other bit lines
laying beside memory cells overlaid by said control gate, e)
connecting semiconductor substrate to zero volts, f) reading said
first cell by detecting conduction of transistor of said first
cell.
13. The method of reading a flash memory cell of claim 12, wherein
said first buried bit line is operating as a source and said second
buried bit line is operating as a drain.
14. The method of reading a flash memory cell of claim 12, wherein
said control gate overlaying a row of flash memory cells operates
as a word line.
15. A method of erasing a flash memory cell constructed with buried
bit lines used as sources and drains, comprising: a) applying a
high positive voltage to buried bit lines laying beside and
partially under floating gates flash memory cells, b) applying zero
volts to a control gate overlaying floating gates of cells to be
erased, c) applying zero volts to semiconductor substrate, d)
maintaining voltages and connections until threshold of said cells
fall below a predetermined threshold voltage level.
16. The method of erasing a flash memory cell of claim 15, wherein
erasing said floating gates is done by means of Fowler-Nordheim
tunneling.
17. The method of erasing a flash memory cell of claim 15, wherein
applying said high positive voltage to said buried bit lines erases
only those cells adjacent to said buried bit lines and laying under
said control gate.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of Invention
[0002] This invention relates to semiconductor memories and in
particular split gate flash memory cells.
[0003] 2. Description of Related Art
[0004] Split gate flash memory technology requires a relatively
large cell size compared to other type memory technologies. This is
in part caused by misalignment problems and not being able to take
advantage of self alignment techniques. Some designs of flash
memory cells have multiple storage bits per each memory cell to
accommodate the increased demand storage density, but this usually
comes with an increased program current.
[0005] In U.S. Pat. No. 5,838,618 (Lee et al.) a method is
disclosed to erase data from a flash EEPROM while electrical
charges trapped in the tunneling oxide are eliminated to maintain
separation of the programmed and erased thresholds. In U.S. Pat.
No. 5,508,995 (Zimmer et al.) is described a split gate EPROM cell
with buried bit lines on either side of a storage cell. The source
for the EPROM cell is in part a buried bit line on one side of the
storage cell and the drain is in part a buried bit line on the
other side of the cell. In U.S. Pat. No. 5,440,158 (Sung-Mu) is
shown an EPROM cell with dual sidewall floating gates. Source and
drain regions are formed between and on either side of the floating
gates and a control gate is formed over the floating gates. In U.S.
Pat. No. 5,067,108 (Jenq), an electrically conductive
re-crystallized floating gate is disposed over an insulating area
extending over a portion of a channel region and a drain region. A
control gate partially overlaps the floating gate and extends over
a portion of a source region.
[0006] With the demands for increased density for flash memory
chips, it is important to create a small cell size that can be easy
to shrink. The demand for increased density will require a solution
to the misalignment problem in conventional split gate flash
memories, and the minimizing of requirements for metalization and
contact areas. To deal with the density requirement a cell
architecture is required that has floating gates with source and
drain areas that are in part a portion of buried bit lines and a
control gate that extends beyond the cell to form in part a word
line for the flash memory. Doing these items of improvement can
produce an architecture for a split gate flash memory cell that
will allow the cell to be reduced in size producing a higher flash
memory density.
SUMMARY OF THE INVENTION
[0007] In this invention bit lines for a flash memory are ion
implanted into a semiconductor substrate. The bit lines lay beside
and extend partially under each column of floating gates and run
the length of each column. A control gate is formed over each row
of floating gates and runs the length of each row. The control gate
of each row of floating gates serves as a word line for that row.
Combinations of voltages applied to a control gate overlaying a row
of floating gates and to bit lines on either side of a floating
gate in that row, allow the floating gate to be programmed, read
and erased. This invention is a virtual ground architecture since a
bit line acts as a drain for floating gates on one side of the bit
line with Vcc being applied and acts as a source for floating gates
on the opposite side of the bit line with zero volts being
applied.
[0008] Bit lines are alternately used as drains and sources as spit
gate transistors are formed between adjacent columns. A bit line
physically associated with a first column of floating gates and
separated from a second column by a channel length in the
semiconductor substrate is a source for the split gate transistors
formed between the first and second columns of floating gates. A
bit line physically associated with the second column and partially
laying under the floating gates of the second column is the drain
for the split gate transistors formed between the first and second
columns. In like manner, the bit line physically associated with
the second column and spaced by a channel length from the floating
gate of a third column is a source for the split gate transistors
formed between the second and third columns. The buried bit line
physically associated with the third column is the drain for the
split gate transistors formed between the second and third
columns.
[0009] A flash memory cell comprises a floating gate with a buried
bit line extending partially under the floating gate, a buried bit
line from an adjacent column separated from the floating gate by a
portion of a channel length, and a control gate running the length
of the row containing the floating gate. The flash memory cell is
programmed by applying a high voltage to the control gate, a
moderate voltage to the bit line lay beside and extending partially
under the floating gate, and applying zero volts to the bit line in
the adjacent column. Electrons flowing from the bit line of the
adjacent column gain energy as they flow through the channel
between the two bit lines and are injected into the floating gate
caused by impact ionization in the channel. The floating gate is
erased by applying a high voltage to the surrounding bit lines and
zero volts to the control gate. The erasure that removes electrons
from the floating gate is done by means of Fowler-Nordheim
tunneling from the floating gate and the bit line partially
extending under the floating gate. The floating gate is read by
applying a moderate voltage to the control gate, applying a
moderate voltage of lower magnitude than that applied to the
control gate to the buried bit line from the adjacent column and
applying zero volts to the buried bit line partially extending
under the floating gate being read.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] This invention will be described with reference to the
accompanying drawings, wherein:
[0011] FIG. 1 is a cross sectional view of a split gate flash
memory cell of prior art,
[0012] FIG. 2a is a plan view of a portion of the flash memory
cells of this invention,
[0013] FIG. 2b, is a cross section view of a portion of flash
memory cells of this invention,
[0014] FIG. 3 is a chart of voltages required to program, erase,
and read the flash memory cells,
[0015] FIG. 4 is a flow diagram for forming the flash memory cells
of this invention,
[0016] FIG. 5 is a flow diagram for programming a flash memory cell
of this invention,
[0017] FIG. 6 is a flow diagram for reading a flash memory cell of
this invention, and
[0018] FIG. 7 is a flow diagram for erasing a flash memory cell of
this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0019] Referring to FIG. 1, two flash memory cells of prior art are
shown comprising floating gates 10 and 11 separated from control
gates 12 and 13 by an insulating layer of ONO (oxide-nitride-oxide)
14. A metal land 15 is connected to a drain 17 in a semiconductor
substrate 18 by a metal plug 16. The size and the separation of the
two flash memory cells is limited by the need to make contact from
the metal land 16 to the drain 17. If the spacing that is
maintained between the metal plug 16 and the adjacent control gates
12 and 13 is minimal, misalignment of the metal plug 16 through the
inter-metal dielectric 19 can cause electrical shorts. Therefore, a
minimum spacing needs to be maintained between the metal plug 16
and the adjacent control gates 12 and 13 that restricts the size
reduction of the flash memory cells.
[0020] In FIG. 2a is shown a plan view of a portion of a flash
memory of this invention. Bit lines 30 are buried into a
semiconductor substrate 34 by means of imaging using photo resist
or the equivalent and ion implantation. The bit lines 30 lay beside
columns of floating gates 31 of the flash memory and extend
partially beneath each floating gate 31 and 32 in the column.
Overlaying each row of floating gates is a control gate 33
extending the length of the row and forming a word line for that
row. In FIG. 2b is shown the cross section view of a portion of the
flash memory of this invention. The floating gates 31 are formed on
the semiconductor substrate 34 over gate oxide 35. A layer of ONO
separates and isolates the floating gates 31 from the control gates
33.
[0021] Continuing to refer to FIGS. 2a and 2b and referring to FIG.
3, three floating gates (FG-1) 40, (FG-2) 41 and (FG-3) 42 are
shown for illustrative purposes to explain FIG. 3 associated with
three buried bit lines (BL-1) 43, (BL-2) 44 and (BL-3) 45 and two
channel regions 46 and 47. To program cell 2 a charge is injected
onto FG-2. This is done by applying a large voltage of
approximately about 7V to the control gate 33, applying a moderate
voltage of approximately about 3V to bit line BL-2, applying 0V to
bit line BL-1 and floating bit line BL-3 with the substrate 34 held
at 0V. A high current flows in the channel 46 of the transistor
formed between BL-1 and BL-2 and under the control gate 33.
Ionization is formed in the channel 46 near the floating gate from
which hot electrons are injected into the floating gate FG-2. The
bit line BL-1 acts a the source of the transistor and bit line BL-2
acts as the drain. To program cell 3 charge is injected onto
floating gate FG-3. Here bit line BL-2 becomes the source and bit
line BL-3 is the drain. Bit line BL-1 is left floating and charge
from the hot electron effect in channel 47 is injected into
floating gate FG-3. This is done by applying a high voltage of
approximately about 7V to the control gate 33, connecting 0V to bit
line BL-2 acting as a source and connecting approximately about 3V
to bit line 3 acting as a drain with the substrate 34 held at 0V.
All other bit lines intersecting and laying under control gate 33
are floating as represented by bit line BL-1.
[0022] Continuing to refer to FIG. 3 along with FIGS. 2a and 2b,
Flash memory cells containing floating gates FG-1, FG-2, and FG-3
are erased by applying a high voltage of approximately about 8V to
bit lines BL-1, BL-2 and BL-3 with the control gate 33 and the
substrate 34 connected to 0V. This removes charge from the floating
gates by means of Fowler-Nordheim tunneling until a predetermined
threshold voltage is reached which defines the cells as being
erased, or not programmed. The flash memory cell containing
floating gate FG-2 is read by applying a moderate voltage of
approximately about 3V to the control gate 33, applying a moderate
voltage of approximately about 2V to bit line BL-1 operating as a
drain and 0V to bit line BL-2 operating as a source. Current flows
between bit lines BL-1 and BL-2 when the floating gate FG-2 has a
low charge resulting in a low threshold voltage and is detected by
a sense amplifier. When the charge on the floating gate FG-2 is
high (programmed state) no current flows between the two bit lines
BL-1 and BL-2 and into the sense amplifier. To read the cell
containing FG-3 a moderate voltage of approximately about 3V is
applied to the control gate 33, bit line BL-2 now operating as a
drain has a moderate voltage of approximately 2V applied and bit
line BL-3 is connected to 0V. All other bit lines, represented by
BL-1, are connected to 0V. Current flows between bit lines BL-2 and
BL-3 when the floating gate FG-3 has a low charge resulting in a
low threshold voltage and is detected by a sense amplifier. When
the charge on the floating gate FG-3 is high (programmed state) no
current flows between the two bit lines BL-2 and BL-3 and into the
sense amplifier.
[0023] Referring to FIG. 4, a method for forming a split gate flash
memory with buried bit lines is shown. A gate oxide is formed over
a semiconductor substrate 50. The thickness of the gate oxide is in
a range of 80 A to 100 A. An array of floating gates arranged in
rows and columns are formed over the gate oxide 51. Buried bit
lines are patterned and ion implanted into the semiconductor
substrate along side the columns of floating gates 52. The bit
lines extend partially under the columns of floating gates beside
which they lay. Phosphorous ions are implanted into the substrate
to form the buried bit lines having an expected energy of 40 KeV
with a range of approximately about 40 KeV minimum and 60 KeV
maximum. The implant dosage has an expected value of 2E15
ions/cm.sup.2 with a range of approximately about 2E15
ions/cm.sup.2 minimum and 5E15 ions/cm maximum. The depth of the
buried bit lines is expected to be 0.3 u with a range of
approximately about 0.2u minimum and 0.4u maximum. After the bit
lines are implanted into the substrate an insulation of ONO
(oxide-nitride-oxide) is formed over the surface of the substrate
and the floating gates 53. Next polysilicon is deposited over the
surface of the substrate 54. Control gates are patterned and formed
over rows of the floating gates 55. Each row of floating gates is
covered by a separate control gate that extends the full length of
the row and serves as a word line for the split gate flash
memory.
[0024] In FIG. 5 is shown the method of programming a split gate
flash memory cell that has bit lines buried into a semiconductor
substrate. A high voltage is applied to a control gate overlaying
the row containing the flash memory cell to be programmed 60. A
moderate voltage is applied to a first bit line laying beside and
partially under the floating gate of the flash memory cell to be
programmed 61. Zero volts is applied to a second buried bit line
separated from the first buried bit line by the channel of the
split gate transistor of the cell to be programmed and laying
beside a floating gate of an adjacent flash memory cell 62. All
other bit lines associated with cells overlaid by the control gate
are left floating 63. The semiconductor substrate is connected to
zero volts 64, and all voltages are maintained until a
predetermined threshold voltage is reached for the split gate
transistor being programmed 65.
[0025] In FIG. 6 is shown the method of reading a split gate flash
memory cell that has bit lines buried into a semiconductor
substrate. A first moderate voltage is applied to the control gate
overlaying a row of split gate flash memory cells 70. Zero volts is
applied to a first buried bit line laying beside and partially
under the floating gate of the flash memory cell that is being read
71. A second moderate voltage lesser than the first moderate
voltage is applied to a second bit line separated form the first
bit line by the channel of the split gate transistor of the cell to
be read and laying beside a floating gate of an adjacent flash
memory cell 72. Zero volts is applied to all other bit lines
associated with cells overlaid by the control gate 73, and the
semiconductor substrate is connected to zero volts 74. The flash
memory cell is read by detecting the conduction of current of the
split gate transistor of the flash memory cell being read 75.
[0026] In FIG. 7 is shown the method of erasing split gate flash
memory cells that have bit lines buried into a semiconductor
substrate. A high voltage is applied to bit lines buried in a
semiconductor substrate that lay beside and partially under the
floating gates of the flash memory cells that are to be erased 80.
Zero volts is applied to the control gate overlaying the row of
flash memory cells to be erased 81, and zero volts is connected to
the semiconductor substrate 82. The voltages and connections are
maintained until the threshold voltage of the cells being erased
fall below a predetermined voltage level 83 which defines the flash
memory cells as being erased.
[0027] While the invention has been particularly shown and
described with reference to preferred embodiments thereof, it will
be understood by those skilled in the art that various changes in
form and details may be made without departing from the spirit and
scope of the invention.
* * * * *