U.S. patent application number 09/738403 was filed with the patent office on 2001-09-13 for high-speed programmable interconnect.
This patent application is currently assigned to Altera Corporation. Invention is credited to Cliff, Richard G., Huang, Joseph, Nguyen, Khai, Sung, Chiakang, Wang, Bonnie I., Wang, Xiaobao.
Application Number | 20010020851 09/738403 |
Document ID | / |
Family ID | 27574346 |
Filed Date | 2001-09-13 |
United States Patent
Application |
20010020851 |
Kind Code |
A1 |
Huang, Joseph ; et
al. |
September 13, 2001 |
High-speed programmable interconnect
Abstract
An improved interconnection between horizontal conductors and
the input to logic elements. A signal regeneration circuit is
provided in the path between the horizontal conductor and the logic
element, thereby isolating and boosting the signal. This allows for
faster switching operation. A path is provided allowing the
selective routing of signals from the horizontal conductors to the
vertical conductors, without passing through a logic element. Also,
a path is provided to allow a horizontal conductors to be routed to
any of a plurality of vertical conductors.
Inventors: |
Huang, Joseph; (San Jose,
CA) ; Sung, Chiakang; (Milpitas, CA) ; Wang,
Bonnie I.; (Cupertino, CA) ; Nguyen, Khai;
(San Jose, CA) ; Wang, Xiaobao; (Santa Clara,
CA) ; Cliff, Richard G.; (Milpitas, CA) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Altera Corporation
|
Family ID: |
27574346 |
Appl. No.: |
09/738403 |
Filed: |
December 15, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09738403 |
Dec 15, 2000 |
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09094356 |
Jun 9, 1998 |
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6262595 |
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60049243 |
Jun 10, 1997 |
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60049245 |
Jun 10, 1997 |
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60049275 |
Jun 10, 1997 |
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60049478 |
Jun 13, 1997 |
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60049246 |
Jun 10, 1997 |
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60052990 |
Jun 10, 1997 |
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60049247 |
Jun 10, 1997 |
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60050953 |
Jun 13, 1997 |
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Current U.S.
Class: |
326/41 |
Current CPC
Class: |
H03K 19/17736 20130101;
H03K 19/17792 20130101; G06F 11/2273 20130101; G01R 31/318555
20130101 |
Class at
Publication: |
326/41 |
International
Class: |
H01L 025/00 |
Claims
What is claimed is:
1. A programmable integrated circuit comprising: a plurality of
vertical interconnect conductors; a plurality of horizontal
interconnect conductors; and a buffer circuit to programmably
couple one of the plurality of vertical interconnect conductors to
any one of the plurality of horizontal interconnect conductors.
2. The programmable integrated circuit of claim 1 wherein the
buffer circuit further comprises: a first transistor coupled
between a first conductor in the plurality of vertical interconnect
conductors and a first node wherein a control electrode of the
first transistor is coupled to a first memory bit; a second
transistor coupled between a second conductor in the plurality of
vertical interconnect conductors and the first node wherein a
control electrode of the second transistor is coupled to a second
memory bit; a first buffer comprising an input coupled to the first
node; a multiplexer coupled to an output of the first buffer; and a
second buffer coupled to an output of the multiplexer.
3. The programmable integrated circuit of claim 1 wherein the
buffer circuit further comprises: a plurality of transistors
coupled to an output line of the buffer circuit, and each of the
plurality of transistors coupled to a different one of the
plurality of horizontal interconnect conductors.
4. The programmable integrated circuit of claim 3 further
comprising a plurality of memory cells, each coupled to a different
one of the plurality of transistors.
5. The programmable integrated circuit of claim 1 wherein the
buffer circuit drives a signal from one of the plurality of
vertical interconnect conductors to two of the plurality of
horizontal interconnect conductors.
6. The programmable integrated circuit of claim 1 wherein the
buffer circuit comprises: a first transistor to selectively couple
a first conductor of the plurality of vertical interconnect
conductors to a first output line; a second transistor to
selectively couple a second conductor of the plurality of vertical
interconnect conductors to the first output line; a third
transistor to hold the output line at a known voltage level when
the first and second conductors of the plurality of vertical
interconnect conductors are not coupled to the output line.
7. The programmable integrated circuit of claim 1 wherein the
buffer circuit may programmably couple an output of a logic element
to any one of the plurality of horizontal interconnect
conductors.
8. The programmable integrated circuit of claim 4 wherein the
memory cells are SRAM cells.
9. A programmable integrated circuit comprising: a plurality of
vertical interconnect conductors; a plurality of horizontal
interconnect conductors; and a buffer circuit to drive one of the
plurality of horizontal interconnect conductors to any one of the
plurality of vertical interconnect conductors.
10. The programmable integrated circuit of claim 9 wherein the
buffer circuit may drive more than one of the plurality of vertical
interconnect conductors.
11. A programmable integrated circuit of claim 9 wherein the buffer
circuit may drive an output from a logic element to the plurality
of vertical interconnect conductors.
12. A programmable integrated circuit of claim 9 wherein the buffer
circuit comprises: a first transistor coupled between one of the
plurality of horizontal interconnect and a first node, wherein a
control electrode of the first transistor is coupled to a memory
cell; an inverter coupled to the first node and providing an output
at a second node; a second transistor coupled between a first
supply and the first node, wherein a control electrode of the
second transistor is coupled to the second node; and a multiplexer
comprising a first input coupled to the second node, a second input
coupled to an output of a logic element.
13. A programmable integrated circuit comprising: a plurality of
horizontal interconnect conductors; a multiplexer to selectively
couple one of the plurality of horizontal interconnect conductors
to a local conductor of a logic array block; and a signal
regeneration circuit coupled between the multiplexer and the local
conductor to buffer a signal from the multiplexer.
14. A programmable integrated circuit of claim 13 wherein the
signal regeneration circuit comprises: a first inverter coupled
between the multiplexer and the local conductor; and a second
inverter coupled between the local conductor and the multiplexer.
Description
CROSS-REFERENCE TO RELATED CASES
[0001] This application claims priority from U.S. provisional
application Ser. No. 60/049,275, filed Jun. 10, 1997; Ser. No.
60/049,478, filed Jun. 13, 1997; Ser. No. 60/049,246, filed Jun.
10, 1997; Ser. No. 60/052,990, filed Jun. 10, 1997; Ser. No.
60/049,247, filed Jun. 10, 1997; Ser. No. 60/049,243, filed Jun.
10, 1997; Ser. No. 60/050,953, filed Jun. 13, 1997; and Ser. No.
60/049,245, filed Jun. 10, 1997, all of which are incorporated
herein by reference for all purposes.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to the field of programmable
logic devices, and more particularly, to interconnection resources
for programmable logic devices.
[0003] Logic devices and methods of their operation are well known
to those of skill in the art. Programmable logic devices have found
particularly wide application as a result of their combined low
up-front cost and versatility to the user. Altera's FLEX.RTM. line
of programmable logic are among the most advanced and successful
programmable logic devices. The FLEX architecture provides a large
matrix of small logic elements (also known as macrocells) that can
be programmably configured and interconnected to provide desired
logic functions.
[0004] In many programmable logic devices, for example, a number of
logic elements are arranged in groups to form larger entities
referred to as logic array blocks ("LABs"). The various LABs are
arranged in a two-dimensional array and are connectable to each
other and to I/O pins of the device though continuous lines that
run the entire length/width of the device. These lines are referred
to as horizontal interconnect and vertical interconnect or
collectively as "global" interconnect lines. In Altera's line of
production these may include what are referred to as "Horizontal
FastTracks.TM." and "Vertical FastTracks.TM.."
[0005] Each logic element can perform various combinational and
registered logical operations. A local interconnect resource is
also provided to allow the logic elements in a LAB to share signals
without using the global interconnection resources. Additional
detail regarding the FLEX devices may be found, for example, in
Altera's Data Book, January 1998, along with U.S. Pat. Nos.
5,260,610 and 5,260,611, all of which are incorporated herein by
reference for all purposes.
[0006] These logic devices have met with substantial success and
are considered pioneering in the area of programmable logic. While
pioneering in the industry, certain limitations still remain. For
example, a large portion of the delay in the critical path is due
to delay in the interconnect resources. A certain amount of delay
exists in the connection between the global interconnect structure
and the LABs. Thus a faster global interconnect can increase the
overall system performance significantly.
[0007] Another aspect of programmable logic integrated circuits
that may be improved is the programming flexibility of the
interconnect resources in the logic device. In currently available
devices, a signal may be routed from a vertical conductor to a
horizontal conductor without passing through a logic element, but
for a signal to be routed from a horizontal conductor to a vertical
conductor, it must pass through a logic element. Also, currently
available devices do not provide complete flexibility in routing
between horizontal and vertical lines. For example, at a particular
junction, a vertical conductor may only be connected to a single
horizontal conductor. It is desirable to be able to select from
among a plurality of vertical conductors as the destination,
thereby increasing the routing flexibility of the logic device.
[0008] For at least the above reasons, a PLD which provides faster
and more flexible interconnect resources is needed.
SUMMARY OF THE INVENTION
[0009] An improved programmable logic integrated circuit with
high-speed interconnection resources and greater routability is
described.
[0010] In accordance with a first aspect of the present invention,
a faster interconnection between the horizontal interconnect
resource and the local interconnect is provided. The local
interconnect provides a path to the logic inputs of the logic
elements. A signal regeneration circuit is provided in the path
between horizontal conductors and the local interconnection. The
signal regeneration circuit is preferably a pair of cross-coupled
inverters that isolate the capacitance of the horizontal
interconnect resource from the local interconnect, thereby allowing
the switching to occur at a faster rate. It also boosts the signal
allowing for faster switching operation.
[0011] In accordance with another aspect of the present invention,
improved routability between the horizontal and vertical
interconnects is described. A path is provided allowing the
selective routing of signals from the horizontal interconnect to
the vertical interconnect, without passing through a logic element.
The horizontal interconnect may be selectively coupled to several
of the vertical interconnect conductors in some embodiments.
[0012] In accordance with yet another aspect of the present
invention, improved routability between the vertical and horizontal
interconnects is described. A path is provided to allow a
horizontal interconnect to be routed to any of a plurality of
vertical interconnect conductors. In an embodiment, a multiplexer
allows the selection from a plurality of horizontal interconnect
conductors to be routed to the plurality of vertical interconnect
conductors.
[0013] A further understanding of the nature and advantages of the
present invention may be realized by reference to the remaining
portions of the specification and the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a diagram of a system incorporating a programmable
logic integrated circuit;
[0015] FIG. 2 is a block diagram of an exemplary architecture of a
programmable logic integrated circuit of the present invention;
[0016] FIG. 3 is a more detailed block diagram of the exemplary
architecture of a programmable logic integrated circuit of the
present invention;
[0017] FIG. 4 is a block diagram of the interconnection between
horizontal conductors and logic inputs to logic elements according
to the present invention;
[0018] FIG. 5 is a block diagram of the interconnection from
vertical interconnect conductors to horizontal interconnect
conductors according to the present invention;
[0019] FIG. 6 is a block diagram of the interconnection from
horizontal interconnect conductors to vertical interconnect
conductors according to the present invention;
[0020] FIG. 7 is a block diagram of clock routing scheme that may
be implemented in a programmable logic integrated circuit of the
present invention;
[0021] FIG. 8 is a logic diagram of a TTL buffer for the clock
routing scheme of FIG. 7; and
[0022] FIG. 9 is a logic element driver circuit for driving a fast
output from a logic element.
DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS
[0023] FIG. 1 illustrates a typical environment in which an
integrated circuit having been designed according to the principles
of the present invention may be embodied. A digital system 100 has
a processing unit 101 that is coupled with a memory 105 and an
input/output device 111. A personal computer is an example of
digital system 100; however, a wide variety of electronic and
consumer products will find beneficial use from the present
invention. For example, the present invention will find application
in telecommunications, switches, networks, and many other areas of
technology.
[0024] Digital system 100 contains one or more programmable logic
integrated circuits 121 of the type described in the present
invention. Programmable logic integrated circuit 121 may be, for
example, a programmable logic device (sometimes referred to as
PALs, PLAs, FPLAs, PLDs, EPLDs, CPLDS, EEPLDs, LCAs, or FPGAs.)
Programmable logic devices are described for example, in U.S. Pat.
No. 4,617,479, incorporated herein by reference for all purposes.
Such devices are currently represented by, for example, Altera's
FLEX.RTM. series of PLDs and are described, for example, in the
Altera Data Book, January 1998, which is incorporated herein in its
entirety by reference for all purposes. In FIG. 1, programmable
logic integrated circuit 121 is shown as a part of processing unit
101, but, memory 105 or input/output device 111 may also
advantageously contain programmable logic integrated circuit
121.
[0025] FIG. 2 is a simplified block diagram of the overall internal
architecture and organization of an exemplary programmable logic
integrated circuit 121. Many details of the architecture,
organization, and circuit design are not necessary for an
understanding of the present invention and such details are not
shown. The exemplary PLD of FIG. 2 shows an array of logic array
blocks (LABs) 200 interconnected by a global interconnect including
horizontal conductors 210 and vertical conductors 220. Each LAB 200
is a physically grouped set of logical resources including logic
elements 230.
[0026] Logic elements 230 within a LAB 200 can be programmably
coupled to each other and sometimes to logic elements 230 in an
adjacent LAB 200 by means of a local interconnect 240. Details of
LAB 200, logic elements 230, and local interconnect 240 may also be
found in the Altera Data Book, January 1998, previously
incorporated by reference. Other designs may also be preferentially
used. Horizontal and vertical conductors 210 and 220 may also be
coupled to input/output elements 250 for routing signals from
programmable logic integrated circuit 121.
[0027] FIG. 3 shows a more detailed block diagram of two LABs 200
and the interconnections between horizontal conductors 210,
vertical conductors 220, local interconnects 240, and LABS 200.
Each LAB 200 is coupled to the local interconnect 240 on its left
and the local interconnect to its right in the matrix. Other
architectures may also be used without departing from the spirit
and scope of the present invention.
[0028] FIG. 4 shows a block diagram of the programmable connections
between horizontal conductors 210 and the logic inputs to logic
elements 230. As mentioned above, horizontal conductors 210 are a
part of a global interconnection resource. They may extend across
several LABs 200, and possibly across the entirety of PLD 121.
Horizontal conductors 210 are coupled to the logic inputs of logic
elements 230 through local interconnect 240. Although only one
logic input of one logical element 230 is depicted in FIG. 4, it
will be recognized that the structure may be substantially
replicated many times to accommodate all of the logic inputs for
the logic elements in LAB 200.
[0029] One or more of horizontal conductors 210 are selectively
coupled to a signal regeneration circuit 310. In the specific
embodiment, a multiplexer 318 is provided to programmably select
from among a plurality of horizontal conductors 210 for connecting
one of them to signal regeneration circuit 310. Multiplexer 318 may
be a plurality of transistors 320 connected in parallel with the
source of each being coupled to differing ones of horizontal
conductors 210 and the drains being commonly coupled to an input of
signal regeneration circuit 310. A programming element 322 is
coupled to the gates of each of transistors 310 to allow one of the
paths to be selected.
[0030] Programming element 322 and other programming elements
described herein may be a memory cell. For example, in the specific
embodiment, programming element 322 is an SRAM cell.
[0031] Although any size multiplexer may be used, in the specific
embodiment multiplexer 318 is a 16-1 multiplexer. This arrangement
gives the user flexibility in selecting any one of 16 different
horizontal conductors 210 for routing to a particular line of local
interconnect 240.
[0032] Signal regeneration circuit 310 may be comprised of a pair
of cross-coupled inverting buffers 326 and 328. A transistor 329
may also be provided selectively coupling the input of signal
regeneration circuit 310 to GROUND. A reset signal is coupled with
the gate of transistor 329. This provides a method of initializing
the state of regeneration circuit 310 to a known state at the time
of resetting programmable logic integrated circuit 121.
[0033] Signal regeneration circuit 310 serves several functions
that is advantageous to the present invention. For example, it
isolates local interconnect 240 from the capacitance on horizontal
conductors 210. Thus, a signal on local interconnect 240 can switch
polarity at a faster rate than it would otherwise be able to
switch. Further, signal regeneration circuit 310 boosts the signal
also allowing it to switch at a faster rate.
[0034] Multiplexer 318 and signal regeneration circuit 310 may be
replicated a number of times. The output of each signal
regeneration circuit 310 is coupled to a different line of local
interconnect 240. In the specific embodiment, 22 instances of
multiplexer 318 and signal regeneration circuit 310 are provided.
Local interconnect 240 also has 10 lines that come from the outputs
of the corresponding LAB 200 making a total of 32 lines in each
local interconnect 240. In the specific embodiment, half of the 10
lines come from the LAB 200 to the right of local interconnect 240,
and half come from the LAB 200 to the left of local interconnect
240.
[0035] The individual lines in local interconnect 240 may be
programmably coupled to the logic inputs of logic elements 230 by a
logic input selector circuit 330. Logic input selector circuit 330
provides a multiplexer 340, the output of which is coupled to one
of the logic inputs of logic element 230. Multiplexer 340 may
comprise a number of transistors 345 coupled in parallel, with the
gates of transistors 345 being coupled to programmable elements
348. Each of the inputs to multiplexer 340 are coupled to traces
that extend perpendicularly to local interconnect 240. Transistors
345 are coupled between the individual lines of local interconnect
240 and the traces.
[0036] Logic input selector 330 provides a logic input to one of
logic elements 230. In the specific embodiment, each logic element
230 has four inputs, and each LAB 200 has 10 logic elements 230.
Thus, the circuitry shown in FIG. 4 is replicated 40 times, once
for each logic input to the LAB. In the specific embodiment, two of
the inputs to each logic element 230 may be coupled to the local
interconnect from LAB 240 to its left, and the other two may be
coupled to the local interconnect from LAB 240 to its right.
[0037] FIG. 5 shows a column interconnect 500. Column interconnect
500 provides a path for coupling horizontal conductors 210 or local
interconnect 240, to vertical conductors 220. One of horizontal
conductor 210 is coupled to an input of a multiplexer 510 through a
transistor 515. The gate of transistor 515 is coupled to a
programmable element 518. One of the local interconnect lines 240
is coupled to another input of multiplexer 510. The selection input
to multiplexer 510 is coupled to a programmable element (not shown)
for selecting which input is to be routed to the output of
multiplexer 510.
[0038] The specific embodiment includes inverting buffers 530 and
532 on the inputs of multiplexer 510, and an inverting buffer 534
on the output of multiplexer 234. The output of inverting buffer
534 is selectively coupled to one of the vertical conductors 220
through a transistor 540 with a programming element 542 coupled to
its gate. In some embodiments, the output may be coupled to a
plurality of vertical conductors 220.
[0039] A pull-up transistor 560 is coupled between transistor 515
and inverting buffer 530. Pull-up transistor 560 is a p-type device
and has a gate coupled to the output of inverting buffer 530. This
boosts the signal as it passes through column interconnect 500. A
pull-down transistor 565 is also provided between transistor 515
and inverting buffer 530. A NAND gate 570 is coupled to the gate of
pull-down transistor 565. NAND gate 570 is coupled to programming
element 518 and to the inverse of a reset signal. Thus, when the
horizontal conductor path through transistor 515 is not selected,
the input to inverting buffer is pulled to GROUND. It is also
pulled to GROUND when the reset signal is asserted.
[0040] FIG. 6 shows a row interconnect circuit 600. Row
interconnect circuit 600 provides a path for one or more vertical
conductors 220 to one or more horizontal conductors 210. A path is
also provided to route the output from one of the logic elements
230 to one or more horizontal conductors 210.
[0041] In the specific embodiment, row interconnect circuit 600 is
coupled to two of the vertical conductors 220. A multiplexer 610
selects between the two vertical conductors. Multiplexer 610 is
programmable and may be constructed in a manner similar to the
multiplexers described above using transistors 612 and 614, each of
which has its gate coupled to programmable elements 616 and 618,
respectively.
[0042] The output of multiplexer 610 is coupled through an
inverting buffer 620 to another multiplexer 624. Multiplexer 620 is
also coupled at its other input to the output of a logic element
230 through an inverting buffer 626. The output of multiplexer 624
is coupled through an inverting buffer 628 to all of the horizontal
conductors 210 through transistors 630-636, each of which has a
programmable elements 640-646 coupled to its gate. In some
embodiments, the output may only be coupled to a subset of
horizontal conductors 210.
[0043] Row interconnect circuit 600 also has a pull-up transistor
650 that is coupled the output of multiplexer 610 to boost the
signal from vertical conductor 210. It also includes a pull-down
transistor coupled to the output of multiplexer 610. A NAND gate
660 and an OR gate 665 are coupled to the gate to turn pull-down
transistor 655 on when neither programmable elements 616 and 618
are activated, or when the reset signal is activated.
[0044] FIG. 7 depicts a clocking scheme that may be implemented in
programmable logic integrated circuit 121 of the present invention.
A clock is typically used throughout the programmable logic
integrated circuit 121 to allow synchronous operation. It is
desirable in an integrated circuit to reduce the amount of clock
skew. A large clock skew will degrade the overall system
performance, since the device can only operate as fast as its
slowest path.
[0045] In the specific embodiment, two clock skew components can be
identified. Inter-row clock skew is the amount of skew between the
horizontal rows, while inter-column clock skew is the amount of
skew between the elements in a column for each row.
[0046] Referring to FIG. 7, a TTL buffer 710 is placed along each
row of integrated circuit 121. Each TTL buffer 710 is coupled to a
clock pin 720. A typical integrated circuit will have a plurality
of clock pins 720. By this arrangement, each row has a similar
clock skew. Thus, the clock skew is determined by the inter-column
clock skew alone. of further advantage, since TTL buffer 710 is
repeated for each row, the clock signal is driven to each row by
the external driver, which is typically much larger than TTL buffer
710. Clock pins 720 are preferably centered along the left and
right edges of integrated circuit 121 to further balance the
clocking skews.
[0047] FIG. 8 shows a more detailed circuit diagram of TTL buffer
710. TTL buffer 710 includes a 4:1 multiplexer 810. Multiplexer 810
includes three control inputs (MODE 820, NRFAST 822, and RLEONE1
824.) Control inputs 820-824 determine which of the four input
lines TTL buffer 710 will drive. In the specific embodiment, TTL
buffer 710 is coupled to four different inputs through inputs 830,
832, 834, and 836. Clock input 830 is coupled to the clock pin. LE
inputs 832 and 834 are coupled to fast outputs of logic element
230, and JTAG input 836 is coupled to a JTAG input. The decoder
table in FIG. 8 shows how each line is selected by the values on
control inputs 820-824. The inverse of a reset signal is provided
on a reset input 840 which is coupled to a NAND gate 842. This
drives the output to GROUND when the reset signal is activated.
[0048] Input 830 is coupled to the output through two inverting
buffers 850 and 852. The output of multiplexer 810 is coupled to an
output of TTL buffer 710 through a buffer 860 which drives the fast
signal to the rows.
[0049] The present invention also provides LE driver circuitry 900
to allow an asynchronous clock or other fast signal to be driven
from logic elements 230. FIG. 9 shows a circuit diagram of LE
driver circuitry 900 for driving the asynchronous clock from logic
elements 230. An LE driver output 910 is coupled to either of LE
inputs 832 or 834 of TTL buffer 710. Inverting buffers 918 and 920
are provided to boost the signal and drive LE driver output
910.
[0050] A programmable inversion circuit 930 is also provided to
allow the user to selectively invert the asynchronous clock signal.
When a signal on PIIN input 932 is asserted, the signal on an LE
input 938 is inverted before being driven out on LE driver output
910. Otherwise, the signal is not inverted.
[0051] The foregoing description of preferred embodiments of the
invention has been presented for the purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise form described, and many modifications and
variations are possible in light of the teaching above. The
embodiments were chosen and described in order to best explain the
principles of the invention and its practical applications to
thereby enable others skilled in the art to best utilize the
invention in various embodiments and with various modifications as
are suited to the particular use contemplated. It is intended that
the scope of the invention be defined by the claims appended
hereto.
* * * * *