U.S. patent application number 08/964997 was filed with the patent office on 2001-09-06 for modifying timing graph to avoid given set of paths.
Invention is credited to ANDREEV, ALEXANDER, BOLOTOV, ANATOLI, PAVISIC, IVAN, SCEPANOVIC, RANKO.
Application Number | 20010020289 08/964997 |
Document ID | / |
Family ID | 25509294 |
Filed Date | 2001-09-06 |
United States Patent
Application |
20010020289 |
Kind Code |
A1 |
PAVISIC, IVAN ; et
al. |
September 6, 2001 |
MODIFYING TIMING GRAPH TO AVOID GIVEN SET OF PATHS
Abstract
Integrated circuit chips (IC's) require proper placement of many
cells (groups of circuit components) and complex routing of wires
to connect the pins of the cells. Designing of the IC's require
meeting real-world constraints such as minimization of the circuit
area, minimization of wire length within the circuit, and
minimization of the time the IC requires to perform its function,
referred to as the IC delay. In order to design circuits to meet a
given set of requirements, each signal path of the circuit must be
analyzed. Because of the large number of the cells and the complex
connections, the number of paths is very large and requires much
computing power to analyze. Also, some of the paths are not
important for the purposes of the operations of the chip and can be
discounted during the analysis process. The present invention
discloses a method and apparatus used to avoid analyzing
non-important paths, referred to as false paths of a directed
timing graph. To avoid the false paths, the timing graph
representing the circuit is modified to exclude the false paths
before the graph is analyzed. To modify the timing graph, duplicate
nodes are constructed, duplicate edges are constructed, and some
edges of the original graph are cut and replaced by mixed edges
connecting non-duplicate nodes to duplicate nodes. Finally, mixed
edges are created to connect duplicate nodes to non-duplicate
nodes, integrating the duplicate graph with the original graph.
Inventors: |
PAVISIC, IVAN; (CUPERTINO,
CA) ; ANDREEV, ALEXANDER; (OBLAST, RU) ;
SCEPANOVIC, RANKO; (SAN JOSE, CA) ; BOLOTOV,
ANATOLI; (KVAMOS, RU) |
Correspondence
Address: |
STEVEN E. SHARPIRO
MITCHELL, SILBERBERG & KNUPP
11377 WEST OLYMPIC BLVD
LOS ANGELES
CA
900641683
|
Family ID: |
25509294 |
Appl. No.: |
08/964997 |
Filed: |
November 5, 1997 |
Current U.S.
Class: |
716/113 |
Current CPC
Class: |
G06F 30/3312
20200101 |
Class at
Publication: |
716/1 ; 716/2;
716/3; 716/6 |
International
Class: |
G06F 017/50; G06F
009/45 |
Claims
What is claimed is:
1. A method of modifying timing graph to avoid false paths, said
method comprising the step of modifying the timing graph to include
all the paths except the false paths.
2. A method according to claim 1 further comprising a step of
grouping said false paths into a false path interval.
3. A method according to claim 2 wherein said step of modifying the
graph comprises the steps of: constructing duplicate nodes;
constructing duplicate edges connecting said duplicate nodes;
replacing selected edges of said timing graph by mixed edges; and
adding selected mixed edges to said timing graph.
4. A method according to claim 2 further comprising the steps of:
identifying all the nodes of false paths, V(PI); identifying all
input nodes of said false paths, V.sub.beg(PI); identifying all
output nodes of said false paths, V.sub.fin(PI); and identifying
all intermediate nodes of said false paths, V.sub.int(PI).
5. A method according to claim 1 wherein said step of modifying the
graph comprises the steps of: defining false path interval (PI);
constructing duplicate nodes of non-duplicates nodes belonging to
said false path interval; replacing top level edges of PI with
mixed edges having the same non-duplicate parent nodes and
duplicate child nodes wherein said duplicate child nodes are
duplicates of child nodes of deleted edges; constructing duplicate
edges corresponding to non-duplicate edges; and constructing mixed
edges having a duplicate parent node and a non-duplicate child node
if there exists a non-duplicate corresponding edge.
6. A method according to claim 5 further comprising the step of
determining arrival time of non-duplicate nodes and duplicate
nodes.
7. A method according to claim 1 wherein said timing graph
represents a circuit.
8. A method according to claim 1 further comprising the step of
determining arrival time of said modified graph.
9. A method of modifying timing graphs to avoid false interval, PI,
said method comprising the steps of: a. constructing a duplicate
nodes for each intermediate nodes of the false interval, each of
said duplicate nodes corresponding to a non-duplicate node; b.
deleting all edges of the false interval having a parent node in
V.sub.beg(PI) and a child node in V.sub.int(PI); c. constructing
first mixed edges to replace said deleted edges, said first mixed
edges having the same parent node as said deleted edges but having
a duplicate child node wherein said duplicate child node is a
duplicate of the child node of said deleted edges; d. constructing
duplicate edges connecting said duplicate nodes, each duplicate
edge corresponding to a non-duplicate edge connecting non-duplicate
nodes to which the duplicate nodes of said duplicate edges
correspond; and e. constructing second mixed edges having parent
nodes which are duplicates of nodes belonging to V.sub.int(PI) and
having non-duplicate child nodes, said second mixed edges
corresponding to non-duplicate edges.
10. A method for determining arrival times of pins of an integrated
circuit, said method comprising the steps of: constructing a timing
graph having nodes, representing the pins, and edges; modifying
said timing graph to exclude false paths, said modified graph
having non-duplicate and duplicate nodes; and determining arrival
time of said non-duplicate and duplicate nodes of said modified
timing graph.
11. A method according to claim 10 wherein said step of modifying
said timing graph comprises step of: constructing duplicate nodes;
constructing duplicate edges connecting said duplicate nodes;
replacing selected edges of said timing graph by mixed edges; and
adding selected mixed edges to said timing graph.
12. A method according to claim 10 further comprising the steps of:
identifying all the nodes of false paths, V(PI); identifying all
input nodes of said false paths, V.sub.beg(PI); identifying all
output nodes of said false paths, V.sub.fin(PI); and identifying
all intermediate nodes of said false paths, V.sub.int(PI).
13. A method according to claim 12 further comprising the steps of:
identifying all the edges of said false paths, W(PI); identifying
all beginning edges of said false paths, W.sub.beg(PI); identifying
all finishing edges of said false paths, W.sub.fin(PI); and
identifying all intermediate edges of said false paths,
W.sub.int(PI).
14. An integrated circuit having an IC delay determined in
accordance with the process of claim 1.
15. An integrated circuit having pins wherein arrival times of the
pins are determined by: constructing a timing graph having nodes,
representing the pins; modifying said timing graph to exclude false
paths, said modified graph having non-duplicate and duplicate
nodes; and determining arrival time of said non-duplicate and
duplicate nodes of said modified timing graph.
16. An apparatus for of modifying timing graphs to avoid false
paths, said apparatus comprising: a processor; and a memory
connected to said processor having instructions for said processor
to modify the timing graph to include all the paths except the
false paths.
17. An apparatus for of modifying timing graphs to avoid false
interval, PI, said apparatus comprising: a. means for constructing
a duplicate nodes for each intermediate nodes of the false
interval, each of said duplicate nodes corresponding to a
non-duplicate node; b. means for deleting all edges of the false
interval having a parent node in V.sub.beg(PI) and a child node in
V.sub.int(PI); c. means for constructing first mixed edges to
replace said deleted edges, said first mixed edges having the same
parent node as said deleted edges but having a duplicate child node
wherein said duplicate child node is a duplicate of the child node
of said deleted edges; d. means for constructing duplicate edges
connecting said duplicate nodes, each duplicate edge corresponding
to a non-duplicate edge connecting non-duplicate nodes to which the
duplicate nodes of said duplicate edges correspond; and e. means
for constructing second mixed edges having parent nodes which are
duplicates of nodes belonging to V.sub.int(PI) and having
non-duplicate child nodes, said second mixed edges corresponding to
non-duplicate edges.
18. An apparatus for determining arrival times of pins of an
integrated circuit, said apparatus comprising: means for
constructing a timing graph having nodes, representing the pins,
and edges; means for modifying said timing graph to exclude false
paths, said modified graph having non-duplicate and duplicate
nodes; and means for determining arrival time of said non-duplicate
and duplicate nodes of said modified timing graph.
19. A machine-readable storage medium containing instructions for a
processor, said instructions comprising the steps for the processor
to modify the timing graph to include all the paths except the
false paths.
20. A storage medium according to claim 19 wherein said storage
medium is selected from a group consisting of semiconductor memory
device, magnetic device, optical device, magneto-optical device,
floppy diskette, hard drive, CD-ROM, magnetic tape, computer
memory, and memory card.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to the art of
microelectronic integrated circuits. In particular, the present
invention relates to the art of placing and connecting cells on
integrated circuit chips.
[0003] 2. Description of Related Art
[0004] An integrated circuit chip (hereafter referred to as an "IC"
or a "chip") comprises cells and connections between the cells
formed on a surface of a semiconductor substrate. The IC may
include a large number of cells and require complex connections
between the cells.
[0005] A cell is a group of one or more circuit elements such as
transistors, capacitors, and other basic circuit elements grouped
to perform a function. Each of the cells of an IC may have one or
more pins, each of which, in turn, may be connected to one or more
other pins of the IC by wires. The wires connecting the pins of the
IC are also formed on the surface of the chip. For example, FIG. 1A
shows a grossly simplified IC 10 having four cells 12, 14, 16, and
18 and ten pins 22, 24, 26, 28, 30, 22, 34, 36, 38, and 40. For
simplicity, the cells will be denoted C.sub.nn and the pins will be
denoted p.sub.nn where nn is the reference number of the cell or
the pin used in the figure.
[0006] A net is a set of two or more pins which must be connected.
Because a typical chip has thousands, tens of thousands, or
hundreds of thousands of pins, which must be connected in various
combinations, the chip also includes definitions of thousands, tens
of thousands, or hundreds of thousands of nets, or sets of pins.
The number of the nets for a chip is typically in the same order as
the order of the number of cells on that chip. Commonly, a majority
of the nets include only two pins to be connected; however, many
nets comprise three or more pins. Some nets may include hundreds of
pins to be connected. The IC 10 of FIG. 1A has two nets. The first
net is a two-pin net comprising pins P.sub.34 and p.sub.40. The
second net is a three pin net comprising pins P.sub.32, P.sub.36,
and P.sub.38. A net can be denoted as a set of pins net (P.sub.1,
P.sub.2, . . . P.sub.n).
[0007] A netlist is a list of nets for a chip.
[0008] Typically, an IC has a plurality of input pins and a
plurality of output pins. The inputs are digital electrical signals
being provided to the IC to be operated on. The outputs are digital
electrical signals resulting from the operations of the IC. In
between the input pins receiving the input signals to the IC and
the output pins providing the output signals, the digital signals
are operated on by a plurality of cells connected to each other.
The connections of the cells are defined by the nets discussed
hereinabove. The IC 10 of FIG. 1A has three input pins--P.sub.22,
P.sub.24, and P.sub.26--and two output pins--P.sub.28 and P.sub.30.
For the purposes of describing the present invention, the pins of
the IC which are neither input pins nor output pins will be
referred to as intermediate pins.
[0009] One of the major constraints in design and fabrication of
IC's is the time the IC requires to perform the specified function.
This is often referred to as the performance of the IC. To
determine the performance of an IC, various time measurements must
to be considered. This is because, in addition to the input and
output lines, the IC may include internal registers, or flip-flops,
which may store certain output values and provide a portion of
input values to the logic circuits. The performance of an IC may be
defined as the period of time between the instant the last of the
input signals are available to the logic circuit (whether the
signals are from the input lines or from internal registers) to the
instant the latest of the output signals are available from the
logic circuit (whether the signals are for the output lines or for
internal registers) . The instant the input signal are applied is
often denoted as t.sub.0. In any event, the performance of the IC
is the period of time required for the logic circuits of the IC to
performs its designed function irrespective of whether the inputs
to the logic circuits are from the input pins or from the
flip-flops or the outputs from the logic circuits are to the output
pins or to the flip-flops. The performance of the IC is also
referred to as the delay of the IC, or the IC delay.
[0010] For example, if the inputs to the IC 10 of FIG. 1A is
applied at time t.sub.0 and the last of the output signals of the
IC is available at t.sub.0+3 ns (nano-seconds), then the delay of
the IC 10 is 3 ns. This is true even if the other outputs signals
of the IC are available at t.sub.0+1 ns or at t.sub.0+2 ns.
[0011] The performance of the IC depends on many factors such as
the physical characteristics of the material, the layout of the
cells, etc. Some of these factors, such as the physical
characteristics of the material of the IC, cannot be changed during
the cell placement and routing process. On the other hand, the
placement of the cells and the routing of the nets can be modified
during the placement process to improve the performance of the
IC.
[0012] In order to increase the performance of the IC by modifying
the placement of the cells and re-routing the nets, the paths of
the IC must be analyzed and the critical paths identified. A path
is an alternating sequence of nodes and edges connecting them. A
criticalpath is the path or the paths among all possible paths of
an IC which causes the highest delay of the IC.
[0013] An edge is the direction of signals flow through the cells
and the wires. There are two types of edges in an IC. A cell edge
is the direction of signals flow through the cells of an IC, and is
obtained by "connecting" an input pin of a cell with an output pin
of the same cell. If a cell takes an input signal at pin p.sub.i
and produces and output signal at pin P.sub.0, then the cell edge
for that signal flow is denoted e.sub.c(p.sub.i, P.sub.0) Then,
p.sub.i is called a parent of P.sub.0 and p.sub.0 a child of
p.sub.i. For example, the IC 10 of FIG. 1A has several cell edges.
The cell edges are e.sub.c(P.sub.22, P.sub.32), e.sub.c(P.sub.24,
P.sub.34), e.sub.c(P.sub.26, P.sub.34), e.sub.c(P.sub.36,
P.sub.38), e.sub.c(P.sub.38, P.sub.30), and e.sub.c(P.sub.40,
P.sub.30). A pin may have none (for an input pin), one, or many
parent(s), and none (for an output pin), one, or many children. If
there is a path from node P.sub.1 to node P.sub.2, then P.sub.1 is
an ancestor of P.sub.2 and P.sub.2 is a descendant of P.sub.1.
[0014] A net edge is the direction of signal flow from an output
pin of a cell to an input pin of another cell, and is obtained by
connecting the driverpin of a net with sink pin of the same net. A
driverpin is the pin of a net which provides the signal to the sink
pins of the same net and is typically an output pin of a cell. If a
net has a driver pin P.sub.d which is connected to a sink pin
p.sub.s, then the net edge for that signal flow is denoted
e.sub.n(P.sub.d, p.sub.s). A sink pin is a pin of a net which
receives the signal from a driver pin, and is often an input pin of
a cell. For example, the IC 10 of FIG. 1A has several net edges.
The net edges are e.sub.n(p.sub.32, P.sub.36), e.sub.n(p.sub.32,
P.sub.38), and e.sub.n(p.sub.34, P.sub.40).
[0015] All edges of an IC are directed edges having a driver pin
from which the signal originates and a sink pin to which the signal
flows. For the purposes of the present invention, the distinction
between the cell edges and net edges is not critical. Therefore, an
edge will mean a cell edge or a net edge, and will be denoted
.sub.e(P.sub.p, P.sub.c) to indicate an edge between a parent pin
P.sub.p and a child pin P.sub.c.
[0016] A path may be denoted as a set of pins and edges, for
example, path(p.sub.1, e(p.sub.1, P.sub.2), P.sub.2, e(p.sub.2,
P.sub.3), P.sub.3, . . . ) An alterative expression of the path is
to merely list the nodes, for example, path(p.sub.1, P.sub.2, . . .
). Regardless of how it is denoted, a path comprises pins and edges
connecting the pins.
[0017] The relationships of ancestor and descendent may exist
between an edge and a node or between two edges. For example, if
p.sub.1 is an ancestor of P.sub.2, then P.sub.1 is also an ancestor
of the edge e(p.sub.2, p.sub.3). Similarly, if p.sub.7 is a
descendent of p.sub.4, then e(p.sub.7, P.sub.8) is a descendent of
p.sub.4.
[0018] FIG. 1B illustrates a directed graph constructed from the
pins and the edges of the IC 10 of FIG. 1A. Each node of the graph
50 correspond to a pin of the IC 10 of FIG. 1, and each edge of the
graph 50 correspond to an edge of the same IC 10. In FIG. 1B, the
edges are directed. That is, each of the edges is indicated by an
arrow to show the direction of the signal flow. In the present
specification, the terms pins and the nodes will be used
interchangeably unless otherwise specified.
[0019] Because each of the edges of the directed graph 50 of FIG.
1B represents a signal travel through a cell or through a wire,
each of the edges can be assigned an edge delay to indicate the
time required for a signal to travel from the parent pin to the
child pin. Then, the directed graph is referred to as a directed
timing graph or merely a timing graph. The delay of e(p.sub.1,
P.sub.2) is denoted delay(p.sub.1, P.sub.2). It takes time for
electrical signal to travel from pin to pin; thus, every edge has a
delay.
[0020] The paths of the timing graph of an IC can be analyzed to
locate the critical paths.
[0021] The timing characteristics of the cell edges can be obtained
from libraries. However, the timing characteristics of net edges
are not easily obtainable before the actual routing of the
nets.
[0022] The period of time required for signals to travel from an
input pin to pin p may be called the arrival time of pin p. The
arrival time of node p, denoted arrival(p), is the latest time a
signal from an input mode reaches node though any available path
from an input node to the node. Formally, arrival(p) is 1 arrival (
p ) = max i = 1 - k ( arrival ( p i ) + delay ( p i , p ) )
[0023] where k is the number of parents of p; and
[0024] p is a child of p.sub.i;
[0025] P.sub.i is a parent of p; and
[0026] arrival(p)=0 if p is an input node.
[0027] To determine the performance, or the delay, of an IC, each
of the paths of the IC must be analyzed. The IC delay may be
expressed as the largest arrival time of any of the output nodes,
or 2 IC delay = max j = 1 - m ( arrival ( p j ) )
[0028] where m is the number of output pins of the IC;
[0029] P.sub.j is an output pin.
[0030] As discussed above, the IC delay is the period of time
signals take to travel from an input pin to an output pin.
Accordingly, it is not possible to determine the IC delay at an
output pin without first determining the delay from the input pins
to each of the intermediate pins the signal travels through to
arrive at the output pin. In fact, for any pin not an input pin,
arrival(p) cannot be determined unless the arrival(p) of all of its
ancestors are first found.
[0031] For example, referring to FIG. 2, the IC delay of the chip
represented by the timing graph 70 cannot be determined unless
arrival(P.sub.90) and arrival(p.sub.92) are found. However,
arrival(p.sub.92) cannot be found until arrival(p.sub.86) is first
determined. Likewise, arrival(p.sub.86) cannot be found until
arrival(p.sub.82) and arrival(.sub.80) are found, and so on.
[0032] To find the delay of an IC, the arrival time of each of the
pins of the IC must be determined. Because a typical IC contains
many thousands or even millions of pins and paths, the analysis of
arrival times for each of the pins are computationally expensive.
Accordingly, the IC delay analysis of large IC circuits requires a
large amount of time even when utilizing very powerful
computers.
[0033] Additionally, IC's usually contain paths the delay of which
should not be considered in the determination of the IC delay.
These paths are called false paths. For example, self-test circuits
of the IC may cause high IC delay. However, the self-test circuits
are not used during the ultimate use of the IC, and the IC delay,
as defined by the self-test, would be misleading. For instance, if
the self-test circuits causes the IC to have the IC delay of 20 ns
where the other, more relevant portions of the IC has the delay of
5 ns, then the IC delay of 20 ns is misleading.
[0034] In short, to determine the delay of an IC, only the true
paths of the IC should be considered. Calculation of the arrival
times and the delays of the false paths wastes the processing time
and provides misleading results for the IC.
SUMMARY OF THE INVENTION
[0035] Therefore, an object of the present invention is to provide
for a method and apparatus to ignore the false paths of an IC for
the purposes of analyzing IC timing graphs and determining IC
delays.
[0036] The present invention provides for a method of modifying
timing graph to avoid false paths, by modifying the timing graph to
include all the paths except the false paths. The timing graph is
modified by constructing duplicate nodes, duplicate edges, and
mixed edges, and by replacing selected non-duplicate edges by mixed
edges.
[0037] The present invention also provides for an integrated
circuit for which the arrival time of its pins were determined by
constructing a timing graph, modifying the timing graph to exclude
false paths, and determining the arrival time of the non- duplicate
and duplicate nodes of the modified timing graph.
[0038] The present invention also provides for an apparatus for of
modifying timing graphs to avoid false paths. The apparatus has a
processor and memory connected to the processor. The memory stores
instructions for the processor to modify the timing graph to
include all the paths except the false paths.
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] FIG. 1A is a simplified illustration of an integrated
circuit chip;
[0040] FIG. 1B is a timing graph derived from the integrated
circuit chip of FIG. 1A;
[0041] FIG. 2 is a sample directed timing graph;
[0042] FIG. 3 is the sample directed timing graph of FIG. 2 after
it has been modified in accordance with the technique of the
present invention; and
[0043] FIG. 4 is a block diagram illustrating an apparatus
according to a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0044] Directed timing graph may be used to facilitate the analysis
of the paths of an IC. The timing graph used in delay calculations
is constructed from the netlist. Therefore, a timing graph must
first be constructed from a given IC design in order for the
circuit to be analyzed.
[0045] Referring to FIG. 2, a sample timing graph 70 is
illustrated. The timing graph 70 has input pins 72, 74, 76, and 78,
output pins 90 and 92, and pins 80, 82, 84, and 86. For simplicity,
the pins will be denoted P.sub.nn where nn is the reference number
of the pin used in the figure. The graph 70 also has the following
edges e(p.sub.72, P.sub.84), e(P.sub.74, P.sub.82), e(P.sub.76,
P.sub.80), e(P.sub.78, P.sub.80), e(P.sub.80, P.sub.82),
e(p.sub.80, P.sub.86), e(P.sub.82, P.sub.84), e(P.sub.82,
P.sub.86), e(P.sub.84, P.sub.90), e(P.sub.86, P.sub.90), and
e(P.sub.86, P.sub.92). In the present specification, the terms pins
and the nodes will be used interchangeably unless otherwise
specified.
[0046] For the purposes of the discussion, the following sample
delay values are assigned to the edges of the graph 70 of FIG.
2:
1 TABLE 1 Edges Edge Delay (in nano seconds) e(p.sub.76, p.sub.80),
e(p.sub.80, p.sub.82) 1.0 e(p.sub.78, p.sub.80) 0.8 e(p.sub.74,
p.sub.82), e(p.sub.84, p.sub.90) 1.2 e(p.sub.72, p.sub.84),
e(p.sub.76, p.sub.82) 1.4 e(p.sub.80, p.sub.86) 3.2 e(p.sub.82,
p.sub.84) 1.8 e(p.sub.82, p.sub.86) 1.5 e(p.sub.86, p.sub.90) 2.6
e(p.sub.86, p.sub.92) 1.7
[0047] The arrival(p) is determined by analyzing each of the nodes
of the graph. The resultant arrival times of the sample graph 70 is
summarized by Table 2 below:
2 TABLE 2 Node Arrival time (0 = t.sub.0, in ns) p.sub.72,
p.sub.74, p.sub.76, p.sub.78 0 p.sub.80 1.0 p.sub.82 2.0 via
path(p.sub.76, p.sub.80, p.sub.82) p.sub.84 3.8 via path(p.sub.76,
p.sub.80, p.sub.82, p.sub.84) p.sub.86 4.2 via path(p.sub.76,
p.sub.80, p.sub.86) p.sub.90 6.8 via path(p.sub.76, p.sub.80,
p.sub.86, p.sub.90) p.sub.92 5.9 via path(p.sub.76, p.sub.80,
p.sub.86, p9.sub.2)
[0048] Because nodes P.sub.90 and P.sub.92 are the output nodes,
the IC delay is the larger of the two which is 6.8 ns of pgo. This
value may be denoted D. The critical paths are the paths leading to
the highest arrival time at an output node. In the present example,
the critical path is path(p.sub.76, P.sub.80, P.sub.86, P.sub.90)
requiring 6.8 ns for signal to traverse the path.
[0049] However, if path(P.sub.76, P.sub.80, P.sub.86, P.sub.90) is
a false path, then the IC delay of 6.8 ns is misleading because
that path should not be used in determining the IC delay. Also, the
calculation of path(P.sub.76, P.sub.80, P.sub.86, P.sub.90)
required computational resources.
[0050] To preclude the use of a false path delay as an IC delay,
and to avoid the arrival time calculation of the false paths, the
following technique may be used:
[0051] Identify the False Path Intervals
[0052] Very often, the false paths form groups that can be
expressed as "all the paths starting in the set of nodes N.sub.1,
then going through the set of edges E.sub.1, then through the set
of nodes N.sub.2," and so on. Such groups of paths can be called a
path interval. Thus, a path interval is an alternating sequence of
sets of nodes and sets of edges such that every element from
N.sub.1 is an ancestor of every element from any other sets of
nodes or edges of the path interval. A path interval may comprise
one or more paths to be ignored for the purposes of arrival time
and IC delay determinations. Because all edges have a parent and a
child node, a path interval always begins and ends with a set of
nodes.
[0053] The arrival time of the nodes of the false paths can be
easily ignored by grouping the false paths into path intervals. A
path interval is denoted PI.
[0054] First, the false path interval must be clearly defined by
determining the beginning nodes, finishing nodes, and the
intermediate nodes of the false path interval. Assuming that the
false path interval is defined as
[0055] PI={N.sub.1, E.sub.1, N.sub.2, E.sub.2, . . . , E.sub.n-1,
N.sub.n}
[0056] where
[0057] N.sub.1 is a set of beginning nodes, not necessarily the
input nodes;
[0058] E.sub.1 is a set of edges, each edge having a parent node
belonging to N.sub.1 and a child node belonging to N.sub.2;
[0059] N.sub.2 is a set of nodes, each node being a child node of
an edge belonging to E.sub.1; and so on until
[0060] N.sub.n is a set of finishing nodes, each node being a child
node of an edge belonging to E.sub.n-1; the nodes of N.sub.n are
not necessarily the output nodes.
[0061] Then, define
[0062] V(PI)=set of all nodes of the path interval PI
[0063] V.sub.beg(PI)=N.sub.1, set of all nodes comprising the top
level nodes, or input nodes, of PI. These are not necessarily the
input nodes of the timing graph;
[0064] V.sub.fin(PI)=N.sub.n, set of all nodes comprising the
bottom level nodes, or output nodes of PI; These are not
necessarily the output nodes of the timing graph; and
[0065] V.sub.int(PI)=V(PI)-(V.sub.beg(PI).orgate.V.sub.fin(PI)),
all other nodes of PI.
[0066] And define
[0067] W(PI)=set of all edges of the path interval PI;
[0068] W.sub.beg(PI) set of edges having a parent node belonging in
V.sub.beg(PI);
[0069] W.sub.fin(PI)=set of edges having a child node belonging in
V.sub.fin(PI); and
[0070] w.sub.int(PI)=W(PI)-(W.sub.beg(PI).orgate.W.sub.fin(PI)),
all other edges of PI.
[0071] Referring again to FIG. 2, these definitions can be
illustrated using the directed timing graph 70. Assuming that the
path(P.sub.76, P.sub.80, P.sub.86, P.sub.90) is a false path, a
false path interval, PI, is defined as comprising a single false
path, path(p.sub.76, P.sub.80, P.sub.86, P.sub.90), then,
[0072] V(PI)={P.sub.76, P.sub.80, P.sub.86, P.sub.90}
[0073] V.sub.beg(PI)={P.sub.76}
[0074] V.sub.fin(PI)={P.sub.80}
[0075] V.sub.int(PI)={P.sub.80, P.sub.86}
[0076] W(PI)={e(P.sub.76, P.sub.80), e(P.sub.80, P.sub.86),
e(P.sub.86, P.sub.90)}
[0077] W.sub.beg(PI)={e(P.sub.76, P.sub.80)}
[0078] W.sub.fin(PI)={e(P.sub.86, P.sub.90)}
[0079] W.sub.int(PI)={e(P.sub.80, P.sub.86)}
[0080] Modify the Graph
[0081] To modify the timing graph to preclude the analysis of the
false paths grouped in a false path interval PI, the following
operation are applied to the graph:
[0082] Step 1. For each node in V.sub.int(PI), a duplicate node,
denoted P'.sub.nn, is constructed. As discussed above, a pin, or a
node, is denoted pnn where nn is the reference number used in the
figure to identify the node. For simplicity, the duplicate pin if
p.sub.nn will be denoted p'.sub.nn where nn' is the reference
number used in the figure to identify the duplicate pin. Pin
p'.sub.nn is the duplicate of non-duplicate pin p.sub.nn.
[0083] For uniformity of terminology, the nodes of the original
graph 70 of FIG. 2 will be referred to as non-duplicate nodes or
non-duplicate pins. Similarly, edges connecting non-duplicate nodes
will be referred to as non-duplicate edges. Edges connecting
duplicate nodes will be referred to as duplicate edges. Edges
connecting a duplicate pin and a non-duplicate pin will be referred
to as a mixed edge. A duplicate node corresponds to the
non-duplicate node to which it is the duplicate of. For instance,
node P'.sub.80 corresponds to node P.sub.80. Similarly, a duplicate
edge or a mixed edge corresponds to the non-duplicate edge if the
node or the nodes defining the duplicate or mixed edge corresponds
to the node or nodes of the non-duplicate edge. For example,
e(p'.sub.80, P'.sub.86) corresponds to e(p.sub.80, P.sub.86), and
e(p'.sub.86, P.sub.92) corresponds to e(p.sub.86, P.sub.92). The
sets of duplicate nodes, duplicate edges, and mixed edges comprise
a duplicate graph. Note that a duplicate graph does not completely
copy the original timing graph, but copies only a portion of the
original timing graph.
[0084] Step 2. For every edge e(p.sub.i, p.sub.j) in W.sub.beg(PI),
if the child node, p.sub.j, is a member of V.sub.int(PI), then the
edge e(p.sub.i, p.sub.j) is deleted and a new edge e(p.sub.i,
p'.sub.j) is constructed. Node p'.sub.j exists for the edge because
it was constructed during Step 1. Note that pi is a member of
V.sub.beg(PI). The edges of W.sub.beg(PI) is also referred to as
the top level edges of PI.
[0085] Step 3. For every edge e(p.sub.m, P.sub.n) in W.sub.int(PI),
a duplicated edge e(p'.sub.m, P'.sub.n) is constructed.
[0086] Step 4. For every edge e(p.sub.j, P.sub.k), if the parent
node, pj, is a member of V.sub.int(PI) and the child node, pk, is
not a member of V(PI), then a new edge e(p'.sub.j, P.sub.k) is
added.
[0087] The modification of the graph is now complete, and the new,
modified timing graph may be used to calculate the arrival time of
the pins and the IC delay of the circuit. The edge delay between a
non-duplicate pin and a duplicate pin is same as the edge delay
between the non-duplicate pin and the non-duplicate pin to which
the child pin is the duplicate of. More formally,
[0088] delay(p.sub.i, p.sub.j)=delay(p.sub.i, p'.sub.j) where
P'.sub.j is a duplicate of p.sub.j.
[0089] Also,
[0090] delay(p.sub.i, p.sub.j)=delay(p'.sub.i, p.sub.j); and
[0091] delay(p.sub.i, p.sub.j)=delay(p'.sub.i, p'.sub.j).
[0092] To calculate the IC delay of the circuit represented by the
modified timing graph, all the nodes, including the non-duplicate
and the duplicate nodes, must be analyzed for the arrival
times.
[0093] FIG. 2 shows the timing graph 70 which has a false path
path(p.sub.76, P.sub.80, P.sub.86, P.sub.90). As analyzed above,
the false path, if not ignored, defines the IC delay of the circuit
represented by the graph 70 because the false path includes an
output pin with the highest arrival time. In this example, there is
only one false path, so the false path interval, PI is a one member
set comprising path(p.sub.76, P.sub.80, P.sub.86, P.sub.90).
[0094] FIG. 3 shows a timing graph 70' which is the timing graph 70
of FIG. 2 after it has been modified in accordance with the steps
outlined above. Note that in the modified graph 70', the false path
path(p.sub.76, P.sub.80, P.sub.86, P.sub.90) does not exist, but
all other paths exists.
[0095] Beginning with the graph 70 of FIG. 2, Step 1 is applied to
the graph 70 by constructing duplicate pins P'.sub.80 and P'.sub.86
because P.sub.80 and P.sub.86 are members of V.sub.int(PI).
[0096] Step 2 requires the deletion of e(P.sub.76, P.sub.80) and
addition of e(P.sub.76, P'.sub.80). Note that e(P.sub.76, P.sub.80)
is a member of W.sub.beg(PI), and P.sub.80 is a member of
V.sub.int(PI).
[0097] In the present example, the set W.sub.int(PI) comprises only
one edge e(p.sub.80, P.sub.86). Thus, in accordance with Step 3, a
duplicate edge, e(p'.sub.80, P'.sub.86) is constructed.
[0098] Finally, the application of Step 4 requires the addition of
edges e(p'80, P.sub.82) and e(p'.sub.86, P.sub.92). Note that for
each of the edges e(P.sub.80, P.sub.82) and e(p.sub.86, p.sub.90),
the parent nodes were members of V.sub.int(PI), and the child nodes
were not members of V(PI).
[0099] The resultant directed timing graph 70' of FIG. 3 has all
the nodes and the edges of the initial graph 70 except the false
paths as defined by the false path interval PI.
[0100] Because the edge delay between a non-duplicate pin and a
duplicate pin, and the edge delay between duplicate pins are same
as the edge delay between the corresponding non-duplicate pins, the
delays of the edges of the new timing graph can be summarized as
listed by Table 3 below.
3TABLE 3 Edges Edge Delay (in nano seconds) e(p.sub.76, p'.sub.80),
e(p.sub.80, p.sub.82), e(p'.sub.80, p.sub.82) 1.0 e(p.sub.78,
p.sub.80) 0.8 e(p.sub.74, p.sub.82), e(p.sub.84, p.sub.90) 1.2
e(p.sub.72, p.sub.84), e(p.sub.76, p.sub.82) 1.4 e(p.sub.80,
p.sub.86), e(p'.sub.80, p'.sub.86) 3.2 e(p.sub.82, p.sub.84) 1.8
e(p.sub.82, p.sub.86) 1.5 e(p.sub.86, p.sub.90) 2.6 e(p.sub.86,
p.sub.92), e(p'.sub.86, p.sub.92) 1.7
[0101] The modified graph 70' no longer contains the false path
path(p.sub.76, P.sub.80, P.sub.86, P.sub.90). However, the graph
70' includes paths traversing duplicate nodes and duplicated edges.
The arrival(p) for the nodes of the new graph 70' is summarized by
Table 4 below:
4 TABLE 4 Node Arrival time (0 = t.sub.0, in ns) p.sub.72, .sub.74,
p.sub.76, p.sub.78 0, input nodes p.sub.80 0.8 p'.sub.80 1.0
p.sub.82 2.0 via path(p.sub.76, p'.sub.80, p.sub.82) p.sub.84 3.8
via path(p.sub.76, p'.sub.80, p.sub.82, p.sub.84) p.sub.86 4.0 via
path(p.sub.78, p.sub.80, p.sub.86) p'.sub.86 4.2 via path(p.sub.76,
p'.sub.80, p'.sub.86) p.sub.90 6.6 via path(p.sub.78, p.sub.80,
p.sub.86, p.sub.90) p.sub.92 5.9 via path(p.sub.76, p'.sub.80,
p'.sub.86, p.sub.92)
[0102] Note that the new IC delay value for the circuit represented
by the graph 70' is 6.6 ns via path path(p.sub.78, P.sub.80,
P.sub.86, P.sub.90). One could have expected the IC delay of the
circuit, after the removal of the false path, to be 5.9 ns via
path(p.sub.76, P.sub.80, P.sub.86, P.sub.92). Such expectation is
based on the fact that path(p.sub.76, P.sub.80, P.sub.86, P.sub.92)
was the path with the second longest delay according to the
original graph 70. See FIG. 2 and Table 2. However, the removal of
the false path allowed a true path with a delay higher than 5.9 ns
to be detected. This true path, path(p.sub.78, P.sub.80, P.sub.86,
P.sub.90), was "hidden" by the false path until the false path was
removed. Therefore, another advantage of the present invention is
that, by removing false paths, the true paths are uncovered for a
better analysis of the circuit.
[0103] Apparatus for Modifying Timing Graphs to Avoid False
Paths
[0104] Now referring to FIG. 5, a computing apparatus 100 for
modifying timing graphs to avoid false paths is illustrated. The
apparatus comprises a processor 102 and memory 104. connected to
the processor. The memory 104 stores instructions for the processor
102 for the processor 102 to modify the timing graph to include all
the paths except the false paths.
[0105] The memory 104 may be any kind of machine-readable storage
medium containing the instructions for the processor to read input
information 106, modify the timing graph, and produce an output
108. For the present invention, the input 106 may comprise the
original timing graph, in which case, the memory 104 comprises
instructions for the processor 102 to modify the timing graph and
to produce, as the output 108, the modified timing graph. If the
input 106 is a circuit design, the memory 104 comprises
instructions for the processor 102 to construct a timing graph,
modify the timing graph, and determine the arrival times of the
pins of the circuit to produce, as the output 108, the arrival
times of the pins of the circuit. It is well known in the art that
the memory may be formed as a semiconductor memory device, magnetic
device, optical device, magneto-optical device, floppy diskette,
hard drive, CD-ROM, magnetic tape, computer memory, or memory
card.
[0106] Although the present invention has been described in detail
with regarding the exemplary embodiments and drawings thereof, it
should be apparent to those skilled in the art that various
adaptations and modifications of the present invention may be
accomplished without departing from the spirit and the scope of the
invention. Accordingly, the invention is not limited to the precise
embodiment shown in the drawings and described in detail
hereinabove. Therefore, it is intended that all such variations not
departing from the spirit of the invention be considered as within
the scope thereof as limited solely by the claims appended
hereto.
[0107] In the following claims, those elements which do not include
the words "means for" are intended not to be interpreted under 35
U.S.C..sctn.112 .paragraph.6.
* * * * *