Pavisic; Ivan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pavisic; Ivan.The latest application filed is for "architectural floorplan for a structured asic manufactured on a 28 nm cmos process lithographic node or smaller".

Company Profile

0.46.26

Pavisic; Ivan - San Jose CA
Pavisic; Ivan - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller Grant 9,024,657 - Andreev , et al. May 5, 2	2015-05-05
Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller App 20140103959 - Andreev; Alexander ; et al.	2014-04-17
Method and computer program for generating grounded shielding wires for signal wiring Grant 8,516,425 - Nikitin , et al. August 20, 2	2013-08-20
Signal Delay Skew Reduction System App 20120278783 - Nikitin; Andrey ; et al.	2012-11-01
Method and apparatus for balancing signal delay skew Grant 8,239,813 - Nikitin , et al. August 7, 2	2012-08-07
Signal Delay Skew Reduction System App 20110258587 - Nikitin; Andrey ; et al.	2011-10-20
Signal delay skew reduction system Grant 7,996,804 - Nikitin , et al. August 9, 2	2011-08-09
Density driven layout for RRAM configuration module Grant 7,818,703 - Andreev , et al. October 19, 2	2010-10-19
Methods and apparatus for fast unbalanced pipeline architecture Grant 7,667,494 - Andreev , et al. February 23, 2	2010-02-23
Methods And Apparatus For Fast Unbalanced Pipeline Architecture App 20090243657 - Andreev; Alexander ; et al.	2009-10-01
Signal Delay Skew Reduction System App 20090187873 - Nikitin; Andrey ; et al.	2009-07-23
Built in self test transport controller architecture Grant 7,546,505 - Gribok , et al. June 9, 2	2009-06-09
Built in self test transport controller architecture App 20080109688 - Gribok; Sergey ; et al.	2008-05-08
Optimizing IC clock structures by minimizing clock uncertainty Grant 7,356,785 - Lu , et al. April 8, 2	2008-04-08
System for avoiding false path pessimism in estimating net delay for an integrated circuit design Grant 7,334,204 - Guo , et al. February 19, 2	2008-02-19
Density Driven Layout For Rram Configuration Module App 20080016482 - Andreev; Alexander ; et al.	2008-01-17
Density driven layout for RRAM configuration module Grant 7,246,337 - Andreev , et al. July 17, 2	2007-07-17
Method of buffer insertion to achieve pin specific delays Grant 7,243,324 - Lu , et al. July 10, 2	2007-07-10
System for avoiding false path pessimism in estimating net delay for an integrated circuit design App 20070157143 - Guo; Weiqing ; et al.	2007-07-05
Memory tiling architecture Grant 7,207,026 - Andreev , et al. April 17, 2	2007-04-17
Compact custom layout for RRAM column controller Grant 7,194,717 - Andreev , et al. March 20, 2	2007-03-20
Optimizing IC clock structures by minimizing clock uncertainty App 20060190886 - Lu; Aiguo ; et al.	2006-08-24
Method of buffer insertion to achieve pin specific delays App 20060190901 - Lu; Aiguo ; et al.	2006-08-24
Optimizing IC clock structures by minimizing clock uncertainty Grant 7,096,442 - Lu , et al. August 22, 2	2006-08-22
Method and system for classifying an integrated circuit for optical proximity correction Grant 7,093,228 - Andreev , et al. August 15, 2	2006-08-15
Density driven layout for RRAM configuration module App 20060123373 - Andreev; Alexander ; et al.	2006-06-08
Memory tiling architecture App 20060104145 - Andreev; Alexandre ; et al.	2006-05-18
Compact custom layout for RRAM column controller App 20060085777 - Andreev; Alexander E. ; et al.	2006-04-20
RRAM backend flow Grant 7,028,274 - Andreev , et al. April 11, 2	2006-04-11
Clock tree synthesis with skew for memory devices Grant 6,941,533 - Andreev , et al. September 6, 2	2005-09-06
Timing-driven placement method utilizing novel interconnect delay model Grant 6,901,571 - Petranovic , et al. May 31, 2	2005-05-31
Optimizing IC clock structures by minimizing clock uncertainty App 20050010884 - Lu, Aiguo ; et al.	2005-01-13
Process of restructuring logics in ICs for setup and hold time optimization Grant 6,810,515 - Lu , et al. October 26, 2	2004-10-26
Process for layout of memory matrices in integrated circuits Grant 6,804,811 - Andreev , et al. October 12, 2	2004-10-12
Process layout of buffer modules in integrated circuits Grant 6,760,896 - Andreev , et al. July 6, 2	2004-07-06
System and method for identifying and eliminating bottlenecks in integrated circuit designs Grant 6,757,877 - Stenberg , et al. June 29, 2	2004-06-29
Power routing with obstacles Grant 6,757,881 - Andreev , et al. June 29, 2	2004-06-29
Method and system for classifying an integrated circut for optical proximity correction App 20040123265 - Andreev, Alexandre ; et al.	2004-06-24
Clock tree synthesis with skew for memory devices App 20040078766 - Andreev, Alexander E. ; et al.	2004-04-22
Process layout of buffer modules in integrated circuits App 20040060027 - Andreev, Alexander E. ; et al.	2004-03-25
Process of restructuring logics in ICs for setup and hold time optimization App 20040060012 - Lu, Aiguo ; et al.	2004-03-25
Process For Layout Of Memory Matrices In Integrated Circuits App 20040060029 - Andreev, Alexander E. ; et al.	2004-03-25
Floor plan tester for integrated circuit design Grant 6,701,493 - Gasanov , et al. March 2, 2	2004-03-02
Assignment of cell coordinates Grant 6,637,016 - Gasanov , et al. October 21, 2	2003-10-21
Floor plan tester for integrated circuit design App 20030188274 - Gasanov, Elyar E. ; et al.	2003-10-02
Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells Grant 6,629,304 - Gasanov , et al. September 30, 2	2003-09-30
Optimal clock timing schedule for an integrated circuit Grant 6,615,397 - Andreev , et al. September 2, 2	2003-09-02
System and method for identifying and eliminating bottlenecks in integrated circuit designs App 20030163797 - Stenberg, Robert ; et al.	2003-08-28
Power routing with obstacles App 20030145302 - Andreev, Alexandre E. ; et al.	2003-07-31
Netlist resynthesis program based on physical delay calculation Grant 6,557,144 - Lu , et al. April 29, 2	2003-04-29
Timing recomputation Grant 6,553,551 - Zolotykh , et al. April 22, 2	2003-04-22
Method in integrating clock tree synthesis and timing optimization for an integrated circuit design Grant 6,550,044 - Pavisic , et al. April 15, 2	2003-04-15
Changing clock delays in an integrated circuit for skew optimization Grant 6,550,045 - Lu , et al. April 15, 2	2003-04-15
Netlist resynthesis program using structure co-factoring Grant 6,546,539 - Lu , et al. April 8, 2	2003-04-08
Parallelization Of Resynthesis App 20020162085 - Zolotykh, Andrej A. ; et al.	2002-10-31
Parallelization of resynthesis Grant 6,470,487 - Zolotykh , et al. October 22, 2	2002-10-22
Optimal clock timing schedule for an integrated circuit App 20020091983 - Andreev, Alexander E. ; et al.	2002-07-11
Wire routing optimization Grant 6,412,102 - Andreev , et al. June 25, 2	2002-06-25
Advanced modular cell placement system Grant 6,292,929 - Scepanovic , et al. September 18, 2	2001-09-18
Modifying Timing Graph To Avoid Given Set Of Paths App 20010020289 - PAVISIC, IVAN ; et al.	2001-09-06
Method and apparatus for parallel routing locking mechanism Grant 6,269,469 - Pavisic , et al. July 31, 2	2001-07-31
Advanced Modular Cell Placement System App 20010003843 - SCEPANOVIC, RANKO ; et al.	2001-06-14
Method and apparatus for determining wire routing Grant 6,186,676 - Andreev , et al. February 13, 2	2001-02-13
Metal layer assignment Grant 6,182,272 - Andreev , et al. January 30, 2	2001-01-30
Method and apparatus for horizontal congestion removal Grant 6,123,736 - Pavisic , et al. September 26, 2	2000-09-26
Method and apparatus for continuous column density optimization Grant 6,075,933 - Pavisic , et al. June 13, 2	2000-06-13
Method and apparatus for congestion removal Grant 6,068,662 - Scepanovic , et al. May 30, 2	2000-05-30
Method and apparatus for congestion driven placement Grant 6,070,108 - Andreev , et al. May 30, 2	2000-05-30
Advanced modular cell placement system Grant 6,067,409 - Scepanovic , et al. May 23, 2	2000-05-23
Method and apparatus for vertical congestion removal Grant 6,058,254 - Scepanovic , et al. May 2, 2	2000-05-02
Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization Grant 5,796,625 - Scepanovic , et al. August 18, 1	1998-08-18