SCEPANOVIC; Ranko

Patent Applications and Registrations

Patent applications and USPTO patent grants for SCEPANOVIC; Ranko.The latest application filed is for "structured integrated circuit device with multiple configurable via layers".

Company Profile

0.131.53

SCEPANOVIC; Ranko - Saratoga CA
Scepanovic; Ranko - San Jose CA US
Scepanovic; Ranko - Saratogo CA
Scepanovic; Ranko - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structured Integrated Circuit Device With Multiple Configurable Via Layers App 20160293541 - ANDREEV; Alexander ; et al.	2016-10-06
Data shredding RAID mode Grant 8,806,227 - Grinchuk , et al. August 12, 2	2014-08-12
Via-configurable high-performance logic block architecture Grant 8,735,857 - Andreev , et al. May 27, 2	2014-05-27
Method and apparatus for generating memory models and timing database Grant 8,566,769 - Andreev , et al. October 22, 2	2013-10-22
Method and computer program for generating grounded shielding wires for signal wiring Grant 8,516,425 - Nikitin , et al. August 20, 2	2013-08-20
Signal Delay Skew Reduction System App 20120278783 - Nikitin; Andrey ; et al.	2012-11-01
Method and Apparatus for Generating Memory Models and Timing Database App 20120278775 - Andreev; Alexandre ; et al.	2012-11-01
Method and apparatus for generating memory models and timing database Grant 8,245,168 - Andreev , et al. August 14, 2	2012-08-14
Method and apparatus for balancing signal delay skew Grant 8,239,813 - Nikitin , et al. August 7, 2	2012-08-07
Via-Configurable High-Performance Logic Block Architecture App 20120161093 - Andreev; Alexander ; et al.	2012-06-28
Memory mapping for parallel turbo decoding Grant 8,132,075 - Andreev , et al. March 6, 2	2012-03-06
Signal Delay Skew Reduction System App 20110258587 - Nikitin; Andrey ; et al.	2011-10-20
Method and apparatus for mapping design memories to integrated circuit layout Grant 8,037,432 - Andreev , et al. October 11, 2	2011-10-11
Methods and apparatus for programmable decoding of a plurality of code types Grant 8,035,537 - Andreev , et al. October 11, 2	2011-10-11
Method and system for outputting a sequence of commands and data described by a flowchart Grant 8,006,209 - Nikitin , et al. August 23, 2	2011-08-23
Signal delay skew reduction system Grant 7,996,804 - Nikitin , et al. August 9, 2	2011-08-09
Decision tree representation of a function Grant 7,877,724 - Andreev , et al. January 25, 2	2011-01-25
Command language for memory testing Grant 7,856,577 - Andreev , et al. December 21, 2	2010-12-21
Generation of test sequences during memory built-in self testing of multiple memories Grant 7,788,563 - Andreev , et al. August 31, 2	2010-08-31
Pipelined LDPC arithmetic unit Grant 7,739,575 - Andreev , et al. June 15, 2	2010-06-15
High performance tiling for RRAM memory Grant 7,739,471 - Andreev , et al. June 15, 2	2010-06-15
Method and Apparatus for Generating Memory Models and Timing Database App 20100023904 - Andreev; Alexandre ; et al.	2010-01-28
Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories App 20090316507 - Andreev; Alexandre E. ; et al.	2009-12-24
Methods And Apparatus For Programmable Decoding Of A Plurality Of Code Types App 20090309770 - Andreev; Alexander ; et al.	2009-12-17
Decision Tree Representation of a Function App 20090281969 - Andreev; Alexander ; et al.	2009-11-12
Method and apparatus for generating memory models and timing database Grant 7,584,442 - Andreev , et al. September 1, 2	2009-09-01
Signal Delay Skew Reduction System App 20090187873 - Nikitin; Andrey ; et al.	2009-07-23
Command Language For Memory Testing App 20090133003 - Andreev; Alexander E. ; et al.	2009-05-21
Method and system for outputting a sequence of commands and data described by a flowchart App 20090094571 - Nikitin; Andrey A. ; et al.	2009-04-09
Multimode delay analysis for simplifying integrated circuit design timing models Grant 7,512,918 - Andreev , et al. March 31, 2	2009-03-31
Method and system for outputting a sequence of commands and data described by a flowchart Grant 7,472,358 - Nikitin , et al. December 30, 2	2008-12-30
Method And Apparatus For Mapping Design Memories To Integrated Circuit Layout App 20080295044 - Andreev; Alexandre ; et al.	2008-11-27
Method and apparatus for mapping design memories to integrated circuit layout Grant 7,424,687 - Andreev , et al. September 9, 2	2008-09-09
Method and system for outputting a sequence of commands and data described by a flowchart Grant 7,415,691 - Andreev , et al. August 19, 2	2008-08-19
Memory timing model with back-annotating Grant 7,415,686 - Andreev , et al. August 19, 2	2008-08-19
Pipelined Ldpc Arithmetic Unit App 20080178057 - Andreev; Alexander ; et al.	2008-07-24
Method and apparatus for tiling memories in integrated circuit layout Grant 7,389,484 - Andreev , et al. June 17, 2	2008-06-17
Method and system for analyzing the quality of an OPC mask Grant 7,340,706 - Golubtsov , et al. March 4, 2	2008-03-04
Memory Mapping For Parallel Turbo Decoding App 20080049719 - Andreev; Alexander E. ; et al.	2008-02-28
Data Shredding RAID Mode App 20080046764 - Grinchuk; Mikhail I. ; et al.	2008-02-21
Verification of RRAM tiling netlist Grant 7,315,993 - Nikitin , et al. January 1, 2	2008-01-01
System and method for efficiently testing a large random access memory space Grant 7,305,597 - Andreev , et al. December 4, 2	2007-12-04
Memory mapping for parallel turbo decoding Grant 7,305,593 - Andreev , et al. December 4, 2	2007-12-04
Method and system for outputting a sequence of commands and data described by a flowchart App 20070169009 - Nikitin; Andrey A. ; et al.	2007-07-19
Memory timing model with back-annotating App 20070143648 - Andreev; Alexander ; et al.	2007-06-21
Method and apparatus for generating memory models and timing database App 20070136704 - Andreev; Alexandre ; et al.	2007-06-14
Search engine for large-width data Grant 7,231,383 - Andreev , et al. June 12, 2	2007-06-12
Method and apparatus for tiling memories in integrated circuit layout App 20070108961 - Andreev; Alexandre ; et al.	2007-05-17
Method and apparatus for mapping design memories to integrated circuit layout App 20070113212 - Andreev; Alexandre ; et al.	2007-05-17
Method and BIST architecture for fast memory testing in platform-based integrated circuit Grant 7,216,278 - Andreev , et al. May 8, 2	2007-05-08
High performance tiling for RRAM memory App 20070091105 - Andreev; Alexander ; et al.	2007-04-26
Method and system for analyzing the quality of an OPC mask App 20070079277 - Golubtsov; Ilya ; et al.	2007-04-05
RRAM memory timing learning tool Grant 7,200,826 - Andreev , et al. April 3, 2	2007-04-03
Multimode delay analyzer App 20070044053 - Andreev; Alexander ; et al.	2007-02-22
FIFO memory with single port memory modules for allowing simultaneous read and write operations Grant 7,181,563 - Andreev , et al. February 20, 2	2007-02-20
Yield driven memory placement system Grant 7,168,052 - Andreev , et al. January 23, 2	2007-01-23
Memory generation and placement Grant 7,155,688 - Andreev , et al. December 26, 2	2006-12-26
Decomposer for parallel turbo decoding, process and integrated circuit App 20060236194 - Andreev; Alexander E. ; et al.	2006-10-19
Process and apparatus for fast assignment of objects to a rectangle Grant 7,111,264 - Andreev , et al. September 19, 2	2006-09-19
Decomposer for parallel turbo decoding, process and integrated circuit Grant 7,096,413 - Andreev , et al. August 22, 2	2006-08-22
Controller architecture for memory mapping Grant 7,065,606 - Andreev , et al. June 20, 2	2006-06-20
RRAM memory timing learning tool App 20060117284 - Andreev; Alexandre ; et al.	2006-06-01
Verification of RRAM tiling netlist App 20060117281 - Nikitin; Andrey A. ; et al.	2006-06-01
Pseudo-random one-to-one circuit synthesis Grant 7,050,582 - Andreev , et al. May 23, 2	2006-05-23
Memory generation and placement App 20060107247 - Andreev; Alexandre ; et al.	2006-05-18
FFS search and edit pipeline separation Grant 7,035,844 - Andreev , et al. April 25, 2	2006-04-25
RRAM backend flow Grant 7,028,274 - Andreev , et al. April 11, 2	2006-04-11
Table module compiler equivalent to ROM Grant 7,003,510 - Andreev , et al. February 21, 2	2006-02-21
Method and system for outputting a sequence of commands and data described by a flowchart App 20060020927 - Andreev; Alexander E. ; et al.	2006-01-26
Universal gates for ICs and transformation of netlists for their implementation Grant 6,988,252 - Andreev , et al. January 17, 2	2006-01-17
Yield driven memory placement system App 20060010092 - Andreev; Alexander E. ; et al.	2006-01-12
User selectable editing protocol for fast flexible search engine Grant 6,941,314 - Andreev , et al. September 6, 2	2005-09-06
Fault repair controller for redundant memory integrated circuits Grant 6,928,591 - Grinchuk , et al. August 9, 2	2005-08-09
Timing-driven placement method utilizing novel interconnect delay model Grant 6,901,571 - Petranovic , et al. May 31, 2	2005-05-31
Method and system for constructing a hierarchy-driven chip covering for optical proximity correction Grant 6,898,780 - Egorov , et al. May 24, 2	2005-05-24
FIFO memory with single port memory modules for allowing simultaneous read and write operations App 20050091465 - Andreev, Alexander E. ; et al.	2005-04-28
Memory that allows simultaneous read requests Grant 6,886,088 - Andreev , et al. April 26, 2	2005-04-26
Process and apparatus for fast assignment of objects to a rectangle App 20050086624 - Andreev, Alexander E. ; et al.	2005-04-21
Controller architecture for memory mapping App 20050055527 - Andreev, Alexander E. ; et al.	2005-03-10
Memory mapping for parallel turbo decoding App 20050050426 - Andreev, Alexander E. ; et al.	2005-03-03
Universal gates for ICs and transformation of netlists for their implementation App 20050030067 - Andreev, Alexander E. ; et al.	2005-02-10
Multidirectional router Grant 6,845,495 - Andreev , et al. January 18, 2	2005-01-18
Symbolic simulation driven netlist simplification Grant 6,842,750 - Andreev , et al. January 11, 2	2005-01-11
Process for layout of memory matrices in integrated circuits Grant 6,804,811 - Andreev , et al. October 12, 2	2004-10-12
Method of decreasing instantaneous current without affecting timing Grant 6,795,954 - Andreev , et al. September 21, 2	2004-09-21
Prefix comparator Grant 6,785,699 - Andreev , et al. August 31, 2	2004-08-31
Process layout of buffer modules in integrated circuits Grant 6,760,896 - Andreev , et al. July 6, 2	2004-07-06
Fault repair controller for redundant memory integrated circuits App 20040128593 - Grinchuk, Mikhail I. ; et al.	2004-07-01
Method and system for constructing a hierarchy-driven chip covering for optical proximity correction App 20040123266 - Egorov, Evgueny E. ; et al.	2004-06-24
Memory that allows simultaneous read requests App 20040107308 - Andreev, Egor A. ; et al.	2004-06-03
Decomposer for parallel turbo decoding, process and integrated circuit App 20040098653 - Andreev, Alexander E. ; et al.	2004-05-20
Editing protocol for flexible search engines Grant 6,735,600 - Andreev , et al. May 11, 2	2004-05-11
Method of decreasing instantaneous current without affecting timing App 20040076067 - Andreev, Alexander E. ; et al.	2004-04-22
Process For Layout Of Memory Matrices In Integrated Circuits App 20040060029 - Andreev, Alexander E. ; et al.	2004-03-25
Process layout of buffer modules in integrated circuits App 20040060027 - Andreev, Alexander E. ; et al.	2004-03-25
Process for fast cell placement in integrated circuit design Grant 6,704,915 - Andreev , et al. March 9, 2	2004-03-09
Table module compiler equivalent to ROM App 20030236774 - Andreev, Alexander E. ; et al.	2003-12-25
Fast free memory address controller Grant 6,662,287 - Andreev , et al. December 9, 2	2003-12-09
User selectable editing protocol for fast flexible search engine App 20030208495 - Andreev, Alexander E. ; et al.	2003-11-06
Search engine for large-width data App 20030208475 - Andreev, Alexander E. ; et al.	2003-11-06
Symbolic simulation driven netlist simplification App 20030187815 - Andreev, Alexander E. ; et al.	2003-10-02
FFS search and edit pipline separation App 20030163442 - Andreev, Alexander E. ; et al.	2003-08-28
Method and apparatus for formula area and delay minimization Grant 6,587,990 - Andreev , et al. July 1, 2	2003-07-01
Multidirectional router App 20030121017 - Andreev, Alexandre E. ; et al.	2003-06-26
Fast flexible search engine for longest prefix match Grant 6,564,211 - Andreev , et al. May 13, 2	2003-05-13
Flexible search engine having sorted binary search tree for perfect match Grant 6,553,370 - Andreev , et al. April 22, 2	2003-04-22
Method and apparatus for application of proximity correction with relative segmentation Grant 6,532,585 - Petranovic , et al. March 11, 2	2003-03-11
Method and apparatus for minimization of net delay by optimal buffer insertion Grant 6,519,746 - Andreev , et al. February 11, 2	2003-02-11
Method and apparatus for application of proximity correction with unitary segmentation Grant 6,499,003 - Jones , et al. December 24, 2	2002-12-24
Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms Grant 6,493,658 - Koford , et al. December 10, 2	2002-12-10
Process, apparatus and program for transforming program language description of an IC to an RTL description Grant 6,487,698 - Andreev , et al. November 26, 2	2002-11-26
Process for fast cell placement in integrated circuit design App 20020124233 - Andreev, Alexander E. ; et al.	2002-09-05
Hexagonal architecture Grant 6,407,434 - Rostoker , et al. June 18, 2	2002-06-18
Method And Apparatus For Application Of Proximity Correction With Unitary Segmentation App 20020004714 - JONES, EDWIN ; et al.	2002-01-10
Method and apparatus for parallel simultaneous global and detail routing Grant 6,324,674 - Andreev , et al. November 27, 2	2001-11-27
Advanced modular cell placement system Grant 6,292,929 - Scepanovic , et al. September 18, 2	2001-09-18
Method and apparatus for local optimization of the global routing Grant 6,289,495 - Raspopovic , et al. September 11, 2	2001-09-11
Modifying Timing Graph To Avoid Given Set Of Paths App 20010020289 - PAVISIC, IVAN ; et al.	2001-09-06
Method And Apparatus For Parallel Simultaneous Global And Detail Routing App 20010018759 - ANDREEV, ALEXANDER E. ; et al.	2001-08-30
Method and apparatus for parallel routing locking mechanism Grant 6,269,469 - Pavisic , et al. July 31, 2	2001-07-31
Method and apparatus for coarse global routing Grant 6,260,183 - Raspopovic , et al. July 10, 2	2001-07-10
Net routing using basis element decomposition Grant 6,253,363 - Gasanov , et al. June 26, 2	2001-06-26
Advanced Modular Cell Placement System App 20010003843 - SCEPANOVIC, RANKO ; et al.	2001-06-14
Method and apparatus for parallel Steiner tree routing Grant 6,247,167 - Raspopovic , et al. June 12, 2	2001-06-12
Method and apparatus for minimization of process defects while routing Grant 6,230,306 - Raspopovic , et al. May 8, 2	2001-05-08
Advanced modular cell placement system with overlap remover with minimal noise Grant 6,223,332 - Scepanovic , et al. April 24, 2	2001-04-24
Mask having an arbitrary complex transmission function Grant 6,197,456 - Aleshin , et al. March 6, 2	2001-03-06
Method and apparatus for determining wire routing Grant 6,186,676 - Andreev , et al. February 13, 2	2001-02-13
Method and apparatus for hierarchical global routing descend Grant 6,175,950 - Scepanovic , et al. January 16, 2	2001-01-16
Cell placement representation and transposition for integrated circuit physical design automation system Grant 6,155,725 - Scepanovic , et al. December 5, 2	2000-12-05
Memory-saving method and apparatus for partitioning high fanout nets Grant 6,154,874 - Scepanovic , et al. November 28, 2	2000-11-28
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints Grant 6,134,702 - Scepanovic , et al. October 17, 2	2000-10-17
Method and apparatus for horizontal congestion removal Grant 6,123,736 - Pavisic , et al. September 26, 2	2000-09-26
Triangular semiconductor or gate Grant 6,097,073 - Rostoker , et al. August 1, 2	2000-08-01
Advanced modular cell placement system with sinusoidal optimization Grant 6,085,032 - Scepanovic , et al. July 4, 2	2000-07-04
Method and apparatus for continuous column density optimization Grant 6,075,933 - Pavisic , et al. June 13, 2	2000-06-13
Method and apparatus for congestion removal Grant 6,068,662 - Scepanovic , et al. May 30, 2	2000-05-30
Method and apparatus for congestion driven placement Grant 6,070,108 - Andreev , et al. May 30, 2	2000-05-30
Advanced modular cell placement system Grant 6,067,409 - Scepanovic , et al. May 23, 2	2000-05-23
Method and apparatus for vertical congestion removal Grant 6,058,254 - Scepanovic , et al. May 2, 2	2000-05-02
Advanced modular cell placement system with overlap remover with minimal noise Grant 6,026,223 - Scepanovic , et al. February 15, 2	2000-02-15
Architecture having diamond shaped or parallelogram shaped cells Grant 5,973,376 - Rostoker , et al. October 26, 1	1999-10-26
Congestion based cost factor computing apparatus for integrated circuit physical design automation system Grant 5,914,887 - Scepanovic , et al. June 22, 1	1999-06-22
Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles" Grant 5,909,376 - Scepanovic , et al. June 1, 1	1999-06-01
Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows Grant 5,903,461 - Rostoker , et al. May 11, 1	1999-05-11
Advanced modular cell placement system with iterative one dimensional preplacement optimization Grant 5,892,688 - Scepanovic , et al. April 6, 1	1999-04-06
Tri-directional interconnect architecture for SRAM Grant 5,889,329 - Rostoker , et al. March 30, 1	1999-03-30
Towards optimal Steiner tree routing in the presence of rectilinear obstacles Grant 5,880,970 - Scepanovic , et al. March 9, 1	1999-03-09
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system Grant 5,875,117 - Jones , et al. February 23, 1	1999-02-23
Hexagonal sense cell architecture Grant 5,872,380 - Rostoker , et al. February 16, 1	1999-02-16
Optimization processing for integrated circuit physical design automation system using parallel moving windows Grant 5,870,313 - Boyle , et al. February 9, 1	1999-02-09
Triangular semiconductor NAND gate Grant 5,864,165 - Rostoker , et al. January 26, 1	1999-01-26
Advanced modular cell placement system with universal affinity driven discrete placement optimization Grant 5,844,811 - Scepanovic , et al. December 1, 1	1998-12-01
Physical design automation system and method using monotonically improving linear clusterization Grant 5,838,585 - Scepanovic , et al. November 17, 1	1998-11-17
Triangular semiconductor "AND" gate device Grant 5,834,821 - Rostoker , et al. November 10, 1	1998-11-10
Advanced modular cell placement system with wire length driven affinity system Grant 5,831,863 - Scepanovic , et al. November 3, 1	1998-11-03
CAD for hexagonal architecture Grant 5,822,214 - Rostoker , et al. October 13, 1	1998-10-13
Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip Grant 5,815,403 - Jones , et al. September 29, 1	1998-09-29
Transistors having dynamically adjustable characteristics Grant 5,811,863 - Rostoker , et al. September 22, 1	1998-09-22
Polydirectional non-orthoginal three layer interconnect architecture Grant 5,808,330 - Rostoker , et al. September 15, 1	1998-09-15
Advanced modular cell placement system with cell placement crystallization Grant 5,808,899 - Scepanovic , et al. September 15, 1	1998-09-15
Hexagonal SRAM architecture Grant 5,801,422 - Rostoker , et al. September 1, 1	1998-09-01
Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization Grant 5,796,625 - Scepanovic , et al. August 18, 1	1998-08-18
Cell placement alteration apparatus for integrated circuit chip physical design automation system Grant 5,793,644 - Koford , et al. August 11, 1	1998-08-11
Hexagonal architecture with triangular shaped cells Grant 5,789,770 - Rostoker , et al. August 4, 1	1998-08-04
Method for producing integrated circuit chip having optimized cell placement Grant 5,781,439 - Rostoker , et al. July 14, 1	1998-07-14
Hexagonal field programmable gate array architecture Grant 5,777,360 - Rostoker , et al. July 7, 1	1998-07-07
Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations Grant 5,745,363 - Rostoker , et al. April 28, 1	1998-04-28
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system Grant 5,742,510 - Rostoker , et al. April 21, 1	1998-04-21
Hexagonal DRAM array Grant 5,742,086 - Rostoker , et al. April 21, 1	1998-04-21
Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization Grant 5,712,793 - Scepanovic , et al. January 27, 1	1998-01-27
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints Grant 5,699,265 - Scepanovic , et al. December 16, 1	1997-12-16
Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters Grant 5,661,663 - Scepanovic , et al. August 26, 1	1997-08-26
Microelectronic integrated circuit including triangular CMOS "nand" gate device Grant 5,650,653 - Rostoker , et al. July 22, 1	1997-07-22
Optimal pad location method for microelectronic circuit cell placement Grant 5,638,293 - Scepanovic , et al. June 10, 1	1997-06-10
Computer implemented method for producing optimized cell placement for integrated circiut chip Grant 5,636,125 - Rostoker , et al. June 3, 1	1997-06-03
Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry Grant 5,578,840 - Scepanovic , et al. November 26, 1	1996-11-26
Cell placement alteration apparatus for integrated circuit chip physical design automation system Grant 5,557,533 - Koford , et al. September 17, 1	1996-09-17
Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing Grant 5,495,419 - Rostoker , et al. February 27, 1	1996-02-27
Towards optical steiner tree routing in the presence of rectilinear obstacles Grant 5,491,641 - Scepanovic , et al. February 13, 1	1996-02-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.