U.S. patent application number 09/821510 was filed with the patent office on 2001-08-09 for a new structure to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. Invention is credited to Hsieh, Chia-Ta, Kuo, Di-Son, Lin, Yia-Fen, Sung, Hung-Cheng, Yeh, Jack.
Application Number | 20010012662 09/821510 |
Document ID | / |
Family ID | 23247751 |
Filed Date | 2001-08-09 |
United States Patent
Application |
20010012662 |
Kind Code |
A1 |
Hsieh, Chia-Ta ; et
al. |
August 9, 2001 |
A new structure to fabricate split-gate with self-aligned source
and self-aligned floating gate to control gate
Abstract
A split-gate flash memory cell having self-aligned source and
floating gate self-aligned to control gate is disclosed as well as
a method of forming the same. This is accomplished by depositing
over a gate oxide layer on a silicon substrate a poly-1 layer to
form a vertical control gate followed by depositing a poly-2 layer
to form a spacer floating gate adjacent to the control gate with an
intervening intergate oxide layer. The source is self-aligned and
the floating gate is also formed to be self-aligned to the control
gate, thus making it possible to reduce the cell size. The
resulting self-aligned source alleviates punch-through from source
to control gate while the self-aligned floating gate with respect
to the control gate provides improved programmability. The method
also replaces the conventional poly oxidation process thereby
yielding improved sharp peak of floating gate for improved erasing
and writing of the split-gate flash memory cell.
Inventors: |
Hsieh, Chia-Ta; (Tai-nan,
TW) ; Sung, Hung-Cheng; (Hsin-chu, TW) ; Lin,
Yia-Fen; (Non-tou, TW) ; Yeh, Jack; (Hsin-chu,
TW) ; Kuo, Di-Son; (Hsin-chu, TW) |
Correspondence
Address: |
George O. Saile
20 McIntosh Drive
Poughkeepsie
NY
12603
US
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
COMPANY
|
Family ID: |
23247751 |
Appl. No.: |
09/821510 |
Filed: |
March 30, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09821510 |
Mar 30, 2001 |
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09320759 |
May 27, 1999 |
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6228695 |
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Current U.S.
Class: |
438/257 ;
257/E21.209; 257/E21.682; 257/E27.103; 438/266; 438/267 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 27/115 20130101; H01L 29/40114 20190801 |
Class at
Publication: |
438/257 ;
438/266; 438/267 |
International
Class: |
H01L 021/336 |
Claims
What is claimed is:
1. A method of forming split-gate flash memory having a
self-aligned source as well as a floating gate self-aligned to
control gate comprising the steps of: providing a silicon substrate
having a plurality of active and field regions defined by shallow
trench isolation (STI); forming first gate oxide layer over said
substrate; forming first polysilicon (poly-1) layer over said first
gate oxide layer; forming silicide layer over said poly-1 layer;
forming tetraethyl orthosilicate (TEOS) layer over said silicide
layer; forming first photoresist layer over said TEOS layer;
patterning said first photoresist layer to define control gate
area; etching said TEOS layer and said silicide layer through said
patterning in said first photoresist layer and forming opening in
said TEOS layer exposing portion of said poly-1 layer; etching said
exposed portion of said poly-1 layer and forming control gate;
removing said first photoresist layer; forming second gate oxide
layer over said substrate; forming partial-depth second polysilicon
(poly-2) layer over said second gate oxide layer; etching said
partial-depth poly-2 layer to form drain spacer and source spacer
and sharp peak therein; forming second photoresist layer over said
substrate to define self-align source (SAS) region; etching
partially said isolation oxide layer through said second
photoresist layer in said SAS region; removing said second
photoresist layer; forming third photoresist layer over said
substrate with openings exposing said poly-2 drain spacer and said
poly-2 covering said STI regions; etching through said openings in
said third photoresist layer to remove said poly-2 drain spacer and
said poly-2 covering said STI regions to form floating gate cell;
forming fourth photoresist layer over said substrate to redefine
self-align source (SAS) region; etching completely said isolation
oxide layer through said fourth photoresist layer until said
silicon substrate is reached in said SAS region; ion implanting
said SAS region; removing said fourth photoresist layer; annealing
said tungsten silicide layer; forming drain in said substrate;
forming interlevel dielectric layer (ILD) over said substrate; and
forming metal contact in said ILD layer to complete the forming of
said split-gate flash memory cell.
2. The method of claim 1, wherein said forming said first gate
oxide layer is accomplished by thermal growth at a temperature
between about 850 to 950.degree. C.
3. The method of claim 2, wherein said gate oxide layer has a
thickness between about 190 to 210 angstroms (.ANG.).
4. The method of claim 1, wherein said forming a poly-1 layer is
accomplished with silicon source SiH.sub.4 using LPCVD at a
temperature between about 550 to 620.degree. C.
5. The method of claim 1, wherein said poly-1 layer has a thickness
between about 900 to 1100 angstroms (.ANG.).
6. The method of claim 1, wherein said forming silicide is
accomplished by co-sputtering tungsten.
7. The method of claim 6, wherein the thickness of said silicide
layer is between about 800 to 1500 .ANG..
8. The method of claim 1, wherein said forming said TEOS layer is
accomplished by decomposing tetraethyl orthosilicate at a
temperature between about 600-650.degree. C.
9. The method of claim 1, wherein said TEOS layer has a thickness
between about 1900 to 2100 .ANG..
10. The method of claim 1, wherein said etching said TEOS layer is
accomplished with etch recipe comprising O.sub.2 gas.
11. The method of claim 1, wherein said etching said exposed
portion of said poly-1 layer is accomplished with a recipe
comprising gases HBr, Cl.sub.2, He and O.sub.2.
12. The method of claim 1, wherein said forming said second gate
oxide layer is accomplished by thermal growth at a temperature
between about 850 to 950.degree. C.
13. The method of claim 1, wherein said second oxide layer has a
thickness between about 70 to 90 .ANG..
14. The method of claim 1, wherein said forming said partial-depth
poly-2 layer is accomplished with silicon source SiH.sub.4 using
LPCVD at a temperature between about 550 to 620.degree. C.
15. The method of claim 1, wherein said partial-depth poly-2 layer
has a thickness between about 1900 to 2100 .ANG..
16. The method of claim 1, wherein said etching said partial-depth
poly-2 layer to form drain spacer and source spacer is accomplished
with gases O.sub.2, HBr, Cl.sub.2 and He.
17. The method of claim 1, wherein said etching partially said
second gate oxide layer is accomplished with gases CF.sub.4,
CHF.sub.3 and O.sub.2.
18. The method of claim 1, wherein said etching partially said
isolation oxide layer is performed until said isolation oxide layer
has a thickness between about 300 to 600 .ANG..
19. The method of claim 1, wherein said etching through said
openings in said third photoresist layer to remove said poly-2
drain spacer and said poly-2 covering said STI regions to form
floating gate cell is accomplished with gases O.sub.2, HBr,
Cl.sub.2 and He.
20. The method of claim 1, wherein said etching completely said
isolation oxide layer through fourth photoresist layer in said SAS
region is accomplished with gases CF.sub.4, CHF.sub.3 and
O.sub.2.
21. The method of claim 1, wherein said ion implanting said SAS
region is accomplished by implanting phosphorous ions with a dosage
between about 1.times.10.sup.15 to 9.times.10.sup.15 atoms/cm.sup.2
and at an energy between about 10 to 60 KeV.
22. The method of claim 1, wherein said annealing said silicide
layer is accomplished at a temperature between about 800 to
900.degree. C.
23. The method of claim 1, wherein said forming said drain is
accomplished by implanting arsenic ions at a dosage level between
about 1.times.10.sup.15 to 9.times.10.sup.15 atoms/cm.sup.2 with
energy level between about 10 to 60 KeV.
24. The method of claim 1, wherein said forming said interlevel ILD
layer is accomplished by depositing an oxide layer to a thickness
between about 10,000 to 15,000 .ANG..
25. The method of claim 1, wherein said forming said metal contact
in said ILD layer is accomplished by patterning said ILD layer with
contact hole pattern and then filling with metal.
26. A split-gate flash memory cell with a self-aligned source and a
floating gate self-aligned to control gate comprising: a substrate
having active and field regions defined; a gate oxide formed over
said substrate; a poly-1 layer forming a columnar control gate over
said gate oxide; a silicide layer covering said columnar control
gate; a TEOS layer covering said silicide layer; a poly-2 layer
forming a spacer floating gate adjacent and self-aligned to said
columnar control gate with an intervening intergate oxide layer; a
sharp poly-2 peak in said spacer floating gate; and a self-aligned
source in said split-gate flash memory cell.
27. The split-gate memory cell of claim 26, wherein said gate oxide
layer is formed by thermal growth at a temperature between about
850 to 950.degree. C.
28. The split-gate memory cell of claim 26, wherein said poly-1
layer forming said columnar control gate has a thickness between
about 900 to 1100 .ANG..
29. The method of claim 26, wherein said silicide layer is
co-sputtered tungsten having a thickness between about 800 to 1500
.ANG..
30. The split-gate memory cell of claim 26, wherein said TEOS layer
has thickness between about 1900 to 2100 .ANG..
31. The split-gate memory cell of claim 26, wherein said poly-2
layer forming said spacer floating gate adjacent to said columnar
control gate has a thickness between about 1900 to 2100 .ANG..
32. The split-gate memory cell of claim 26, wherein said
intervening intergate oxide layer has a thickness between about 70
to 90 .ANG..
33. The split-gate memory cell of claim 26, wherein said sharp
poly-2 peak in said spacer floating gate has a thickness between
about 1900 to 2100 .ANG..
Description
BACKGROUND OF THE INVENTION
[0001] (1) Field of the Invention
[0002] The present invention relates to semiconductor memory
devices and more particularly to a method of forming a split-gate
flash memory cell having a self-aligned source as well as a
floating gate self-aligned to a control gate.
[0003] (2) Description of the Related Art
[0004] A split-gate flash memory device is characterized by its
split-gate side (between the control gate and the drain) and the
stacked-side (between the floating gate and the source).
Conventionally, the floating gate is not self-aligned to the
control gate, and neither is the self-aligned source commonly used.
Without self-aligned source, the problem of punch-through from the
source to the control gate is encountered which in turn causes
programming fails. And in the absence of alignment between the
floating gate and the control gate, the misalignment causes
variability of the coupling ratio, which also causes weak
programmability in the cell. As is known, the coupling ratio
affects the program speed, that is, the larger the coupling ratio,
the faster is the programming speed, and is not a fixed value by
virtue of the variability of the channel length and hence that of
the overlap between the floating gate and the source. Usually, if
channel length is increased through greater lateral diffusion in
the source region, punchthrough occurs due to excessive current
well below the threshold voltage. It is disclosed later in the
embodiments of this invention that these problems can be alleviated
by forming self-aligned source and also self-aligned floating gate
with respect to the control gate. As an added advantage, it is
shown that the cell size can be reduced by using self-alignment
methods and self-aligned structures of this invention.
[0005] Over the years, numerous improvements in the performance as
well as in the size of memory devices have been made by varying the
simple, basic one-transistor memory cell, which contains one
transistor and one capacitor. The variations consist of different
methods of forming capacitors, with single, double or triple layers
of polysilicon, and different materials for the word and bit lines.
In general, memory devices include electrically erasable and
electrically programmable read-only memories (EEPROMs) of flash
electrically erasable and electrically programmable read-only
memories (flash EEPROMs). Many types of memory cells for EEPROMs or
flash EEPROMs may have source and drains regions that are aligned
to a floating gate or aligned to spacers. When the source and drain
regions are aligned to the floating gate, a gate electrode for a
select transistor is separate from the control gate electrode of
the floating gate transistor. Separate select and control gates
increase the size of the memory cell. If the source and drain
regions are aligned to a spacer formed after the floating gate is
formed, the floating gate typically does not overlie portions of
the source and drain regions. Programming and erasing performance
is degraded by the offset between the floating gate and source and
drain regions.
[0006] Most conventional flash-EEPROM cells use a
double-polysilicon (poly) structure of which the well known
split-gate cell is shown in FIG. 1a. Here, two MOS transistors
share a source (25). Each transistor is formed on a semiconductor
substrate (10) having a first doped region (20), a second doped
region (25), a channel region (23), a gate oxide (30), a floating
gate (40), intergate dielectric layer (50) and control gate (60).
Substrate (10) and channel region (23) have a first conductivity
type, and the first (20) and second (25) doped regions have a
second conductivity type that is opposite the first conductivity
type.
[0007] As seen in FIG. 1a, the first doped region, (20), lies
within the substrate. The second doped region, (25), also lies
within substrate (10) and is spaced apart form the first doped
region (20). Channel region (23) lies within substrate (10) and
between first (20) and second (25) doped regions. Gate oxide layer
(30) overlies substrate (10). Floating gate (40), to which there is
no direct electrical connection, and which overlies substrate (10),
is separated from substrate (10) by a thin layer of gate oxide (30)
while control gate (60), to which there is direct electrical
connection, is generally positioned over the floating gate with
intergate oxide (50) therebetween.
[0008] In the structure shown in FIG. 1a, control gate (60)
overlaps the channel region, (23) under the floating gate, (40).
This structure is needed because when the cell is erased, it leaves
a positive charge on the floating gate. As a result, the channel
under the floating gate becomes inverted. The series MOS transistor
(formed by the control gate over the channel region) is needed in
order to prevent current flow from control gate to floating gate.
The length of the transistor, that is the overlap of the control
gate over the channel region (23) determines the cell performance.
Furthermore, edges (41), (43) can affect the programming of the
cell by the source size and hot electron injection through the
intergate dielectric layer (50) at such edges. Hot electron
injection is further affected by, what is called, gate bird's beak
(43) that is formed in conventional cells. On the other hand, it
will be known to those skilled in the art that corners such as (41)
can affect the source coupling ratio also.
[0009] To program the transistor shown in FIG. 1a, charge is
transferred from substrate (10) through gate oxide (30) and is
stored on floating gate (40) of the transistor. The amount of
charge is set to one of two levels to indicate whether the cell has
been programmed "on" of "off." "Reading" of the cell's state is
accomplished by applying appropriate voltages to the cell source
(25) and drain (20), and to control gate (60), and then sensing the
amount of charge on floating gate (40). To erase the contents of
the cell, the programming process is reversed, namely, charges are
removed from the floating gate by transferring them back to the
substrate through the gate oxide.
[0010] This programming and erasing of an EEPROM is accomplished
electrically and in-circuit by using Fowler-Nordheim tunneling as
is well known in prior art. Basically, a sufficiently high voltage
is applied to the control gate and drain while the source is
grounded to create a flow of electrons in the channel region in the
substrate. Some of these electrons gain enough energy to transfer
from the substrate to the floating gate through the thin gate oxide
layer by means of Fowler-Nordheim tunneling. The tunneling is
achieved by raising the voltage level on the control gate to a
sufficiently high value of about 12 volts. As the electronic charge
builds up on the floating gate, the electric field is reduced,
which reduces the electron flow. When, finally, the high voltage is
removed, the floating gate remains charged to a value larger than
the threshold voltage of a logic high that would turn it on. Thus,
even when a logic high is applied to the control gate, the EEPROM
remains off. Since tunneling process is reversible, the floating
gate can be erased by grounding the control gate and raising the
drain voltage, thereby causing the stored charge on the floating
gate to flow back to the substrate.
[0011] In the conventional memory cell shown in FIG. 1a, word lines
(not shown) are connected to control gate (60) of the MOS
transistor, while the length of the MOS transistor itself is
defined by the source (25) drain (20) n+ regions shown in the same
Figure. As is well known by those skilled in the art, the
transistor channel is defined by masking the n+ regions. However,
the channel length of the transistor varies depending upon the
alignment of the floating gate (40) with the source and drain
regions. This introduces significant variations in cell performance
from die to die and from wafer to wafer. Furthermore, the
uncertainty in the final position of the n+ regions causes
variations in the series resistance of the bit lines connected to
those regions, and hence additional variation in the cell
performance.
[0012] In prior art, Hsia, et al., of U.S. Pat. No. 4,861,730 teach
a process for producing a high density split gate nonvolatile
memory cell which includes a floating gate and a control gate that
is formed above the floating gate. The drain region is self-aligned
to the floating gate and source region is self-aligned to the
control gate. In U.S. Pat. No. 5,063,172, Manley discloses an
integrated circuit fabrication method that utilizes a conductive
spacer to define the gate length of the series select transistor in
a split-gate memory cell, thereby eliminating misalignment
problems.
[0013] On the other hand, Chen, et al., in U.S. Pat. No. 5,824,484
disclose a sidewall select gate which is formed in conjunction with
a semiconductor doped oxide to form a nonvolatile memory cell. In
another U.S. Pat. No. 5,750,427 Kaya, et al., disclose a
non-volatile split-gate memory cell which can be programmed with
only a five volt power supply and is fabricated using standard
transistor processing methods. Also, a method to improve erase
speed of split-gate flash is taught by Hsieh, et al., in U.S. Pat.
No. 5,858,840 by judiciously implanting nitrogen ions in the first
polysilicon layer and then removing them from the area where the
floating gate is to be formed.
[0014] While prior art offers different approaches for forming
different split-gate flash memory cells, the present invention
discloses a still different method where the floating gate is
aligned to the control gate. In the split-gate cells shown in FIG.
1 of prior art, floating gate (40) is not aligned to control gate
(60) for the dimensions (x) and (y) are different. This is also
shown in a top view given in FIG. 1b. It is disclosed later in the
embodiments of this invention, where this variability is avoided
and the performance of the split-gate flash memory cell is
improved.
SUMMARY OF THE INVENTION
[0015] It is therefore an object of this invention to provide a
method of forming split-gate flash memory with self-aligned
source.
[0016] It is another object of this invention to provide a method
of forming split-gate flash memory with self-aligned floating gate
to control gate.
[0017] It is yet another object of the present invention to provide
a split-gate flash memory cell with both self-aligned source as
well as self-aligned floating gate to control gate in order to
alleviate punch-through from source to control gate as well as to
improve programmability of the cell.
[0018] These objects are accomplished by providing a silicon
substrate having a plurality of active and field regions defined by
shallow trench isolation (STI); forming first gate oxide layer over
said substrate; forming first polysilicon (poly-1) layer over said
first gate oxide layer; forming silicide layer over said poly-1
layer; forming tetraethyl orthosilicate (TEOS) layer over said
silicide layer; forming first photoresist layer over said TEOS
layer; patterning said first photoresist layer to define control
gate area; etching said TEOS layer through said patterning in said
first photoresist layer and forming opening in said TEOS layer
exposing portion of said poly-1 layer; etching said exposed portion
of said poly-1 layer and forming control gate; removing said first
photoresist layer; forming second gate oxide layer over said
substrate; forming partial-depth second polysilicon (poly-2) layer
over said second gate oxide layer; etching said partial-depth
poly-2 layer to form drain spacer and source spacer and sharp peak
therein; forming second photoresist layer over said substrate to
define self-align source (SAS) region; etching partially said
second gate oxide layer through said second photoresist layer in
said SAS region; removing said second photoresist layer; forming
third photoresist layer over said substrate with openings exposing
said poly-2 drain spacer and said poly-2 covering said STI regions;
etching through said openings in said third photoresist layer to
remove said poly-2 drain spacer and said poly-2 covering said STI
regions to form floating gate cell; forming fourth photoresist
layer over said substrate to redefine self-align source (SAS)
region; etching completely said second gate oxide layer through
said fourth photoresist layer until said silicon substrate is
reached in said SAS region; ion implanting said SAS region;
removing said fourth photoresist layer; annealing said tungsten
silicide layer; forming drain in said substrate; forming interlevel
dielectric layer (ILD) over said substrate; and forming metal
contact in said ILD layer to complete the forming of said
split-gate flash memory cell.
[0019] These objects are further accomplished by providing memory
cell comprising a substrate having active and field regions
defined; a gate oxide formed over said substrate; a poly-1 layer
forming a columnar control gate over said gate oxide; a silicide
layer covering said columnar control gate; a TEOS layer covering
said silicide layer; a poly-2 layer forming a spacer floating gate
adjacent and self-aligned to said columnar control gate with an
intervening intergate oxide layer; a sharp poly-2 peak in said
spacer floating gate; and a self-aligned source in said split-gate
flash memory cell.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1a shows a cross-sectional view of a split-gate type
memory cell of prior art.
[0021] FIG. 1b shows a top view of the split-gate memory cell of
prior art of FIG. 1a.
[0022] FIGS. 2a-2h show plan view of a semiconductor substrate at
different stages of the disclosed processing steps. FIGS. 3a-3h, on
the other hand, show cross-sectional views of the substrate
corresponding to locations shown on FIGS. 2a-2h. FIGS. 3a-3h will
now be described more fully as follows:
[0023] FIG. 3a is a cross-sectional view of the semiconductor
substrate of FIG. 2a showing the forming of the passive and active
regions according to this invention.
[0024] FIG. 3b is a cross-sectional view of the semiconductor
substrate of FIG. 2b showing the forming of the vertical control
gate of this invention underlying the silicide and TEOS layers
according to this invention.
[0025] FIG. 3c is a cross-sectional view of the semiconductor
substrate of FIG. 2c showing the forming of the spacer floating
gate self-aligned to the control gate of this invention.
[0026] FIG. 3d is a cross-sectional view of the semiconductor
substrate of FIG. 2d showing the forming of the self-aligned source
(SAS) of to this invention.
[0027] FIG. 3e is a cross-sectional view of the semiconductor
substrate of FIG. 2e showing the etching of the poly-2 not covered
by a photoresist layer according to this invention.
[0028] FIG. 3f is a cross-sectional view of the semiconductor
substrate of FIG. 2f showing the ion implanting of the SAS
according to this invention.
[0029] FIG. 3g is a cross-sectional view of the semiconductor
substrate of FIG. 2g showing the forming of the drain of the memory
cell of this invention.
[0030] FIGS. 3h and 3i show, respectively, the erasing and writing
operations of the disclosed split-gate flash memory cell
represented by the cross-sectional view taken at the 3h-3h location
shown in FIG. 2h.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0031] Referring now to the drawings, specifically to FIGS. 2a-2h,
and FIGS. 3a-3i, there is shown a method of forming a split gate
flash memory cell having both a self-aligned source as well a
floating gate self-aligned to a control gate. FIGS. 2a-2h show plan
views of a semiconductor substrate at different stages of the
disclosed processing steps. FIGS. 3a-3i, on the other hand, show
cross-sectional views of the substrate corresponding to locations
shown on FIGS. 2a-2h. FIGS. 3h and 3i show the writing
(programming) and erasing operations of the disclosed memory cell
represented by the cross-sectional view taken at the 3h-3h location
shown in FIG. 2h.
[0032] In FIG. 2a, substrate (100), preferably silicon, is provided
with field regions (103), and active device regions (105) already
formed using the well known methods including the LOCOS (local
oxidation of silicon) method or the STI (shallow trench isolation)
method. A first gate oxide layer (120) is next grown thermally over
the substrate at a temperature between about 850 to 950.degree. C.
to a thickness between about 190 to 210 angstroms (.ANG.).
Alternatively, the gate oxide can be formed by an atmospheric or
low pressure chemical vapor deposition (LPCVD) process as is well
known. A cross-sectional view of the substrate including the first
gate oxide layer is shown in FIG. 3a corresponding to the location
shown in FIG. 2a.
[0033] Next, a first polysilicon layer (poly-1) (130) (not shown as
a blanket layer) is blanket deposited over the first gate oxide
layer (120). This is accomplished through methods including but not
limited to Low Pressure Chemical Vapor Deposition (LPCVD) methods,
Chemical Vapor Deposition (CVD) methods and Physical Vapor
Deposition (PVD) sputtering methods employing suitable silicon
source materials, preferably formed through a LPCVD method
employing silane SiH.sub.4 as a silicon source material at a
temperature range between about 550 to 620.degree. C. The preferred
thickness of the poly-1 layer is between about 900 to 1100
angstroms (.ANG.). It will be noted from FIG. 3b that gate oxide
layer (120) serves the function of a control gate oxide here.
[0034] The poly-1 deposition is followed by the deposition of
silicide layer (140). As is known in the art, silicides can be
formed by either deposition of pure metal on silicon or
co-evaporation of silicon and refractory metal from two sources, or
by sputter-depositing silicide from a composite target, or by
co-sputtering or layering. The metal is usually selected from a
refractory group consisting of tungsten, titanium, tantalum,
molybdenum, and platinum and can either be deposited as a pure
metal on a silicon bearing surface, or co-evaporated with silicon.
Here, it is preferred that layer (140) is formed by co-sputtering
tungsten to a thickness between about 800 to 1500 .ANG..
[0035] A layer of oxide is then deposited over the substrate
through the decomposition of tetraethyl orthosilicate (TEOS) at a
temperature between about 600 to 650.degree. C. Plasma Enhanced
PECVD TEOS films can also be deposited at lower temperatures. It is
preferred that the decomposition temperature here is between about
300 to 400.degree. C., and that the thickness of TEOS layer (150)
is between about 1900 to 2100 .ANG..
[0036] A first photoresist layer, (not shown), is next formed and
patterned to define the control gate regions over the substrate.
Using the patterned first photoresist layer as a photoresist mask,
layers (150), (140) and (130) are then etched to form a vertical
control gate (130) disposed below tungsten silicide (WSi.sub.x)
layer (140) and TEOS layer (150) as shown in FIG. 3b. It will be
noted from FIG. 3b that the etching is continued with high
selectivity until silicon substrate is reached. Etching is
accomplished in a HDP (high-density plasma) etcher with etch recipe
comprising gases O.sub.2, HBr, Cl.sub.2 and He to etch the
WSi.sub.x and Si, while CF.sub.4, CHF.sub.3 and O.sub.2 gases are
used to etch the TEOS layer. For clarity, in the top view of the
substrate shown in FIG. 2b, control gate (130) is shown without the
overlying silicide and TEOS layers. The layered structure is better
seen in the cross-sectional view in FIG. 3b.
[0037] Next, a second gate oxide layer, this time serving as a
floating gate oxide as well as an inter-gate or inter-poly oxide
between control gate (130) and the to-be-formed floating gate (170)
shown in FIG. 3c is thermally grown to a thickness between about 70
to 90 .ANG. at a temperature between about 850 to 950.degree. C.
This is followed by forming a second blanket polysilicon (poly-2)
layer (not shown as a blanket layer in FIG. 3c) preferably using
the same LPCVD method as in forming the poly-1 layer, with silane
SiH.sub.4 as a silicon source material at a temperature range
between about 550 to 620.degree. C. However, the blanket deposition
of poly-2 is performed only to a partial depth, that is to the same
thickness as the poly-1 layer of between about 1900 to 2100 .ANG.
so that the poly-2 layer does not reach to the height of the
silicide layer nor that of the TEOS layer. The so formed
partial-depth poly-2 layer is then etched anisotropically to form a
spacer floating gate (170) as shown in FIG. 3c. A top view of
spacer (170) can also be seen in FIG. 2c. It is preferred that the
etch recipe comprises O.sub.2, HBr, Cl.sub.2 and He.
[0038] It will be apparent to those skilled in the art that the
method disclosed above enables the forming of the spacer floating
gate (170) self-aligned to the vertical control gate (130), which
is the main feature of this invention. Furthermore the etching
forms a sharp peak of poly-2 (175) which is a key aspect for
controlling the coupling ratio between the vertical control gate
and the spacer floating gate of this invention, which in turn
enhances the erasing function of the cell.
[0039] At the next step, a second photoresist layer (180) is formed
over the substrate as shown in both FIGS. 2d and 3d and patterned
to define self-aligned source (SAS) region (109). Then etching is
performed through the patterns in the second photoresist layer by
using a dry etch recipe comprising CF.sub.4 , CHF.sub.3 and
O.sub.2. It will be noted that this recipe will etch oxide only,
and not silicon. However, it is important that etching is carried
out so that not all of the oxide in region (103) is removed. It is
preferred that an oxide layer with a thickness between about 300 to
600 .ANG. remains in regions (103) that are exposed to etching as
shown in FIGS. 2d and 2e. The remaining oxide will serve as an etch
stop when poly-2 spacer is next removed.
[0040] It will be appreciated by those skilled in the art that the
sharp peak (175) of poly-2, that is, of the spacer floating gate
(170), is well protected during this step of SAS defining.
Normally, the peak (43) of prior art shown in FIG. 1a, for example,
would be damaged during the forming of source because it is not
protected by a layer of photoresist and polysilicon, as is the case
with the method disclosed here as shown in FIG. 3d. Thus, it is
another key aspect of the present invention that photoresist and
polysilicon are used as an etch-stop during the SAS etch which
removes oxide only.
[0041] Second photoresist layer (180) is removed using oxygen
plasma ashing after the defining of SAS region (109). Subsequently,
a third photoresist layer (190) is formed over the substrate and
patterned as shown in both FIGS. 2e and 3e. Of the two poly-2
spacers formed laterally adjacent to one control gate, the one on
the drain-to-be-formed side of the cell is removed by etching
through the pattern in the third photoresist layer shown in FIG.
3e. Etching is performed with high selectivity to oxide using a
recipe comprising O.sub.2, HBr, Cl.sub.2 and He. It will be noted
that this etching removes poly-2 also over the STI regions not
covered by the third photoresist layer. Further, the remaining 30
to 60 .ANG. thick second gate oxide layer over the SAS region
serves as an etch stop and protects the underlying silicon from
damage during poly-2 etching.
[0042] A fourth photoresist layer (200) is next formed and
patterned over the substrate as shown in FIG. 2f for redefining the
self-aligned source (109) shown in FIG. 3f. The SAS is next etched
to remove completely the remaining field, or isolation oxide in
regions (103) over the source area. This is followed by ion
implanting (205) the SAS with phosphorous ions at a dosage level
between about 1.times.10.sup.15 to -9.times.10.sup.15
atoms/cm.sup.2 and at an energy between about 10 to 60 KeV.
Subsequently, the photoresist layer is removed by oxygen plasma
ashing. The source implant diffusion is further increased during
annealing of the tungsten silicide at a temperature between about
800 to 900.degree. C., as shown in FIG. 3g. Drain (107) is next
formed by ion implanting the drain region with arsenic ions at a
dosage between about 1.times.10.sup.15 to 4.times.10.sup.15
atoms/cm.sup.2 and at an energy between about 10 to 60 KeV. A top
view of the substrate corresponding to these process steps are
shown in FIGS. 2g and 2h.
[0043] The forming of the split-gate flash memory cell according to
this invention is completed by depositing an interlevel dielectric
layer (ILD) to a thickness between about 10000 to 15000 .ANG., and
opening contact holes and filling them with metal (not shown)
following the present state of the art methods.
[0044] In FIG. 2h-a, programming operation of the disclosed
split-gate flash memory cell is depicted where the source voltage
V.sub.s is set at 9 volts, the drain voltage V.sub.d at 1 volt,
while the gate voltage V.sub.g is set at 2 volts. Thus, electrons
are transferred to the floating gate (170) as shown by the arrow
(210) in the same FIG. 2h-a. For the erasing operation shown in
FIG. 2h-b, on the other hand, the source and drain voltages are set
at 0 volts, while the gate voltage at 11 volts. Under this
condition, the charge on the floating gate (170) tunnel through the
intergate oxide layer (160) into control gate (130), thus reversing
the state of the floating gate of the memory cell. It will be noted
that the enhanced sharp peak (175) of floating gate (170) improves
electric field between the floating gate and the control gate and
hence promoting faster erase operation, while the spacer floating
gate self-aligned to the vertical control gate improves
programmability, decreases the variability of program, and the
self-aligned source alleviates punch-through from the source to
drain.
[0045] While the invention has been particularly shown and
described with reference to the preferred embodiments thereof, it
will be understood by those skilled in the art that various changes
in form and details may be made without departing from the spirit
and scope of the invention.
* * * * *