Kuo; Di-Son

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kuo; Di-Son.The latest application filed is for "method to increase coupling ratio of source to floating gate in split-gate flash".

Company Profile

0.47.21

Kuo; Di-Son - Hsinchu TW
Kuo, Di-Son - Fremont CA
Kuo, Di Son - Hsin-Chu TW
Kuo; Di-Son - Chu Pei TW
Kuo; Di-Son - Science-Based Industrial Park Hsin-Chu TW
Kuo; Di-Son - Hsinchu County TW
Kuo; Di-Son - Ardsley NY
Kuo; Di-Son - New York NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method to increase coupling ratio of source to floating gate in split-gate flash Grant 7,417,278 - Hsieh , et al. August 26, 2	2008-08-26
Method to increase coupling ratio of source to floating gate in split-gate flash Grant 7,001,809 - Hsieh , et al. February 21, 2	2006-02-21
Method to increase coupling ratio of source to floating gate in split-gate flash App 20050207264 - Hsieh, Chia-Ta ; et al.	2005-09-22
Split-gate memory cell, memory array incorporating same, and method of manufacture thereof App 20050045939 - Park, Eungjoon ; et al.	2005-03-03
Method with trench source to increase the coupling of source to floating gate in split gate flash Grant 6,803,625 - Hsieh , et al. October 12, 2	2004-10-12
Stacked-gate flash memory cell with folding gate and increased coupling ratio Grant 6,724,036 - Hsieh , et al. April 20, 2	2004-04-20
Method with trench source to increase the coupling of source to floating gate in split gate flash App 20040018687 - Hsieh, Chia-Ta ; et al.	2004-01-29
PIP capacitor for split-gate flash process Grant 6,674,118 - Yeh , et al. January 6, 2	2004-01-06
Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash Grant 6,667,509 - Hsieh , et al. December 23, 2	2003-12-23
Method to fabricate poly tip in split gate flash Grant 6,635,922 - Hsieh , et al. October 21, 2	2003-10-21
Method with trench source to increase the coupling of source to floating gate in split gate flash Grant 6,624,025 - Hsieh , et al. September 23, 2	2003-09-23
Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions Grant 6,583,466 - Lin , et al. June 24, 2	2003-06-24
Method with trench source to increase the coupling of source to floating gate in split gate flash App 20030077868 - Hsieh, Chia-Ta ; et al.	2003-04-24
Split gate flash cell for multiple storage Grant 6,504,206 - Sung , et al. January 7, 2	2003-01-07
Method of manufacture of vertical split gate flash memory device and device manufactured thereby App 20020151136 - Lin, Chrong Jung ; et al.	2002-10-17
Vertical split gate field effect transistor (FET) device Grant 6,465,836 - Lin , et al. October 15, 2	2002-10-15
Vertical Split Gate Field Effect Transistor (fet) Device App 20020140022 - Lin, Chrong Jung ; et al.	2002-10-03
Modified nitride spacer for solving charge retention issue in floating gate memory cell App 20020142535 - Ho, Ming-Chou ; et al.	2002-10-03
Novel split gate flash cell for multiple storage App 20020130356 - Sung, Hung-Cheng ; et al.	2002-09-19
Flash memory cell with vertically oriented channel Grant 6,437,397 - Lin , et al. August 20, 2	2002-08-20
Method to increase coupling ratio of source to floating gate in split-gate flash App 20020109181 - Hsieh, Chia-Ta ; et al.	2002-08-15
Split Gate Field Effect Transistor (fet) Device Employing Non-linear Polysilicon Floating Gate Electrode Dopant Profile App 20020098647 - Hsieh, Chia-Ta ; et al.	2002-07-25
Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof App 20020093044 - Hsieh, Chia-Ta ; et al.	2002-07-18
Modified nitride spacer for solving charge retention issue in floating gate memory cell Grant 6,417,046 - Ho , et al. July 9, 2	2002-07-09
Method of manufacture of vertical split gate flash memory device Grant 6,391,719 - Lin , et al. May 21, 2	2002-05-21
Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device Grant 6,387,757 - Chu , et al. May 14, 2	2002-05-14
Method to increase coupling ratio of source to floating gate in split-gate flash Grant 6,380,583 - Hsieh , et al. April 30, 2	2002-04-30
Method to increase coupling ratio of source to floating gate in split-gate flash Grant 6,355,527 - Lin , et al. March 12, 2	2002-03-12
Novel split-gate flash cell App 20020027241 - Sung, Hung-Cheng ; et al.	2002-03-07
Structure with protruding source in split-gate flash App 20020016039 - Hsieh, Chia-Ta ; et al.	2002-02-07
Split gate flash memory device with source line Grant 6,326,662 - Hsieh , et al. December 4, 2	2001-12-04
P-channel EEPROM and flash EEPROM devices and method of manufacture thereof App 20010029076 - Lin, Yai-Fen ; et al.	2001-10-11
PIP capacitor for split-gate flash process App 20010026973 - Yeh, Chung-Ker ; et al.	2001-10-04
Novel method for forming split-gate flash cell for salicide and self-align contact App 20010026968 - Sung, Hung-Cheng ; et al.	2001-10-04
Method to fabricate a new structure with multi-self-aligned for split-gate flash App 20010022375 - Hsieh, Chia-Ta ; et al.	2001-09-20
Method of forming split-gate flash cell for salicide and self-align contact Grant 6,284,596 - Sung , et al. September 4, 2	2001-09-04
Method of fabricating buried source to shrink chip size in memory array App 20010017387 - Hsieh, Chia-Ta ; et al.	2001-08-30
Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line and device manufactured thereby App 20010015455 - Hsieh, Chia-Ta ; et al.	2001-08-23
PIP capacitor for split-gate flash process Grant 6,277,686 - Yeh , et al. August 21, 2	2001-08-21
Method to fabricate a flash memory cell with a planar stacked gate App 20010012661 - Lin, Chong Jung ; et al.	2001-08-09
A new structure to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate App 20010012662 - Hsieh, Chia-Ta ; et al.	2001-08-09
Implant method to improve characteristics of high voltage isolation and high voltage breakdown Grant 6,251,744 - Su , et al. June 26, 2	2001-06-26
Split gate flash with step poly to improve program speed Grant 6,229,176 - Hsieh , et al. May 8, 2	2001-05-08
Forming self-align source line for memory array Grant 6,214,662 - Sung , et al. April 10, 2	2001-04-10
Method of fabricating buried source to shrink chip size in memory array Grant 6,207,515 - Hsieh , et al. March 27, 2	2001-03-27
Method to fabricate poly tip in split-gate flash Grant 6,165,845 - Hsieh , et al. December 26, 2	2000-12-26
Method to increase coupling ratio of source to floating gate in split-gate flash Grant 6,159,801 - Hsieh , et al. December 12, 2	2000-12-12
Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices Grant 6,133,096 - Su , et al. October 17, 2	2000-10-17
Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process Grant 6,130,168 - Chu , et al. October 10, 2	2000-10-10
Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak Grant 6,130,132 - Hsieh , et al. October 10, 2	2000-10-10
Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory Grant 6,127,227 - Lin , et al. October 3, 2	2000-10-03
Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell Grant 6,121,088 - Lin , et al. September 19, 2	2000-09-19
Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell Grant 6,117,732 - Chu , et al. September 12, 2	2000-09-12
Method to fabricate sharp tip of poly in split gate flash Grant 6,090,668 - Lin , et al. July 18, 2	2000-07-18
Vertical channels in split-gate flash memory cell Grant 6,078,076 - Lin , et al. June 20, 2	2000-06-20
Method of making embedded flash memory with salicide and sac structure Grant 6,074,915 - Chen , et al. June 13, 2	2000-06-13
Method of manufacture of P-channel EEprom and flash EEprom devices Grant 6,060,360 - Lin , et al. May 9, 2	2000-05-09
Stack gate flash memory cell featuring symmetric self aligned contact structures Grant 6,037,223 - Su , et al. March 14, 2	2000-03-14
Test structures for monitoring gate oxide defect densities and the plasma antenna effect Grant 6,028,324 - Su , et al. February 22, 2	2000-02-22
Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash Grant 6,017,795 - Hsieh , et al. January 25, 2	2000-01-25
Program and erase method for a split gate flash EEPROM Grant 6,005,809 - Sung , et al. December 21, 1	1999-12-21
Method of forming sharp beak of poly to improve erase speed in split-gate flash EEPROM Grant 5,970,371 - Hsieh , et al. October 19, 1	1999-10-19
Method of fabricating step poly to improve program speed in split gate flash Grant 5,879,992 - Hsieh , et al. March 9, 1	1999-03-09
Multi-level split- gate flash memory cell Grant 5,877,523 - Liang , et al. March 2, 1	1999-03-02
Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash Grant 5,858,840 - Hsieh , et al. January 12, 1	1999-01-12
Multi-level, split-gate, flash memory cell and method of manufacture thereof Grant 5,714,412 - Liang , et al. February 3, 1	1998-02-03
Electrically erasable and programmable read only memory with non-uniform dielectric thickness Grant 5,606,521 - Kuo , et al. February 25, 1	1997-02-25
Electrically erasable and programmable read only memory with trench structure Grant 5,146,426 - Mukherjee , et al. September 8, 1	1992-09-08

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