U.S. patent application number 09/768598 was filed with the patent office on 2001-07-26 for circuit chip package and fabrication method.
Invention is credited to Balch, Ernest Wayne, Burdick, William Edward JR., Douglas, Leonard Richard, Fillion, Raymond Albert, Gorczyca, Thomas Bert, Kolc, Ronald Frank, Wojnarowski, Robert John.
Application Number | 20010009779 09/768598 |
Document ID | / |
Family ID | 23627559 |
Filed Date | 2001-07-26 |
United States Patent
Application |
20010009779 |
Kind Code |
A1 |
Fillion, Raymond Albert ; et
al. |
July 26, 2001 |
Circuit chip package and fabrication method
Abstract
One method for packaging at least one circuit chip includes:
providing an interconnect layer including insulative material
having a first side and a second side, initial metallization
patterned on second side metallized portions of the second side and
not on second side non-metallized portions of the second side, at
least one substrate via extending from the first side to one of the
second side metallized portions, and at least one chip via
extending from the first side to one of the second side
non-metallized portions; positioning the at least one circuit chip
on the second side with at least one chip pad of the at least one
circuit chip being aligned with the at least one chip via; and
patterning connection metallization on selected portions of the
first side of the interconnect layer and in the vias so as to
extend to the at least one second side metallized portion and to
the at least one chip pad. In related embodiments vias are
pre-metallized and coupled to chip pads of the circuit chips by an
electrically conductive binder. Thin film passive components and
multilayer interconnections can additionally be incorporated into
the package.
Inventors: |
Fillion, Raymond Albert;
(Niskayuna, NY) ; Balch, Ernest Wayne; (Ballston
Spa, NY) ; Kolc, Ronald Frank; (Cherry Hill, NJ)
; Burdick, William Edward JR.; (Niskayuna, NY) ;
Wojnarowski, Robert John; (Ballston Lake, NY) ;
Douglas, Leonard Richard; (Burnt Hills, NY) ;
Gorczyca, Thomas Bert; (Schenectady, NY) |
Correspondence
Address: |
GENERAL ELECTRIC COMPANY
CRD PATENT DOCKET ROOM 4A59
P O BOX 8
BUILDING K 1 SALAMONE
SCHENECTADY
NY
12301
US
|
Family ID: |
23627559 |
Appl. No.: |
09/768598 |
Filed: |
January 25, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09768598 |
Jan 25, 2001 |
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09411101 |
Oct 4, 1999 |
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6242282 |
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Current U.S.
Class: |
438/106 ;
257/E21.508; 257/E23.178; 438/111 |
Current CPC
Class: |
H01L 24/19 20130101;
H01L 2924/19043 20130101; H01L 2924/181 20130101; H01L 2224/05624
20130101; H01L 2224/92144 20130101; H01L 2924/00014 20130101; H01L
2924/15311 20130101; H01L 2224/85399 20130101; H01L 21/486
20130101; H01L 2924/01006 20130101; H01L 2224/48463 20130101; H01L
2924/01013 20130101; H01L 21/4853 20130101; H01L 2924/014 20130101;
H01L 2224/13099 20130101; H01L 2924/01022 20130101; H01L 23/5389
20130101; H01L 2924/01073 20130101; H01L 2224/0401 20130101; H01L
2924/00014 20130101; H01L 2224/48463 20130101; H01L 2224/45099
20130101; H01L 2224/45015 20130101; H01L 2924/00014 20130101; H01L
2224/48463 20130101; H01L 2924/207 20130101; H01L 2924/00014
20130101; H01L 2924/00 20130101; H01L 2924/00014 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2924/12042 20130101;
H01L 2224/85399 20130101; H01L 2924/14 20130101; H01L 2224/4824
20130101; H01L 2924/181 20130101; H01L 24/11 20130101; H01L
2224/85399 20130101; H01L 2924/0103 20130101; H01L 2924/19041
20130101; H01L 2924/19042 20130101; H01L 2224/4824 20130101; H01L
2224/24227 20130101; H01L 2924/00014 20130101; H01L 2924/12042
20130101; H01L 2924/01029 20130101; H01L 2924/00014 20130101; H01L
2924/04953 20130101; H01L 2224/05624 20130101; H01L 24/48
20130101 |
Class at
Publication: |
438/106 ;
438/111 |
International
Class: |
H01L 021/44; H01L
021/48 |
Claims
1. A method for packaging at least one circuit chip comprising:
providing an interconnect layer including insulative material
having a first side and a second side, initial metallization
patterned on second side metallized portions of the second side and
not on second side non-metallized portions of the second side, at
least one substrate via extending from the first side to one of the
second side metallized portions, and at least one chip via
extending from the first side to one of the second side
non-metallized portions; positioning the at least one circuit chip
on the second side with at least one chip pad of the at least one
circuit chip being aligned with the at least one chip via; and
patterning connection metallization on selected portions of the
first side of the interconnect layer and in the vias so as to
extend to the at least one second side metallized portion and to
the at least one chip pad.
2. The method of claim 1 wherein positioning the at least one
circuit chip comprises applying a polymeric adhesive between the
second side and the at least one circuit chip.
3. The method of claim 2 further including, prior to patterning
connection metallization, removing the polymeric adhesive from a
surface of the at least one chip pad.
4. The method of claim 3 further including molding a substrate
around the at least one circuit chip.
5. The method of claim 3 further including, after removing the
polymeric adhesive from the surface of the at least one chip pad
and prior to patterning connection metallization, applying a
zincation process through the substrate and chip vias to exposed
areas of the one of the metallized portions of the second side and
the at least one chip pad.
6. The method of claim 5 wherein patterning connection
metallization includes electrolessly depositing connection
metallization.
7. The method of claim 1 wherein the at least one chip pad
comprises at least two chip pads, the at least one chip via
comprises at least two chip vias, and positioning includes using a
vision system to locally align at least two of the at least two
chip pads with at least two of the at least two chip vias.
8. A method for packaging at least one circuit chip comprising:
providing an interconnect layer including insulative material
having a first side and a second side, second side metallization
patterned on second side metallized portions of the second side and
not on second side non-metallized portions of the second side, at
least one substrate via extending from the first side to one of the
second side metallized portions, at least one chip via extending
from the first side to one of the second side non-metallized
portions, and first side metallization patterned in the at least
one substrate via and the at least one chip via and on selected
portions of the first side; positioning the at least one circuit
chip on the second side with at least one chip pad of the at least
one circuit chip being aligned with the at least one chip via; and
applying an electrically conductive binder in the at least one chip
via to electrically couple the first side metallization and the at
least one chip pad.
9. The method of claim 8 wherein the electrically conductive binder
is solder or an electrically conductive adhesive.
10. The method of claim 9 wherein positioning the at least one
circuit chip comprises applying a polymeric adhesive between the
second side and the at least one circuit chip.
11. The method of claim 10 further including, prior to applying the
electrically conductive binder, removing the polymeric adhesive
from a surface of the at least one chip pad.
12. The method of claim 11 further including molding a substrate
around the at least one circuit chip.
13. The method of claim 11 further including, after removing the
polymeric adhesive from the surface of the at least one chip pad
and prior to applying the electrically conductive binder, applying
a zincation process to the at least one chip pad.
14. The method of claim 9 wherein providing the interconnect layer
includes providing the interconnect layer with the first side
metallization including at least one patterned connection pad.
15. The method of claim 14 wherein providing the interconnect layer
includes providing a passivation layer over the first side and the
first side metallization with openings in the passivation layer
over at least portions of the first side metallization in the at
least one chip via and on the patterned connection pad.
16. The method of claim 8 wherein the at least one chip pad
comprises at least two chip pads, the at least one chip via
comprises at least two chip vias, and positioning includes using a
vision system to locally align at least two of the at least chip
pads with at least two of the at least two chip vias.
17. A method for packaging at least one circuit chip comprising:
providing an interconnect layer including insulative material
having a first side and a second side, second side metallization
patterned on second side metallized portions of the second side
with at least one thick second side metallized portion being
thicker than at least one thin second side metallized portion, at
least one substrate via extending from the first side to the at
least one thick second side metallized portion, at least one chip
via extending from the first side to the at least one thin second
side metallized portion, and first side metallization patterned in
the at least one substrate via and the at least one chip via and on
selected portions of the first side; positioning the at least one
circuit chip on the second side with at least one chip pad of the
at least one circuit chip being aligned with the at least one chip
via; removing at least part of the thin second side metallization
situated between the at least one chip via and the at least one
chip pad; and applying an electrically conductive binder in the at
least one chip via to electrically couple the first side
metallization and the at least one chip pad.
18. The method of claim 17 wherein the electrically conductive
binder is solder or an electrically conductive adhesive.
19. The method of claim 18 wherein removing the at least part of
the thin second side metallization includes etching the at least
part of the thin second side metallization.
20. The method of claim 17 further including, while removing the at
least part of the thin second side metallization, protecting the
first side metallization with a passivation layer.
21. A package for at least one circuit chip comprising: an
interconnect layer including insulative material having a first
side and a second side, second side metallization patterned on
second side metallized portions of the second side and not on
second side non-metallized portions of the second side, at least
one substrate via extending from the first side to one of the
second side metallized portions, at least one chip via extending
from the first side to one of the second side non-metallized
portions, and first side metallization patterned in the at least
one substrate via and the at least one chip via and on selected
portions of the first side, the at least one circuit chip having at
least one chip pad and being attached to the second side with the
at least one chip pad of the at least one circuit chip being
aligned with the at least one chip via; and an electrically
conductive binder in the at least one chip via electrically
coupling the first side metallization and the at least one chip
pad.
22. The package of claim 21 wherein the electrically conductive
binder is solder or an electrically conductive adhesive.
23. The package of claim 22 further including a polymeric adhesive
between the second side and the at least one circuit chip.
24. The package of claim 23 further including a substrate
surrounding the at least one circuit chip.
25. The package of claim 9 wherein the first side metallization
includes at least one patterned connection pad.
26. The package of claim 25 further including a passivation layer
over the first side and the first side metallization with openings
in the passivation layer over at least portions of the first side
metallization in the at least one chip via and on the patterned
connection pad.
27. The package of claim 21 wherein the interconnect layer further
includes a thin film resistor or capacitor.
28. A package for at least one circuit chip comprising: an
interconnect layer including insulative material having a first
side and a second side, second side metallization patterned on
second side metallized portions of the second side with at least
one thick second side metallized portion being thicker than at
least one thin second side metallized portion and with the at least
one thin second side metallized portion having at least one thin
second side metallized portion opening, at least one substrate via
extending from the first side to the at least one thick second side
metallized portion, at least one chip via extending from the first
side to the at least one thin second side metallized portion, and
first side metallization patterned in the at least one substrate
via and the at least one chip via and on selected portions of the
first side, the at least one circuit chip including at least one
chip pad and being attached to the second side with the at least
one chip pad of the at least one circuit chip being aligned with
the at least one thin second side metallized portion opening; and
an electrically conductive binder in the at least one chip via
electrically coupling the first side metallization and the at least
one chip pad.
29. The package of claim 28 wherein the electrically conductive
binder is solder or an electrically conductive adhesive.
30. The package of claim 28 wherein the interconnect layer further
includes a thin film resistor or capacitor.
Description
BACKGROUND
[0001] The invention relates generally to circuit chip packaging.
In one form of high density interconnect (HDI) circuit module, an
adhesive-coated polymer film overlay is applied over a substrate
which can support integrated circuit chips in chip wells. Via
openings are then formed to expose chip pads of the integrated
circuit chips. The polymer film provides an insulated layer upon
which is deposited a metallization pattern for interconnection of
substrate metallization and/or individual circuit chips through the
vias. Methods for performing an HDI process using overlays are
further described in Eichelberger et al., U.S. Pat. No. 4,783,695,
issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No.
4,933,042, issued Jun. 12, 1990. Generally a plurality of polymer
film overlays and metallization patterns are used.
[0002] In another form of circuit module fabrication (referred to
herein as chip on flex), as described by Cole et al., U.S. Pat. No.
5,527,741, issued Jun. 18, 1996, a method for fabricating a circuit
module includes using a flexible interconnect layer having a
metallized base insulative layer and an outer insulative layer. At
least one circuit chip having chip pads is attached to the base
insulative layer and vias are formed in the outer and base
insulative layers to expose selected portions of the base
insulative layer metallization and the chip pads. A substrate can
be molded around the attached chip or chips. A patterned outer
metallization layer is applied over the outer insulative layer
extending through selected ones of the vias to interconnect
selected ones of the chip pads and selected portions of the base
insulative layer metallization. The concept of a pre-metallized
flexible interconnect layer was extended as described by commonly
assigned Saia et al., U.S. Pat. No. 5,874,770, wherein a method for
fabricating a flexible interconnect film includes applying a
resistor layer over one or both surfaces of a dielectric film;
applying a metallization layer over the resistor layer; applying a
capacitor dielectric layer over the metallization layer; and
applying a capacitor electrode layer over the capacitor dielectric
layer. The capacitor electrode layer is patterned to form a first
capacitor electrode; the capacitor dielectric layer is patterned;
the metallization layer is patterned to form a resistor; and the
metallization layer and the resistor layer are patterned to form an
inductor and a second capacitor electrode.
[0003] The chip on flex embodiments have been used to fabricate
both single chip and multichip modules and represent a
simplification of the earlier HDI processes. A drawback remains
however due to the fact that the associated fabrication equipment
and processes are not normally found in conventional contract
component assembly facilities. For example, contract assemblers
generally do not form vias or apply and pattern metal and may not
be willing to invest in the equipment required for such steps,
particularly in light of associated waste products and
environmental regulations.
SUMMARY OF THE INVENTION
[0004] Therefore, it would be desirable to have a circuit chip
package fabrication technique that is simpler for a contract
component assembler to apply.
[0005] In one embodiment of the present invention the via formation
is eliminated while in other embodiments metallization and
patterning steps are additionally eliminated. These techniques,
which can be used for single chip or multi-chip packages, offer the
performance advantages of chip on flex with reduced equipment and
processing step requirements and with less environmental
concerns.
[0006] One method for packaging at least one circuit chip includes:
providing an interconnect layer including insulative material
having a first side and a second side, initial metallization
patterned on second side metallized portions of the second side and
not on second side non-metallized portions of the second side, at
least one substrate via extending from the first side to one of the
second side metallized portions, and at least one chip via
extending from the first side to one of the second side
non-metallized portions; positioning the at least one circuit chip
on the second side with at least one chip pad of the at least one
circuit chip being aligned with the at least one chip via; and
patterning connection metallization on selected portions of the
first side of the interconnect layer and in the vias so as to
extend to the at least one second side metallized portion and to
the at least one chip pad. In related embodiments vias are
pre-metallized and coupled to chip pads of the circuit chips by an
electrically conductive binder.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The features of the invention believed to be novel are set
forth with particularity in the appended claims. The invention
itself, however, both as to organization and method of operation,
together with further objects and advantages thereof, may best be
understood by reference to the following description taken in
conjunction with the accompanying drawings, where like numerals
represent like components, in which:
[0008] FIGS. 1-2 and 4-7 are sectional side views of stages in a
fabrication sequence according to one circuit chip packaging
embodiment of the present invention.
[0009] FIG. 3 is a partial top view of the sectional side view of
FIG. 2.
[0010] FIGS. 8-12 are sectional side views of stages in a
fabrication sequence according to another circuit chip packaging
embodiment of the present invention.
[0011] FIGS. 13-17 are sectional side views of stages in a
fabrication sequence according to yet another circuit chip packing
embodiment of the present invention.
[0012] FIGS. 18-20 are sectional side views illustrating a
multilayer interconnection fabrication process of the present
invention.
[0013] FIG. 21 is a sectional side view of an embodiment of the
present invention including a thin film resistor.
[0014] FIGS. 22-25 are sectional side views of stages in a
fabrication sequence according to another circuit chip packing
embodiment of the present invention including thin film
capacitors.
[0015] FIG. 26 is a sectional side view of an embodiment including
several circuit chips as well as a resistor and a capacitor.
DETAILED DESCRIPTION OF THE INVENTION
[0016] FIGS. 1-2 and 4-7 are sectional side views of stages in a
fabrication sequence according to one circuit chip packaging
embodiment 1 of the present invention, and FIG. 3 is a partial top
view of the sectional side view of FIG. 2. In the fabrication
sequence of FIGS. 1-7, a method for packaging at least one circuit
chip 10 includes: providing an interconnect layer 12 including
insulative material 14 having a first side 16 and a second side 18,
initial metallization 20 patterned on second side metallized
portions 22 of the second side and not on second side
non-metallized portions 24 of the second side, at least one
substrate via 26 extending from the first side to one of the second
side metallized portions, and at least one chip via 28 extending
from the first side to one of the second side non-metallized
portions (FIG. 1); positioning the at least one circuit chip on the
second side with at least one chip pad 30 of the at least one
circuit chip being aligned with the at least one chip via (FIGS.
2-3); and patterning connection metallization on selected portions
32 and 34 of the first side of the interconnect layer and in the
vias so as to extend to the at least one second side metallized
portion and to the at least one chip pad (FIGS. 6-7).
[0017] FIG. 1 is a sectional side view of interconnect layer 12.
Insulative material 14 may comprise polyimide, for example.
Metallization 20 may comprise copper and may be applied and
patterned on insulative material 14 by conventional techniques.
Vias 26 and 28 likewise may be formed by conventional techniques
such as laser ablation, for example.
[0018] FIG. 2 is a sectional side view of circuit chip 10
positioned on second side 18 of interconnect layer 12. The
positioning can be achieved, for example, by applying a polymeric
adhesive 36 between second side 18 and at least one circuit chip
10. In one embodiment, the adhesive comprises a polyetherimide, for
example.
[0019] FIG. 3 is a partial top view of FIG. 2 illustrating an
alignment embodiment. In the embodiment of FIG. 3, the at least one
chip pad 30 comprises at least two chip pads 30, the at least one
chip via 28 comprises at least two chip vias 28, and positioning
includes using a vision system 310 (in one embodiment, a machine
vision recognition system) to locally align at least two of the at
least two chip pads with at least two of the at least two chip
vias. Using at least two chip pads is useful for position and
rotation alignment purposes. In one embodiment, the two chip pads
are at opposite ends of the circuit chip to provide for more
accurate rotation alignment. In one embodiment, interconnect layer
12 comprises a material that is sufficiently transparent to permit
vision system 310 to visualize the chip pads 30 therethrough. This
embodiment is useful because a single camera can be used for
alignment purposes in contrast to embodiments requiring two or more
cameras (one for the chip pad and one for the interconnect
layer).
[0020] FIG. 4 further illustrates substrate molding material 40
formed around at least one circuit chip 10. The substrate molding
material may comprise a plastic, for example, which can be formed
by pour molding, transfer molding, injection molding or
compression, for example. Methods of molding substrates are
described, for example, in Fillion et al., U.S. Pat. No. 5,353,498.
If adhesive 36 is applied between second side 18 and circuit chip
10, then the adhesive is removed from a surface 38 of the at least
one chip pad prior to patterning connection metallization.
[0021] FIG. 5 illustrates the structure after the removal of
residual adhesive from surface 38 as well as from any areas of via
128 sidewalls. The removal can be performed by a technique such as
plasma, chemical, or laser etching, for example. Examples of
etching systems include rf-plasma etching systems, such as reactive
ion etching systems or Branson systems with oxygen gas plasmas, and
pulsed excimer laser systems operating at 308 nm or 248 nm
wavelengths.
[0022] FIGS. 6 and 7 illustrate connection metallization 42 and
patterned portions 32 and 34 respectively. In one embodiment, after
removing the polymeric adhesive from the surface of the at least
one chip pad and prior to patterning connection metallization, a
zincation process is applied through the substrate and chip vias to
exposed areas of the one of the metallized portions of the second
side and the at least one chip pad. For aluminum chip pads, the
zincation bath acts to create a chemical replacement of a thin
layer (generally less than about 0.5 micrometers) of aluminum and
aluminum oxide on the chip pads. Patterning connection
metallization can first include electrolessly depositing connection
metallization 42 which can then be patterned by conventional
techniques to form selected portions 32 and 34 of which extend to
the at least one second side metallized portion and to the at least
one chip pad. In one embodiment, the metallization comprises a
first layer of titanium coated by a second layer of copper.
Alternatives to the zincation/electroless deposition technique
include other deposition techniques such as sputtering and
electroplating, for example.
[0023] FIGS. 8-12 are sectional side views of stages in a
fabrication sequence according to another circuit chip packaging
embodiment 2 of the present invention.
[0024] In this embodiment, an interconnect layer 112 includes
insulative material 114 having a first side 116 and a second side
118, second side metallization 120 patterned on second side
metallized portions 122 of the second side and not on second side
non-metallized portions 124 of the second side, at least one
substrate via 126 extending from the first side to one of the
second side metallized portions, at least one chip via 128
extending from the first side to one of the second side
non-metallized portions, and first side metallization 132, 134, 135
patterned in the at least one substrate via and the at least one
chip via and on selected portions of the first side.
[0025] In the embodiment of FIGS. 8-12, first side metallization,
132, 134, 135 is integral to interconnect layer 112 (that is, is
patterned and part of layer 112 prior to the positioning of the at
least one circuit chip on the second side). Again, the at least one
chip pad 130 of the at least one circuit chip is aligned with the
at least one chip via.
[0026] As discussed above, a vision system can be used to locally
align at least two of the at least chip pads with at least two of
the at least two chip vias, a substrate 140 can be molded around
the at least one circuit chip, positioning the at least one circuit
chip can include applying a polymeric adhesive 136 between the
second side and the at least one circuit chip (and removed from
surface 138 as shown in FIG. 9), and after removing the polymeric
adhesive from the surface of the at least one chip pad and prior to
applying the electrically conductive binder, a zincation process
can be applied to the at least one chip pad.
[0027] FIG. 10 illustrates the electrically conductive binder 144
which is used to form the electrical connection between the first
side metallization and the chip pads. Electrically conductive
binder 144 is applied in the at least one chip via to electrically
couple the first side metallization and the at least one chip pad
and may comprise a solder or an electrically conductive adhesive,
for example. Typically, about one-quarter to about one-half of the
volume of the at least one chip via will be filled with the
conductive binder. In one embodiment, after removing the adhesive
from the surface of the at least one chip pad and prior to applying
the electrically conductive binder, a zincation process is applied
to the at least one chip pad.
[0028] FIG. 11 illustrates an embodiment wherein the interconnect
layer 312 includes first side metallization including at least one
patterned connection pad 146 and a passivation layer 148 over the
first side and the first side metallization with openings 149 in
the passivation layer over at least portions of the first side
metallization in the at least one chip via and on the patterned
connection pad. In one embodiment the passivation layer comprises a
solder mask material As shown in FIG. 12, a solder ball 150 can be
coupled to the at least one patterned connection pad. If
passivation layer 148 is present on interconnect layer 312 prior to
attachment of circuit chip 110, then the materials of passivation
layer 148 and any polymeric adhesive 136 should be carefully chosen
so that removal of residual adhesive 136 leaves passivation layer
148 substantially intact. Example materials of passivation layer
148 include siloxane dielectrics such as siloxane polyimide and
benzocyclobutene which tend "glass over" after application.
[0029] FIGS. 13-17 are sectional side views of stages in a
fabrication sequence according to yet another circuit chip packing
embodiment of the present invention. This embodiment is similar to
that of FIGS. 8-12 except that an interconnect layer 212 includes
second side metallization 220 patterned on second side metallized
portions 222 of the second side with at least one thick second side
metallized portion 278 being thicker than at least one thin second
side metallized portion 280 and at least one chip via 228 extending
to the at least one thin second side metallized portion. This
embodiment is useful for preventing adhesive 236 from entering via
228.
[0030] As shown in FIG. 14, the circuit chip 210 is positioned with
at least one chip pad 230 being aligned with the at least one chip
via. As shown in FIG. 15, at least part of the thin second side
metallization 282 situated between the at least one chip via and
the at least one chip pad is removed so that the electrically
conductive binder 244 can be applied in the at least one chip via
to electrically couple the first side metallization and the at
least one chip pad.
[0031] Removing the at least part of the thin second side
metallization may include etching. If desired, to protect the first
side metallization while removing the at least part of the thin
second side metallization, a passivation layer 301 (FIG. 15) can be
applied (either prior to or after positioning chip 210). Like the
earlier embodiments, adhesive 236 is removed from the surface of
chip pad 30 to permit contact of electrically conductive binder
244.
[0032] Without a passivation layer, depending on the composition of
the first and second side metallization layers, portions of the
first side metallization may be removed at the same time as the
second side metallization. In this situation, the first side
metallization is formed to a sufficient thickness to retain
integrity after such removal. Further, it can be useful to fill
vias 128 completely with conductive binder 244 to enhance the
connections.
[0033] FIGS. 18-20 are sectional side views illustrating a
multilayer interconnection fabrication process of the present
invention. In these embodiments, dielectric layer 152 is applied
over interconnect layer 112 and conductive binder 144 (by spray
coating, spin coating, lamination, or extrusion), vias 154 (FIG.
19) are formed, and an outer metallization 156 is patterned in vias
154.
[0034] FIG. 21 is a sectional side view of an embodiment of the
present invention including a thin film resistor, FIGS. 22-25 are
sectional side views of stages in a fabrication sequence according
to another circuit chip packing embodiment of the present invention
including thin film capacitors, and FIG. 26 is a sectional side
view of an embodiment including several circuit chips as well as a
resistor and a capacitor. The thin film components can be
fabricated on the interconnect layer either before or after the
circuit chip is positioned on second side 18 of the interconnect
layer.
[0035] Resistor 159 of FIGS. 21 and 26 comprises resistive material
158 such as tantalum nitride, for example, partially coated with
first side metallization 134 or 135. Methods for fabricating thin
film resistors are described, for example, in commonly assigned
Wojnarowski et al., U.S. Pat. Nos. 5,675,310 and 5,683,928.
[0036] Capacitor 160 of FIGS. 22-26 may include electrodes
comprising first side metallization 134 or 135 and additional
metallization 164 with a dielectric layer 162 situated
therebetween. In one embodiment the dielectric layer comprises
amorphous hydrogenated carbon (commonly referred to as DLC or
diamond like carbon). Methods for fabricating thin film capacitors
are described for example, in commonly assigned Saia et al., U.S.
Pat. No. 5,736,448. The capacitor can be coupled on the
interconnect layer prior to attachment of chip 110 or, as shown in
FIGS. 22-25, after the attachment of chip 100 through additional
dielectric layer 168. vias 170 and 172, and additional
metallization 174.
[0037] While only certain features of the invention have been
illustrated and described herein, many modifications and changes
will occur to those skilled in the art. It is, therefore, to be
understood that the appended claims are intended to cover all such
modifications and changes as fall within the true spirit of the
invention.
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