Wafer carrier with a multi-pocket configuration

Gurary , et al. December 26, 2

Patent Grant D806046

U.S. patent number D806,046 [Application Number D/587,929] was granted by the patent office on 2017-12-26 for wafer carrier with a multi-pocket configuration. This patent grant is currently assigned to Veeco Instruments Inc.. The grantee listed for this patent is Veeco Instruments Inc.. Invention is credited to Mandar Deshpande, Alexander Gurary, Aniruddh Parekh, Yuliy Rashkovsky.


United States Patent D806,046
Gurary ,   et al. December 26, 2017

Wafer carrier with a multi-pocket configuration

Claims

CLAIM We claim the ornamental design for a wafer carrier with a multi-pocket configuration, as shown and described.
Inventors: Gurary; Alexander (Bridgewater, NJ), Deshpande; Mandar (Bridgewater, NJ), Parekh; Aniruddh (New York, NY), Rashkovsky; Yuliy (Millburn, NJ)
Applicant:
Name City State Country Type

Veeco Instruments Inc.

Plainview

NY

US
Assignee: Veeco Instruments Inc. (Plainview, NY)
Family ID: 55358780
Appl. No.: D/587,929
Filed: December 16, 2016

Related U.S. Patent Documents

Application Number Filing Date Patent Number Issue Date
29524104 Apr 16, 2015 D778247

Current U.S. Class: D13/182; D23/386; D23/499
Current CPC Class: H01L21/68721 20130101; C23C16/4584 20130101; C30B25/00 20130101; H01L21/68771 20130101; H01L21/68764 20130101
Current International Class: 1303
Field of Search: ;D23/323,328,333,335,336,337,341,352,357,370,385,386,397,399,400,406,411,413,499 ;D13/182

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Primary Examiner: Rudzinski; Kevin
Assistant Examiner: Lough; Sean D
Attorney, Agent or Firm: Patterson Thuente Pedersen, P.A.

Description



FIG. 1 is a perspective view of embodiment 1 of the wafer carrier with a multi-pocket configuration according to the new design.

FIG. 2 is a top plan view of the wafer carrier with a multi-pocket configuration shown in FIG. 1.

FIG. 3 is a detail view of a portion of the wafer carrier with a multi-pocket configuration shown in FIG. 1 detailing an enlarged portion corresponding to the area indicated in FIG. 1 that includes a single pocket and surrounding region in a perspective view.

FIG. 4 is a right side view of a wafer carrier with a multi-pocket configuration according to the new design shown in FIGS. 1-3, with the left side, front, and rear views being the same as the right side view.

FIG. 5 is a bottom plan view of a wafer carrier with a multi-pocket configuration according to the new design shown in FIGS. 1-4.

FIG. 6 is a perspective view of a wafer carrier with a multi-pocket configuration according to a second embodiment of the new design.

FIG. 7 is a right side view of a wafer carrier with a multi-pocket configuration according to the new design shown in FIGS. 6-8, with the left side, front, and rear views being the same as the right side view; and,

FIG. 8 is a bottom plan view of a wafer carrier with a multi-pocket configuration according to the new design shown in FIGS. 6-8.

The broken lines, where present, in all views illustrate portions of the wafer carrier with a multi-pocket configuration that represent environment of the claimed design and form no part of the claimed design. The dash-dot lines of FIG. 1 define the area corresponding to the enlarged portion shown in FIG. 3 and form no part of the claimed design. The dash-dot and broken lines in FIG. 3 represent the edge of the enlarged portion of the design and form no part of the claimed design.

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References


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