Semiconductor manufacturing equipment

Shimada , et al. January 17, 2

Patent Grant D652395

U.S. patent number D652,395 [Application Number D/371,213] was granted by the patent office on 2012-01-17 for semiconductor manufacturing equipment. This patent grant is currently assigned to Hitachi Kokusai Electric Inc.. Invention is credited to Yukinori Aburatani, Satoshi Aizawa, Mitsuhiro Nagata, Seiyo Nakashima, Takashi Nogami, Masakazu Shimada, Shinobu Sugiura, Tomoyuki Yamada.


United States Patent D652,395
Shimada ,   et al. January 17, 2012

Semiconductor manufacturing equipment

Claims

CLAIM We claim the ornamental design for a semiconductor manufacturing equipment, as shown and described.
Inventors: Shimada; Masakazu (Toyama, JP), Nogami; Takashi (Toyama, JP), Aizawa; Satoshi (Toyama, JP), Nakashima; Seiyo (Toyama, JP), Yamada; Tomoyuki (Toyama, JP), Sugiura; Shinobu (Toyama, JP), Aburatani; Yukinori (Toyama, JP), Nagata; Mitsuhiro (Kodaira, JP)
Assignee: Hitachi Kokusai Electric Inc. (Tokyo, JP)
Appl. No.: D/371,213
Filed: November 29, 2010

Foreign Application Priority Data

Jun 1, 2010 [JP] 2010-013454
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182,184 ;118/500,719 ;250/307,310,311 ;414/217,935,936,937

References Cited [Referenced By]

U.S. Patent Documents
5810538 September 1998 Ozawa et al.
D469412 January 2003 Witte
6547660 April 2003 Suenaga et al.
6580087 June 2003 Suzuki et al.
6945746 September 2005 Yamagishi et al.
7039499 May 2006 Nasr et al.
7607879 October 2009 Hall et al.
D607424 January 2010 Hosaka et al.
2006/0120833 June 2006 Bonora et al.
2007/0098527 May 2007 Hall et al.
2008/0166208 July 2008 Lester et al.
2008/0317581 December 2008 Makino et al.
2011/0123300 May 2011 Hashimoto
2011/0236159 September 2011 Lenz
Primary Examiner: Sikder; Selina
Attorney, Agent or Firm: Stites & Harbison PLLC Marquez, Esq.; Juan Carlos A.

Description



FIG. 1 is a front, top and right side perspective view of an semiconductor manufacturing equipment showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is a right side elevational view thereof.

The broken line showing of the "semiconductor manufacturing equipment" is for the purpose of illustrating environmental structure and forms no part of the claimed design.

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