Grooves formed around a semiconductor device on a circuit board

Ohsawa , et al. April 8, 2

Patent Grant D566060

U.S. patent number D566,060 [Application Number D/240,188] was granted by the patent office on 2008-04-08 for grooves formed around a semiconductor device on a circuit board. This patent grant is currently assigned to Nitto Denko Corporation. Invention is credited to Tetsuya Ohsawa, Emiko Tani.


United States Patent D566,060
Ohsawa ,   et al. April 8, 2008

Grooves formed around a semiconductor device on a circuit board

Claims

CLAIM The ornamental design for grooves formed around a semiconductor device on a circuit board, as shown and described.
Inventors: Ohsawa; Tetsuya (Osaka, JP), Tani; Emiko (Osaka, JP)
Assignee: Nitto Denko Corporation (Osaka, JP)
Appl. No.: D/240,188
Filed: October 11, 2005

Foreign Application Priority Data

Apr 13, 2005 [JP] 2005-010991
Apr 13, 2005 [JP] 2005-010992
Apr 13, 2005 [JP] 2005-010995
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182,158-177 ;336/200 ;324/754 ;D1/106 ;D19/10 ;361/813

References Cited [Referenced By]

U.S. Patent Documents
3676748 July 1972 Kobayashi et al.
D279670 July 1985 Lukits
D288556 March 1987 Wallgren
D295401 April 1988 Klees
5008614 April 1991 Shreeve et al.
D318271 July 1991 Hasegawa et al.
D319629 September 1991 Hasegawa et al.
D374541 October 1996 Garza
5969590 October 1999 Gutierrez
6114937 September 2000 Burghartz et al.
D487430 March 2004 Asaka et al.
D510103 September 2005 Allard et al.
Foreign Patent Documents
11-8275 Jan 1999 JP

Other References

Office Action dated Nov. 4, 2005 for Japanese Application No. 2005-010995 (2 pages). cited by other .
English Translation of Japanese Publication No. 11-8275 dated Jan. 12, 1999 (16 pages). cited by other .
English translation of Office Action dated Nov. 4, 2005 for Japanese Patent Application No. 2005-010995 (1 page). cited by other.

Primary Examiner: Bui; Daniel
Assistant Examiner: Johannes; Thomas J
Attorney, Agent or Firm: Osha Liang LLP

Description



FIG. 1 shows a plan view of grooves formed around a semiconductor device on a circuit board showing our new design.

FIG. 2 shows an enlarged view of the claimed portion identified by the dot-dash line in FIG. 1; and,

FIG. 3 shows an enlarged sectional view along the line 3--3 in FIG. 2.

The special dot-dash broken line defines the boundary of the claimed design; the gray stippling indicates the surface of the groove bed; the broken lines show environmental detail for illustrative purposes only and form no part of the claimed design.

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