Semiconductor substrate with conducting pattern

Description

FIG. 1 is a top perspective view of a semi-conductor mounting device showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and

FIG. 6 is a front elevational view thereof;

FIG. 7 is a top plan view thereof; and

FIG. 8 is a bottom plan view thereof.

Claims

The ornamental design for a semiconductor substrate with conducting pattern, as shown.

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Inventors:	Hasegawa; Terutomi (Ogaki, JP), Goto; Nobumichi (Seki, JP)
Assignee:	Ibiden Co., Ltd. (Ogaki, JP)
[*] Notice:	The portion of the term of this patent subsequent to July 23, 2005 has been disclaimed.
Appl. No.:	07/181,253
Filed:	April 13, 1988

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Current U.S. Class:	D13/182
Field of Search:	;D13/12,20,99 ;361/401,403,404,405 ;357/70,72,74,80 ;174/52.4 ;437/209

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References Cited [Referenced By]

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U.S. Patent Documents

4288841	September 1981	Gogal
4338621	July 1982	Braun
4437141	March 1984	Prokop
4458291	July 1984	Yanagisawa et al.
4513355	April 1985	Shroeder et al.
4677526	June 1987	Muehling
4698663	October 1987	Sugimoto et al.

Foreign Patent Documents

	0232837		Aug 1987		EP
	0048945		Mar 1983		JP
	644662		Feb 1985		JP
	647072		Mar 1985		JP
	647074		Mar 1985		JP
	647078		Mar 1985		JP
	673983		Mar 1986		JP
	673984		Mar 1986		JP
	6739831		Mar 1986		JP
	150353		Jul 1986		JP
	0271863		Dec 1986		JP
	0035653		Feb 1987		JP

Other References

Electronic Design, p. 7, dtd 10-16-86, NCR IC Package Pictured Thereon. . Electronic Design, p. 190, dtd 10-16-86, Disc Controller Pictured Thereon. . Electronics, p. 131, dtd 8-7-86, CMOS Chip Pictured Thereon. . Electronics, p. 7, Feb. 24, 1986, by Fujitsu Microelectronics, Inc..

Primary Examiner: Lucas; Susan J.
Assistant Examiner: Sincavage; Joel
Attorney, Agent or Firm: Lorusso & Loud