Semiconductor memory element

Asaka , et al. March 9, 2

Patent Grant D487430

U.S. patent number D487,430 [Application Number D/171,752] was granted by the patent office on 2004-03-09 for semiconductor memory element. This patent grant is currently assigned to Matsushita Electric Industrial Co., Ltd.. Invention is credited to Nobuyoshi Asaka, Takashi Noda, Takao Ochi, Junichi Shinyashiki.


United States Patent D487,430
Asaka ,   et al. March 9, 2004

Semiconductor memory element

Claims

The ornamental design for a semiconductor memory element, as shown and described.
Inventors: Asaka; Nobuyoshi (Tokyo, JP), Noda; Takashi (Hyogo, JP), Ochi; Takao (Shiga-gun, JP), Shinyashiki; Junichi (Osaka, JP)
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Appl. No.: D/171,752
Filed: November 27, 2002

Foreign Application Priority Data

Jul 10, 2002 [JP] 2002-018507
Current U.S. Class: D13/182; D14/435
Current International Class: 1303
Field of Search: ;D14/432,433,434,435,436,437,438 ;D13/182 ;174/52.2 ;257/659,666,668,687,704,787 ;361/212,816,820

References Cited [Referenced By]

U.S. Patent Documents
D260091 August 1981 Mochizuki et al.
4458291 July 1984 Yanagisawa et al.
D319629 September 1991 Hasegawa et al.
5394009 February 1995 Loo
D474472 May 2003 Maekawa et al.
Foreign Patent Documents
D1136820 Mar 2002 JP
D1137203 Mar 2002 JP
Primary Examiner: Chin; Kay H.
Attorney, Agent or Firm: Brinks Hofer Gilson & Lione

Description



FIG. 1 is a top perspective view of a semiconductor memory element showing our new design;

FIG. 2 is a side elevation view thereof, the opposite side view being a mirror image of that shown;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof; and,

FIG. 5 is a front elevation view thereof, the rear elevation view being a mirror image of that shown.

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