Cover for memory chips on a circuit board

Description

FIG. 1 is a top plan view of a cover for memory chips on a circuit board showing my new design;

FIG. 2 is an inside view of the top portion, of the cover for memory chips on a circuit board;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a cross-sectional view thereof, taken along 5--5 of FIG. 1;

FIG. 6 is a front elevational view thereof;

FIG. 7 is a rear elevational view thereof;

FIG. 8 is an end elevational view thereof, the top portion is shown separately for clarity of illustration, the opposite end is a mirror image;

FIG. 9 is an end elevational view thereof;

FIG. 10 is a top perspective view thereof, on a reduced scale; and,

FIG. 11 is a cross-sectional view thereof, taken on line 11--11 of FIG. 1.

The broken line drawings of a circuit board in FIGS. 1, 4-7 and 9-11 is for illustrative purposes only and forms no part of the claimed design.

Claims

CLAIM The ornamental design for a cover for memory chips on a circuit board, as shown and described.

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Inventors:	Peddle; Charles I. (Las Vegas, NV)
Assignee:	Celetronix, Inc. (Simi Valley, CA)
Appl. No.:	D/168,585
Filed:	October 4, 2002

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Current U.S. Class:	D14/435
Current International Class:	1402
Field of Search:	;D14/432-438 ;D13/182 ;361/816,748,800

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References Cited [Referenced By]

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U.S. Patent Documents

D257723	December 1980	Stockdale
D261760	November 1981	Dlugos
D294579	March 1988	Kirpluk et al.
D296787	July 1988	Hidaka et al.
D376134	December 1996	Anton
5867371	February 1999	Denzene et al.
D432096	October 2000	Jeon et al.

Primary Examiner: Tung; M. H.
Attorney, Agent or Firm: Nichols; Steven L. Fish; Paul W. Rader, Fishman & Grauer PLLC