Electronic postal rate memory

Description

FIG. 1 is a perspective view of an electronic postal rate memory showing my new design;

FIG. 2 is a front elevational view thereof on a reduced scale;

FIG. 3 is a top plan view thereof on a reduced scale;

FIG. 4 is a bottom view thereof on a reduced scale;

FIG. 5 is a rear elevatioal view thereof on a reduced scale;

FIG. 6 is a left side elevational view thereof on a reduced scale;

FIG. 7 is a right side elevational view thereof on a reduced scale.

Claims

The ornamental design for an electronic postal rate memory, as shown and described.

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Inventors:	Dlugos; Daniel F. (Huntington, CT)
Assignee:	Pitney Bowes Inc. (Stamford, CT)
Appl. No.:	05/972,583
Filed:	December 22, 1978

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Current U.S. Class:	D14/438; D13/182
Current International Class:	D1402; D1399
Field of Search:	;339/17R,17L,45R,45M ;361/399,415 ;D13/99 ;D14/40

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References Cited [Referenced By]

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U.S. Patent Documents

3017232	January 1962	Schwab et al.
3798507	March 1974	Damon et al.
3952232	April 1976	Coules

Other References

Electronics, 2-17-77, p. 22-Circuit Board with Ejector Handle. . Electronics, 4-28-77, p. 99, top right, Memory Board. . Vero Bulletin, 6-71, Card Ejector..

Primary Examiner: Lucas; Susan J.
Attorney, Agent or Firm: Levy; Mark E. Soltow, Jr.; William D. Scribner; Albert W.