U.S. patent number D457,146 [Application Number D/142,483] was granted by the patent office on 2002-05-14 for substrate for a semiconductor element.
This patent grant is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Tadaharu Hashiguchi, Kazuhiro Yamamoto.
United States Patent |
D457,146 |
Yamamoto , et al. |
May 14, 2002 |
Substrate for a semiconductor element
Claims
The ornamental design for a substrate for a semiconductor element,
as shown and described.
Inventors: |
Yamamoto; Kazuhiro
(Ninomiya-machi, JP), Hashiguchi; Tadaharu (Yokohama,
JP) |
Assignee: |
Kabushiki Kaisha Toshiba
(Tokyo, JP)
|
Appl.
No.: |
D/142,483 |
Filed: |
May 29, 2001 |
Foreign Application Priority Data
|
|
|
|
|
Nov 29, 2000 [JP] |
|
|
2000-033958 |
|
Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182 ;174/52.1,52.4
;257/666,678,688,690,691,692,696,697,703,777,778,779,780
;361/679,728,748,761 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Shooman; Ted
Assistant Examiner: Sikder; Selina
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Description
FIG. 1 is a right side elevational view of a substrate for a
semiconductor element, showing our new design; the opposite side
being an identical image thereof;
FIG. 2 is a top plan view thereof; the opposite side being an
identical image thereof;
FIG. 3 is a front elevational view thereof; and,
FIG. 4 is a rear elevational view thereof.
* * * * *