Semiconductor

Description

FIG. 1 is a right side, top and front perspective view of a semiconductor showing our new design;

FIG. 2 is a rear elevational view thereof;

FIG. 3 is a left side view thereof;

FIG. 4 is a bottom view thereof;

FIG. 5 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 6 is a bottom view thereof;

FIG. 7 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 8 is a bottom view thereof;

FIG. 9 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 10 is a bottom view thereof;

FIG. 11 is a right side, top and front perspective view of a semiconductor showing another embodiment of our new design;

FIG. 12 is a bottom view thereof.

Claims

The ornamental design for a semiconductor, as shown and described.

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Inventors:	Mochizuki; Hidetoshi (Fuchu, JP), Otsuki; Keizo (Higashiyamato, JP), Kosaka; Hideki (Kodaira, JP), Murakami; Gen (Machida, JP)
Assignee:	Hitachi, Ltd. (Tokyo, JP)
Appl. No.:	06/006,200
Filed:	January 24, 1979

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Foreign Application Priority Data

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Jul 28, 1978 [JP]			53-31689
Jul 28, 1978 [JP]			53-31690
Jul 28, 1978 [JP]			53-31691
Jul 28, 1978 [JP]			53-31697
Jul 28, 1978 [JP]			53-31698

Current U.S. Class:	D13/182
Current International Class:	D1303
Field of Search:	;D13/12,99,40,41 ;174/52R,52PE,52S,52FP,50.5,50.52,50.56 ;357/70,73,74,80

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References Cited [Referenced By]

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U.S. Patent Documents

3208892	September 1965	Miller et al.
3436451	April 1969	Wasser
4012766	March 1977	Phillips et al.

Other References

Electronics, 3-17-1977, front cover-LSI Package (top right). . Electronics, 10-13-1977, p. 9, Semiconductor. . Electronics, 10-27-1977, p. 9, Integrated Circuit Package, (square). . Electronics, 11-24-1977, p. 145, Integrated Circuit Housing (bottom right)..

Primary Examiner: Lucas; Susan J.
Attorney, Agent or Firm: Craig and Antonelli