U.S. patent number 9,496,425 [Application Number 13/792,166] was granted by the patent office on 2016-11-15 for back-illuminated sensor with boron layer.
This patent grant is currently assigned to KLA-Tencor Corporation. The grantee listed for this patent is KLA-Tencor Corporation. Invention is credited to David L. Brown, Jehn-Huar Chern, Yung-Ho Alex Chuang, Gildardo Delgado, Ali R. Ehsani, John Fielden.
United States Patent |
9,496,425 |
Chern , et al. |
November 15, 2016 |
Back-illuminated sensor with boron layer
Abstract
An image sensor for short-wavelength light and charged particles
includes a semiconductor membrane, circuit elements formed on one
surface of the semiconductor membrane, and a pure boron layer on
the other surface of the semiconductor membrane. This image sensor
has high efficiency and good stability even under continuous use at
high flux for multiple years. The image sensor may be fabricated
using CCD (charge coupled device) or CMOS (complementary metal
oxide semiconductor) technology. The image sensor may be a
two-dimensional area sensor, or a one-dimensional array sensor. The
image sensor can be included in an electron-bombarded image sensor
and/or in an inspection system.
Inventors: |
Chern; Jehn-Huar (Santa Clara,
CA), Ehsani; Ali R. (San Ramon, CA), Delgado;
Gildardo (Livermore, CA), Brown; David L. (Los Gatos,
CA), Chuang; Yung-Ho Alex (Cupertino, CA), Fielden;
John (Los Altos, CA) |
Applicant: |
Name |
City |
State |
Country |
Type |
KLA-Tencor Corporation |
Milpitas |
CA |
US |
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Assignee: |
KLA-Tencor Corporation
(Milpitas, CA)
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Family
ID: |
49291556 |
Appl.
No.: |
13/792,166 |
Filed: |
March 10, 2013 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20130264481 A1 |
Oct 10, 2013 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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61622295 |
Apr 10, 2012 |
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61658758 |
Jun 12, 2012 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G01N
21/8806 (20130101); G01N 21/956 (20130101); H01L
27/14806 (20130101); G01N 21/9501 (20130101); H01L
31/0216 (20130101); H01L 27/1464 (20130101); H01L
27/1462 (20130101); H01L 27/14685 (20130101); H01L
27/14689 (20130101); G01N 2021/95676 (20130101) |
Current International
Class: |
G01N
21/88 (20060101); H01L 31/0216 (20140101); G01N
21/95 (20060101); G01N 21/956 (20060101); H01L
27/146 (20060101) |
Field of
Search: |
;250/358.1 |
References Cited
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|
Primary Examiner: Taningco; Marcus
Assistant Examiner: Malevic; Djura
Attorney, Agent or Firm: Bever, Hoffman & Harms, LLP
Parent Case Text
RELATED APPLICATIONS
The present application claims priority to U.S. Provisional
Application 61/622,295, entitled "BACK-ILLUMINATED CCD WITH
PURE-BORON COATING FOR EUV AND VUV APPLICATION IN MASK AND WAFER
INSPECTION" by Chern et al. and filed on Apr. 10, 2012, and to U.S.
Provisional Application 61/658,758, entitled "ELECTRON-BOMBARDED
CCD AND INSPECTION SYSTEMS USING ELECTRON-BOMBARDED CCD DETECTORS"
by Chuang et al. and filed on Jun. 12, 2012, both of which are
incorporated by reference herein.
The present application is also related to U.S. patent application
Ser. No. 13/710,315, entitled "ELECTRON-BOMBARDED CHARGE-COUPLED
DEVICE AND INSPECTION SYSTEMS USING EBCCD DETECTORS", filed by
Chuang et al. on Dec. 10, 2012, which claims priority to
Provisional Application 61/569,611 entitled "ELECTRON-BOMBARDED
CHARGE-COUPLED DEVICE AND INSPECTION SYSTEMS USING EBCCD
DETECTORS", filed by Chuang et al. on Dec. 12, 2011. The present
application is also related to U.S. Provisional Application
61/735,427, entitled "METHOD AND APPARATUS FOR HIGH SPEED
ACQUISITION OF MOVING IMAGES USING PULSED ILLUMINATION", filed by
Brown et al. on Dec. 10, 2012. All these applications are
incorporated by reference herein.
Claims
The invention claimed is:
1. An image sensor for sensing at least one of deep ultraviolet
(DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme
ultraviolet (EUV) radiation, and charged particles, the image
sensor comprising: a semiconductor membrane comprising an epitaxial
layer including opposing first and second surfaces, the
semiconductor membrane including circuit elements formed on the
first surface and a pure boron layer formed on the second
surface.
2. The image sensor of claim 1, wherein the epitaxial layer is
greater than about 20 .mu.m in thickness.
3. The image sensor of claim 2, further including a doped layer
formed in the second surface of the membrane.
4. The image sensor of claim 1, wherein the pure boron layer is
between 2 nm and 20 nm thick.
5. The image sensor of claim 1, further comprising an
anti-reflection coating deposited on the boron layer.
6. The image sensor of claim 1, further comprising a conductive
coating deposited on the boron layer to form a capping layer.
7. The image sensor of claim 1, further comprising a handling wafer
attached to the circuit elements.
8. The image sensor of claim 1, further comprising a protective
layer formed on the circuit elements.
9. The image sensor of claim 4, wherein the image sensor comprises
a charge-coupled device (CCD) or a CMOS device.
10. A method of fabricating an image sensor, the method comprising:
forming an epitaxial layer on a substrate; forming a gate layer on
the substrate; forming a circuit element layer on the gate layer;
thinning the substrate to generated a thinned substrate, the
thinned substrate exposing at least portions of the epitaxial
layer; and forming a pure boron layer on the exposed portions of
the epitaxial layer.
11. The method of claim 10, further comprising forming an
anti-reflection coating on the pure boron layer.
12. The method of claim 10, further comprising forming a conductive
layer on the pure boron layer.
13. The method of claim 10, further comprising forming a protective
layer on the circuit element layer.
14. The method of claim 10, further comprising doping at least one
exposed portion of the epitaxial layer after said thinning the
substrate and before said forming the pure boron layer.
15. A method of fabricating an image sensor, the method comprising:
forming an epitaxial layer on a substrate; forming circuit elements
on the epitaxial layer; attaching a handling wafer to the circuit
elements; thinning the substrate to expose the epitaxial layer; and
forming a pure boron layer on the exposed surface of the epitaxial
layer.
16. The method of claim 15, further comprising forming an
anti-reflection coating on the pure boron layer.
17. The method of claim 15, further comprising forming a conductive
layer on the pure boron layer.
18. An electron-bombarded image sensor comprising: an evacuated
housing; a photocathode; and an image sensor, the photocathode and
the image sensor positioned inside the evacuated housing, wherein
the image sensor comprises a semiconductor membrane having opposing
first and second surfaces, the semiconductor membrane including
circuit elements formed on the first surface of the semiconductor
membrane and a pure boron layer formed on the second surface of the
semiconductor membrane such that a portion of the boron is diffused
into the semiconductor membrane through the second surface.
19. The electron-bombarded image sensor of claim 18, wherein the
photocathode comprises a semiconductor.
20. The electron-bombarded image sensor of claim 19, wherein the
photocathode comprises GaN.
21. The electron-bombarded image sensor of claim 20, wherein the
photocathode is held at a negative voltage between 100 V and 1000 V
relative to the image sensor.
22. The electron-bombarded image sensor of claim 20, wherein the
image sensor further comprises a refractory metal coating deposited
on the surface of the boron layer.
23. A system for inspecting a sample, the system comprising: an
illumination source for illuminating the sample; image relay optics
configured to direct light outputs, reflections, or transmissions,
of the sample to a first channel image mode relay when the light
outputs correspond to the first channel, and to a second channel
image mode relay when the light outputs correspond to the second
channel; and a sensor configured to receive relay outputs of the
first channel image mode relay and the second channel image mode
relay, the sensor including an epitaxial silicon membrane, the
epitaxial silicon membrane including circuit elements formed on a
first surface of the epitaxial silicon membrane and a pure boron
layer deposited on a second surface of the epitaxial silicon
membrane, the second surface being opposite to the first
surface.
24. The system of claim 23, the image sensor further comprising two
sets of readout circuits positioned on either side of an image
region.
25. An inspection system comprising: an illumination source; optics
including an objective lens, the optics configured to direct and
focus radiation from the illumination source onto a sample; a
detector configured to receive reflected or scattered light from
the sample, wherein the optics are further configured to collect,
direct, and focus the reflected or scattered light onto the
detector, the detector including one or more image sensors, at
least one image sensor including a semiconductor membrane
comprising an epitaxial layer and including opposing first and
second surfaces, the semiconductor membrane including circuit
elements formed on the first surface of the semiconductor membrane
and a pure boron layer formed on the second surface of the
semiconductor membrane such that a portion of the boron is diffused
into the epitaxial layer through the second surface.
26. The inspection system of claim 25, wherein the image sensor
further comprises an electron bombarded image sensor.
Description
BACKGROUND OF THE DISCLOSURE
1. Field of the Disclosure
The present application relates to image sensors suitable for
sensing radiation in deep UV (DUV), vacuum UV (VUV), and extreme UV
(EUV) wavelength, and to methods for making such image sensors.
Some embodiments of the sensors are suitable for sensing electrons
and other charged particles. All of the sensors are suitable for
use in photomask, reticle, or wafer inspection systems.
2. Related Art
The integrated circuit industry requires inspection tools with
increasingly higher resolution to resolve ever smaller features of
integrated circuits, photomasks, reticles, solar cells, charge
coupled devices etc., as well as detect defects whose sizes are of
the order of, or smaller than, those feature sizes.
Inspection systems operating at short wavelengths, e.g. wavelengths
shorter than about 250 nm, can provide such resolution in many
cases. In other cases, electrons or other charged particles, such
as helium (He) nuclei (i.e. alpha particles) may be used.
Specifically, for photomask or reticle inspection, it is desirable
to inspect using a wavelength identical, or close, to the
wavelength that will be used for lithography, i.e. close to 193.4
nm for current generation lithography and close to 13.5 nm for
future EUV lithography, as the phase-shifts of the inspection light
caused by the patterns will identical or very similar to those
caused during lithography. For inspecting semiconductor patterned
wafers, inspection systems operating over a relatively broad range
of wavelengths, such as a wavelength range that includes
wavelengths in the near UV, DUV, and/or VUV ranges, can be
advantageous because a broad range of wavelengths can reduce the
sensitivity to small changes in layer thicknesses or pattern
dimensions that can cause large changes in reflectivity at an
individual wavelength.
In order to detect small defects or particles on photomasks,
reticles, and semiconductor wafers, high signal-to-noise ratios are
required. High photon or particle flux densities are required to
ensure high signal-to-noise ratios when inspecting at high speed
because statistical fluctuations in the numbers of photons detected
(Poisson noise) is a fundamental limit on the signal-to-noise
ratio. In many cases, approximately 100,000 or more photons per
pixel are needed. Because inspection systems are typically in use
24 hours per day with only short stoppages, the detectors are
exposed to large doses of radiation after only a few months of
operation.
A photon with a vacuum wavelength of 250 nm has energy of
approximately 5 eV. The bandgap of silicon dioxide is about 10 eV.
Although it would appear that such wavelength photons cannot be
absorbed by silicon dioxide, silicon dioxide as grown on a silicon
surface must have some dangling bonds at the interface with the
silicon because the silicon dioxide structure cannot perfectly
match that of the silicon crystal. Furthermore, because the single
dioxide is amorphous, there are likely also some dangling bonds
within the material. In practice, there will be a non-negligible
density of defects and impurities within the oxide, as well as at
the interface to underlying semiconductor, that can absorb photons
with deep UV wavelengths, particularly those shorter than about 250
nm in wavelength. Furthermore, under high radiation flux density,
two high-energy photons may arrive near the same location within a
very short time interval (nanoseconds or picoseconds), which can
lead to electrons being excited to the conduction band of the
silicon dioxide by two absorption events in rapid succession or by
two-photon absorption. EUV photons have very high energies (13.5 nm
in wavelength corresponds to photon energy close to 92 eV) and are
capable of breaking silicon-oxygen bonds as well as strongly
interacting with defects and contaminants in the oxide. Electron
and charged-particle detectors typically have to detect electrons
or charged particles with energies of a few hundred eV or higher.
Energies greater than 10 eV can readily break silicon-oxygen
bonds.
As indicated above, high-energy photons and particles can break
bonds and ionize atoms in a silicon dioxide layer. Because silicon
dioxide is a good insulator, free electrons created in the silicon
dioxide may have lifetimes of ms or longer before recombining. Some
of these electrons may migrate into the semiconductor material.
These electrons create electric fields within the silicon dioxide
and between the silicon dioxide and semiconductor. These electric
fields can cause electrons created in the semiconductor by
absorption of photons to migrate to the surface of the
semiconductor and recombine, thereby resulting in lost signal and
reduced detector quantum efficiency. Near continuous use of the
instrument means that there may be little, or no, time for recovery
of the detector, as new free charges are created as fast as, or
faster than, they can recombine.
High-energy particles and photons can also cause irreversible
changes to the silicon dioxide. Such changes can include
reconfiguration of the bonding of atoms or migration of small atoms
within the silicon dioxide. At normal operating temperatures of the
detector, which are typically in a range from around room
temperature to about 50.degree. C., these changes will not recover.
In particular, it is known that conventional silicon photodiodes
used as EUV detectors degrade in efficiency with use.
The silicon dioxide layer on the surface of semiconductor detectors
significantly reduces the efficiency of those detectors for
low-energy (less than about 2 kV) electrons. Some low-energy
electrons are absorbed by the silicon dioxide, thereby causing the
silicon dioxide to charge up and deflect subsequent arriving
electrons. Because a native oxide will always form on an exposed
silicon surface, silicon detectors necessarily must have some oxide
on their surface. Growing or depositing an alternative dielectric
material (instead of the oxide) on the surface of the semiconductor
results in a much higher density of defect states at the
semiconductor to silicon dioxide interface. These defects reduce
the quantum efficiency of the detector, especially for photons or
charged particles absorbed close to the surface of the
semiconductor.
An additional cause of degradation of EUV sensors is that, in a EUV
system, a thin layer of carbon builds up over time on any surface
exposed to EUV radiation, including the surface of the image
sensors and optical elements. This carbon layer, as it becomes
thicker, absorbs EUV radiation and reduces the sensitivity of the
sensor, as well as reducing the reflectivity of optical elements in
the light path. In a EUV system, all surfaces exposed to EUV are
periodically cleaned to remove the carbon. This cleaning is usually
performed with activated hydrogen (a mixture of atomic hydrogen and
hydrogen radicals), which is very effective at removing carbon.
However hydrogen radicals affect the oxide on the surface of
silicon detectors and can also cause degradation of the performance
of those sensors.
Diode detectors suitable for detecting EUV and/or electrons are
known in the art. Exemplary diode detectors are described in U.S.
Pat. No. 8,138,485 issued to Nihtianov on Mar. 20, 2012, U.S. Pat.
No. 7,586,108 issued to Nihtianov on Sep. 8, 2009, US Published
Application 2012/0268722 published on Oct. 25, 2012 (filed by
Nihtianov), and US Published Application 2011/0169116 published on
Jul. 14, 2011 (filed by Nanver). These diode detectors include a
thin (1 nm to 20 nm) layer of boron directly on the silicon
surface. US Published Application 2011/0169116 further describes an
open mesh of a metallic conductor on the surface of such a
detector.
These prior-art detectors have contacts formed on the top (light or
electron-incident) surface. A disadvantage of having contacts and
conductors formed on the illuminated surface is that it is not
possible to create a detector with a large number (thousands or
millions) of detector elements (pixels) while maintaining high
detector efficiency. Each detector element requires multiple
control signals, which are typically shared with other detector
elements. For full-well capacities of 100,000 electrons or more,
detector element dimensions may typically be in the range of about
10 .mu.m to 20 .mu.m. It is not possible to make hundreds or
thousands of interconnects that connect these control signals to
one another and to drive circuits without covering a substantial
fraction of the area of the surface. Because DUV, VUV, and EUV
photons and low-energy particles will not penetrate through layers
of conductors such as metals and poly-silicon, the area covered by
these conductors will have low, or no, sensitivity.
Therefore, a need arises for an image sensor capable of detecting
high-energy photons or charged particles yet overcoming the above
disadvantages.
SUMMARY OF THE DISCLOSURE
Methods of fabricating image sensors with high-quantum-efficiency
for imaging DUV, VUV, and/or EUV radiation and/or charged particles
are described. Image sensors fabricated according to these methods
are capable of long-life operation under high fluxes of DUV, VUV,
EUV, and/or charged particles. These methods include process steps
to form light sensitive active and/or passive circuit elements in a
layer on a semiconductor (preferably silicon) wafer.
An exemplary method of fabricating an image sensor includes forming
an epitaxial layer on a substrate, forming a gate layer on the
epitaxial layer, the gate layer comprising one or more layers of
dielectric materials such as silicon dioxide and silicon nitride,
forming circuit elements on the gate layer comprising poly-silicon
and dielectric materials, but no metal films or metal
interconnects, thinning the substrate to generate a thinned
substrate (also referred to herein as a membrane) and expose at
least portions of the epitaxial layer, and forming a pure boron
layer directly on the exposed portions of the epitaxial layer. As
used herein, the phrase "circuit elements" refers to light
sensitive devices such as charge-coupled devices and photodiodes,
other semiconductor devices such as transistors, diodes, resistors
and capacitors, and electrical interconnections (often called
interconnects) between them. In this first exemplary embodiment,
the circuit elements formed prior to boron deposition do not
include any metal interconnects. These circuit elements are formed
using standard semiconductor manufacturing processes including, but
not limited to, photolithography, deposition, etching, ion
implantation and annealing. Thinning the sample (e.g. a wafer) can
be performed using chemical etching and/or polishing. Notably, this
thinning can increase the sensitivity of the image sensor to light
impinging the back surface. An anti-reflection coating or a
conductive coating can be formed on the boron layer. This
anti-reflection or conductive coating may increase the transmission
of wavelengths of interest into the image sensor and/or protect the
image sensor. In one embodiment, at least one exposed portion of
the epitaxial layer can be doped after thinning the substrate and
before forming the boron layer. After the boron layer has been
deposited on the back surface, the circuits on the front surface
can be completed, including forming metal interconnects.
Another method of fabricating an image sensor includes forming an
epitaxial layer on a substrate, then forming circuit elements on
the epitaxial layer. This step may include forming metal
interconnects. Either a handling wafer or a protective layer can be
formed on the circuit elements. The substrate is then thinned to
expose, at least part of, the epitaxial layer. As indicated above,
this thinning can increase the sensitivity of the image sensor to
light impinging on the back surface. A pure boron layer is formed
on the surface of the epitaxial layer exposed in the thinning
process. An anti-reflection coating or a conductive coating can be
formed on the boron layer. This anti-reflection or conductive
coating may increase the transmission of wavelengths of interest
into the image sensor and/or protect the image sensor.
Image sensors with high-quantum-efficiency and long-life operation
for DUV, VUV, and/or EUV radiation and/or charged particles are
described. These image sensors are thinned from the back-side so
that they are highly sensitive to radiation or charged particles
impinging on the back-side of the image sensors (wherein these
image sensors are back-illuminated). Deposited directly on the back
surface of the epitaxial layer is a thin (e.g. between about 2 nm
and about 20 nm thick) layer high-purity amorphous boron. In some
embodiments, an additional layer of material may be coated on the
boron. The thickness and material of each layer may be chosen to
increase the transmission of wavelength of interest into the image
sensor and/or to protect the image sensor.
The image sensors described herein may be fabricated using CCD
(charge coupled device) or CMOS (complementary metal oxide
semiconductor) technology. The image sensors may be two-dimensional
area sensors, or one dimensional array sensors.
An electron-bombarded image sensor is described herein. The
electron-bombarded image sensor includes a photocathode that emits
electrons when it absorbs a photon or charged particle. Emitted
electrons are accelerated towards a solid-state image sensor, such
as a CCD image sensor or a CMOS image sensor. The image sensor
includes a pure boron layer deposited directly on a thinned
substrate, as described above, thereby ensuring that almost all the
electrons striking it penetrate into the device. This high level of
penetration enables the electron-bombarded image sensor to use a
low accelerating voltage (such as an accelerating voltage that is
less than 2 kV, or less than 1 kV), thereby resulting in better
image resolution and longer sensor lifetime.
A system for inspecting a sample is also described. This system
includes an illumination source and two illumination relays for
illuminating the sample. Image relay optics are configured to
direct light outputs, i.e. reflections and/or transmissions, of the
sample to a first channel image mode relay when the light outputs
correspond to the first channel illumination relay, and to a second
channel image mode relay when the light outputs correspond to the
second channel illumination relay. A sensor is configured to
receive relay outputs of the first channel image mode relay and the
second channel image mode relay. The sensor includes a
semiconductor membrane, in which circuit elements are formed on one
surface of the membrane and a boron layer is deposited on the
opposite surface of the membrane. In this configuration, the sensor
is capable of simultaneously detecting two images of the same
sample.
An exemplary inspection system is also described. This inspection
system includes an illumination source, optics, and a detector. The
optics are configured to direct and focus radiation from the
illumination source onto a sample. The detector is configured to
receive reflected or scattered light from the sample, wherein the
optics are further configured to collect, direct, and focus the
reflected or scattered light onto the detector. The detector can
include one or more image sensors. At least one image sensor
includes a semiconductor membrane, wherein the semiconductor
membrane includes circuit elements formed on one surface of the
semiconductor membrane and a boron layer is deposited on the
opposite surface of the semiconductor membrane.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an exemplary method of fabricating an image
sensor.
FIG. 2 illustrates an alternative exemplary technique 120 for
fabricating an image sensor.
FIGS. 3A-3G illustrate exemplary cross-sections of a wafer
subjected to the method described in reference to FIG. 1.
FIGS. 4A-4G illustrate exemplary cross-sections of a wafer
subjected to the method described in reference to FIG. 2.
FIG. 5 illustrates an exemplary electron-bombarded image sensor
system.
FIG. 6 illustrates exemplary driving voltages for the clock signals
of any of the image sensors described herein that incorporate
CCDs.
FIG. 7A illustrates an exemplary split-readout image sensor
including two sets of readout circuits.
FIG. 7B illustrates a plurality of CCD drivers driving sets of gate
electrodes, each set having multiple gates.
FIG. 8 shows a reticle, photomask or wafer inspection system that
can simultaneously detect two channels of image or signal on one
sensor.
FIG. 9 illustrates an exemplary detector assembly incorporating an
image sensor, a silicon interposer, and other electronics.
FIG. 10 illustrates an exemplary sensor module array including a
plurality of time delay integration (TDI) sensor modules.
FIG. 11 illustrates an exemplary inspection system configured to
measure a sample such as a wafer, reticle, or photomask.
DETAILED DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an exemplary technique 100 for fabricating an
image sensor. In step 101, circuit elements can be created using
standard semiconductor processing steps, such as lithography,
deposition, ion implantation, annealing, and etching. CCD and/or
CMOS sensor elements and devices may also be created during step
101. These circuit elements are created in an epitaxial layer on
the front surface of the wafer and therefore are also called
front-side circuit elements. In preferred embodiments, the
epitaxial (epi) layer is about 20 .mu.m to 40 .mu.m thick. In
preferred embodiments, both the epi layer and the substrate are
doped with p-type dopants (such as boron), but the epi layer has a
much lower dopant concentration (referred to below and in the
figures as p- doping) than the bulk wafer (referred to below and in
the figures as p+ doping). Typically the epitaxial layer
resistivity will be about 10 to 100 .OMEGA.cm, and the substrate
resistivity will be less than about 0.01 .OMEGA.cm. Although
poly-silicon interconnects may be formed in step 101, metal
interconnects are generally not because metals will be damaged in
subsequent high-temperature processing steps.
In step 103, the active sensor areas or even the whole wafer may be
thinned from the backside. This thinning typically includes a
combination of polishing and etching to expose the epi layer. In
one embodiment, the wafer is polished from the backside until the
wafer is about 200 .mu.m to 300 .mu.m thick. Then, the front
surface and the frame areas around the active sensor areas are
protected with a material, such as photoresist or other suitable
material. At this point, a chemical etchant is used to etch away
the bulk wafer over the active sensor area, thereby exposing the
active sensor area. Because the bulk wafer has a much higher dopant
concentration and defect density than the epi layer, the etch rate
of the bulk semiconductor material is much higher than that of the
epi layer. The etch process slows down when it reaches the epi
layer, thereby resulting in a uniform thickness membrane area. In
another embodiment, the image sensor wafer is bonded to a handle
wafer, which might be made of quartz, silicon, sapphire or other
material. Then, a polishing process is used to polish the whole
wafer until only the epi layer remains.
In step 105, a protective layer can be deposited on the front-side
surface to protect the front-side circuit elements during steps
107-111. In particular, any exposed silicon or poly-silicon on the
front-side surface must be protected as boron tends to
preferentially deposit on silicon. In some embodiments, step 105
may be performed prior to step 103 so that the protective layer can
provide additional protection for the front-side surface during the
back-thinning process (step 103). In some embodiments, the
protective layer may comprise a silicon nitride layer deposited,
e.g., using plasma-enhanced CVD deposition.
In step 107, the back-side surface can be cleaned and prepared for
boron deposition. During this cleaning, native oxide and any
contaminants, including organics and metals, should be removed from
the back-side surface. In one preferred embodiment, the cleaning
can be performed using a dilute HF solution or an RCA clean process
(which is a well-known set of wafer cleaning steps including the
removal of organic contaminants, the thin oxide layer, and ionic
contamination). After cleaning and during preparation, the wafer is
preferably dried using the Marangoni drying technique (surface
tension based drying technology) or a similar technique to leave
the surface dry and free of water marks. In preferred embodiments,
the wafer is protected in a controlled atmosphere during steps
107-109 (using, e.g. dry nitrogen) to minimize native oxide
regrowth.
In step 109, the wafer can be held at a high-temperature for a few
minutes in a reducing environment, such as a dilute hydrogen gas or
a low-pressure hydrogen gas. In preferred embodiments, the wafer
can be held at a temperature of approximately 800.degree. C. for
about 4 minutes. This high temperature can remove any native oxide
layer that might have regrown following step 107.
In step 111, an amorphous layer of pure boron is deposited on the
back-side of the back-side surface. In one preferred embodiment,
this deposition can be performed using a mixture of diborane and
hydrogen gases at a temperature of about 700-800.degree. C. to
create a high-purity amorphous boron layer. The thickness of the
boron layer depends on the intended application for the sensor.
Typically, the boron layer thickness is between about 2 nm and 20
nm. The minimum thinness is generally limited by the need for a
pinhole-free uniform film. The maximum thickness generally depends
on the absorption of the photons or charged particles of interest
by the boron. Note that steps 109 and 111 can be performed in the
same process tool and, preferably, in the same process chamber,
thereby ensuring that steps 109 and 111 can be performed in quick
succession with no possibility of surface contamination or oxide
growth between the steps. More details on boron deposition can be
found in "Chemical vapor deposition of a-boron layers on silicon
for controlled nanometer-deep p.sup.+-n junction formation,"
Sarubbi et al., J. Electron. Material, vol. 39, pp. 162-173,
2010.
The purity and lack of pinholes in the boron layer are critical to
the sensitivity and lifetime of the image sensors disclosed herein.
If any native oxide film is not removed from the epi layer surface
before deposition of the boron, then that native oxide will be
affected by DUV, VUV and EUV photons and by charged particles and
will cause a degradation of sensor performance with use. Even if
all the native oxide is removed prior to the boron deposition, if
there are pinholes in the boron layer, then, after processing,
oxygen will be able to reach the epi layer through those pinholes
and may oxidize the surface of that layer.
In some embodiments, other layers can also be deposited on top of
the boron layer during, or immediately following, step 111. These
other layers may include anti-reflection coatings comprised of one
or more materials, such as silicon dioxide, silicon nitride,
magnesium fluoride, and lithium fluoride. These other layers may
also include a protective layer comprising a thin (few nm) layer of
a refractory metal. Even though the anti-reflection coating may be
affected by DUV, VUV or EUV radiation, the presence of the boron
layer between the anti-reflection coating and the epi layer shields
the epi layer from charges and traps in the anti-reflection coating
and ensures that the sensitivity of the image sensor does not
significantly degrade.
In step 113, the front-side protective layer can be removed or
patterned to prepare for fabrication of interconnects on the front
surface. In some embodiments, this removal/patterning may include
etching of the front-side surface in dilute HF, because the boron
layer is relatively impervious to dilute HF.
In step 115, interconnects on the front surface can be patterned
and fabricated. These interconnects may be formed by Al, Cu, or
another metal. After interconnect fabrication is complete, a
passivation layer may be deposited on the front-side surface to
protect these interconnects.
In step 117, the completed circuit elements can be packaged. The
package may include flip-chip bonding or wire bonding of a chip to
a substrate. The package may include a window that transmits
wavelengths of interest, or may comprise a flange or seal for
interface to a vacuum seal. In electron-bombarded image sensor
embodiments, the package may include other components such as a
photocathode as well as a sealed, evacuated tube.
FIG. 2 illustrates an alternative exemplary technique 200 for
fabricating an image sensor. In this embodiment, the circuit
elements can be created in step 201 using standard semiconductor
processing steps including lithography, deposition, ion
implantation, annealing, and etching. In one embodiment, CCD and/or
CMOS sensor elements and devices may also be created in step 201.
These circuit elements are created in an epi layer on the
front-side surface of the wafer. In preferred embodiments, the epi
layer is about 20 .mu.m to 40 .mu.m thick. The epi layer has a low
dopant concentration (p-). In one embodiment, interconnects, such
as metal interconnects, can also be created in step 201.
In step 203, the front-side surface of the wafer can be protected.
This protection may include depositing one or more protective
layers on top of the circuit elements formed during step 201. This
protection may also, or instead, include attaching the wafer to a
handling wafer, such as a silicon wafer, a quartz wafer, or a wafer
made of other material.
Step 205 involves thinning the wafer from the back-side so as to
expose the epitaxial layer in, at least, the active sensor areas.
This step may involve polishing, etching, or both. In some
embodiments, the entire wafer is back-thinned. In other
embodiments, only the active sensor areas are thinned all the way
to the epitaxial layer.
Step 207 includes cleaning and preparing the back-side surface
prior to the boron deposition. During this cleaning, the native
oxide and any contaminants, including organics and metals, should
be removed from the back-side surface. In one embodiment, this
cleaning can be performed using a dilute HF solution or using an
RCA clean process. After cleaning and during preparation, the wafer
can be dried using the Marangoni drying technique or a similar
technique to leave the surface dry and free of water marks.
In step 209, the wafer can be transported to a deposition tool in a
protective environment, thereby allowing the wafer to be protected
during step 211. In one embodiment, for example, the protective
environment is a dry nitrogen atmosphere, which minimizes native
oxide regrowth. The time spent to perform step 209 should be kept
to a minimum, preferably no more than about five minutes.
In step 211, boron is deposited on the back-side surface of the
wafer. In one preferred embodiment, this deposition can be done
using a mixture of diborane and hydrogen gases at a temperature of
about 400-450.degree. C., thereby creating a high-purity amorphous
boron layer. The thickness of the deposited boron layer depends on
the intended application for the sensor. Typically, the boron layer
thickness will be between about 2 nm and 10 nm. The minimum
thickness is set by the need for a pinhole-free uniform film,
whereas the maximum thickness depends on the absorption of the
photons or charged particles of interest by the boron, as well as
the maximum length of time that the wafer can be kept at the
elevated temperature when there are metal interconnects on the
front-side.
In some embodiments, other layers may be deposited on the boron
layer in step 211. These other layers may include anti-reflection
coatings comprised of one or more materials such as silicon
dioxide, silicon nitride, magnesium fluoride and lithium fluoride.
These other layers may also include a protective layer comprising a
thin layer of a refractory metal. In some embodiments, this
refractory metal layer thickness may be between approximately 1 nm
and approximately 10 nm.
In one embodiment, the protective front-side layer may be removed
in step 213. In another embodiment, in step 213, holes or vias can
be opened in the protective front-side layer or through-silicon
vias around the edges of the device can be exposed, thereby
allowing connection to the circuit structures.
In step 215, the resulting structure may be packed in a suitable
package. The packing step may comprise flip-chip bonding or wire
bonding of the device to the substrate. The package may include a
window that transmits wavelengths of interest, or may comprise a
flange or seal for interface to a vacuum seal. In the
electron-bombarded image sensor embodiments, the package may
include other components such as the photocathode, and may comprise
a sealed, evacuated tube.
FIGS. 3A-3F illustrate exemplary cross-sections of a wafer
subjected to method 100 (FIG. 1). FIG. 3A illustrates an epitaxial
(epi) layer 302 being formed on the front side of a substrate 301.
In one embodiment, substrate 301 is a p+ (i.e. highly p doped)
substrate, and epi layer 302 is a p- epi layer (i.e. a layer with a
low concentration of p dopant). FIG. 3B illustrates a gate oxide
layer 303 being formed on epi layer 302, a silicon nitride
(Si.sub.3N.sub.4) gate layer 304 being formed on gate oxide layer
303, and front-side circuit elements 305 being formed on gate layer
304 (step 101). Note that depending on the type of image sensor
technology, the gate dielectric may comprise one, two, or three
layers. Forming the front-side circuit elements includes implanting
or doping portions of the front side of the epi layer and may
involve patterning the gate layer. FIG. 3C illustrates substrate
301 being thinned at its back-side surface, at least in certain
areas, to form thinned substrate 301A (step 103), and a protective
layer 305A being formed on front-side circuit elements 305 (step
105). FIG. 3D illustrates an optional doped layer 302A that may be
formed in a portion of epi layer 302 exposed by thinned substrate
301A. This doping may be formed by ion-implantation followed by
thermal activation, by plasma doping, by plasma assisted doping or
similar techniques. In one embodiment, this doping can be performed
during step 107 as part of the back-side surface preparation and
before high-temperature surface treatment in step 109. FIG. 3E
illustrates a pure boron layer 306 being formed on thinned
substrate 301A and exposed epi layer 302 (step 111). Since some of
the boron diffuses a few nm into the epi layer, some embodiments do
not need to include the separately doped layer 303A. FIG. 3F
illustrates that after protective layer 305A is removed or opened
(step 113), front-side metal (i.e. interconnect) 307 can be formed
on front-side circuit elements 305. FIG. 3G illustrates one
optional embodiment in which a capping layer 308 can be formed on
boron layer 306. Capping layer 308 can be formed any time after
step 111 (depositing the boron layer), but before step 117
(packaging).
FIGS. 4A-4G illustrate exemplary cross-sections of a wafer
subjected to method 120 (FIG. 1B). FIG. 4A illustrates an epitaxial
(epi) layer 402 being formed on the front side of a substrate 401.
In one embodiment, substrate 401 is a p+ substrate, and epi layer
402 is a p- epi layer. In one embodiment, the substrate is an SOI
(silicon-on-insulator) wafer with a buried oxide layer 402A between
substrate 401 and epi layer 402. SOI wafers are commercially
available from Soitec (Bernin, France) and other suppliers. In
other embodiments, the epi layer is grown directly on the substrate
401 without any buried oxide layer 402A. FIG. 4B illustrates
various circuit elements 403 including interconnects that can be
formed on the epi layer (step 121) (note that the epi layer is
shown, but not labeled so as not to overly complicate the
drawings). Because the interconnects are formed on the wafer prior
to back thinning all the way to the epi layer, these interconnects
can be formed using normal sub-micron CMOS processing techniques
and may include multiple layers of high density metal
interconnects. In some embodiments, multiple through-silicon vias
(TSV) 403A are created around one, or more, edges of the image
sensor array in order to allow connection to the circuit elements
403. FIG. 4C illustrates a handling wafer 404 attached to the top
of the circuit elements 403 (step 123). Note that the
through-silicon vias are shown, but not labeled so as not to overly
complicate the drawings. In other embodiments, a protective layer
can be used instead of handling wafer 404. FIG. 4D illustrates the
wafer after substrate 401 is back-thinned to epi layer 402. In one
embodiment, this back-thinning exposes buried oxide layer 402A.
FIG. 4E illustrates the wafer after a cleaning and preparation of
the back-side surface (step 127), which may result in etched oxide
402B being patterned so as to protect TSVs 403A while exposing the
epi layer in the image sensor array areas. FIG. 4F illustrates a
pure boron layer 406 after being formed on the back-side surface of
the epi layer 402 (step 131). In some embodiments, an
anti-reflection coating or metal coating or capping layer (not
shown) may be deposited on top of the pure boron layer. FIG. 4G
illustrates the wafer after etched oxide 402B is removed and
replaced with metal pad 407 so as to allow electrical connection to
the TSV 403A (step 131).
FIG. 5 illustrates an exemplary electron-bombarded image sensor
system 501. In this embodiment, the whole assembly can be contained
in a sealed tube 505 (e.g. substantially similar to the sealed tube
of standard image intensifier and electron-bombarded CCD (EBCCD)
devices). A top surface 507 of the tube 505 can include a window
that is transparent at the wavelengths of interest. For UV
sensitive electron-bombarded image sensors, this window preferably
comprises a very pure grade of quartz, fused silica or alumina
(sapphire). In some preferred embodiments, the outside surface of
the window is coated with a UV anti-reflection coating. Such a
coating might comprise a single layer of a low index material such
as MgF.sub.2, or might comprise a multi-layer coating.
Coated on the inside surface of the window, or placed immediately
adjacent to that inside surface, is a photocathode 504. The
photocathode material may be substantially similar to any
photocathode material known in the art for use in photomultiplier,
image intensifier, or prior-art EBCCD detectors. In preferred
embodiments, the photocathode may comprise one or more alkali
metals such as cesium, and/or may comprise a semiconductor such
GaN, GaAs, or silicon. Photocathode 504 can be held at a negative
voltage 503 relative to a solid-state image sensor 502, which is
positioned near the bottom surface of sealed tube 505. In some
embodiments, negative voltage 503 may be approximately 500 V; in
other embodiments, it may be a few hundred volts or approximately
1000 V. In preferred embodiments, negative voltage 503 is between
100 V and 1500 V.
Solid-state image sensor 502 can be a thinned CCD or CMOS image
sensor oriented so that the electrons impinge first on its
back-side surface. The back-side of solid-state image sensor 502
includes a layer of boron deposited directly on the epi layer of
the image array as described above. In some embodiments, a thin
(few nm) layer of a conductive material, such as a refractory
metal, is deposited on the boron layer to prevent charge-up of the
sensor surface. A refractory metal such as titanium, tungsten,
tantalum, rhodium, ruthenium, vanadium or chromium, has advantages
compared with non-refractory metals because refractory metals'
hardness makes them resistant to sputtering by the electrons, and
they are relatively resistant to oxidation at room temperature. In
some embodiments, solid-state image sensor 502 is a time-delay
integration (TDI) CCD. In some embodiments, solid-state image
sensor 502 comprises a linear array of electron-sensitive elements.
In other embodiments, solid-state image sensor 502 comprises a
two-dimensional array of electron sensitive elements. In some
preferred embodiments, solid-state image sensor 502 is held close
to ground potential (shown).
When light 510 is incident on the electron-bombarded image sensor
system 501, one or more photoelectrons 520 are emitted from
photocathode 504. These photoelectrons are emitted in substantially
all directions, but they are accelerated towards solid-state image
sensor 502 by the potential difference between photocathode 504 and
solid-state image sensor 502. In preferred embodiments, the gap
between photocathode 504 and solid-state image sensor 502 is less
than 1 mm. In some embodiments, the gap is approximately 500
.mu.m.
Incorporating solid-state image sensor 502 having one of the
structures and/or fabricated in accordance with any of the methods
described herein enables electron-bombarded image sensor system 501
to operate with a low potential difference between photocathode 504
and solid-state image sensor 502, and yet have high gain because
electrons are more easily able to penetrate through the boron layer
than through a silicon dioxide layer. Because boron-doped silicon,
boron silicide, and boron are all at least partially conductive,
charging of the surface under electron bombardment is minimized or
avoided. The sensitivity to charge up can be further reduced by a
conductive or metallic layer on top of the boron layer as described
herein.
In prior art EBCCD sensors, the gap between the photocathode and
the image sensor is typically 1-2 mm. Such a large gap allows
significant transverse motion of the electrons as they travel from
the photocathode to the image sensor due to energy of the electrons
as they emerge from the photocathode. A gap of 1-2 mm or more is
necessary because of the large potential difference between the
photocathode and the image sensor (typically about 2000 V or more).
Reducing the potential difference between the photocathode and the
image sensor allows a smaller gap to be used. Furthermore, the
lower energy of the electrons means that there is less spreading of
the electrons created within the solid-state image sensor.
The low energy of the electrons arriving at solid-state image
sensor 502 means that the probability of atoms being ablated from
the surface of solid-state image sensor 502 is low to zero.
Furthermore, the energy of the electrons arriving at solid state
image sensor 502 is not enough to generate X-rays from the silicon,
thereby avoiding the generation of spurious signal in nearby pixels
of image sensor 502.
Collisions of low energy electrons with residual gas atoms in the
vacuum created in sealed tube 505 will generate fewer ions as
compared with high energy electrons. Furthermore, due to the low
potential difference between photocathode 504 and solid-state image
sensor 502, those ions will have less kinetic energy when they
strike the photocathode and will ablate less photocathode
material.
Additional details of electron-bombarded image sensors that can be
incorporated into the electron-bombarded image sensor 501 can be
found in U.S. patent application Ser. No. 13/710,315, entitled
"ELECTRON-BOMBARDED CHARGE-COUPLED DEVICE AND INSPECTION SYSTEMS
USING EBCCD DETECTORS", filed by Chuang et al. on Dec. 10, 2012,
and incorporated by reference herein. A photocathode structure
suitable for use in electron-bombarded image sensor system 501 is
described in U.S. Provisional Patent Application 61/679,200
entitled "PHOTOCATHODE WITH LOW NOISE AND HIGH QUANTUM EFFICIENCY,
HIGH SPATIAL RESOLUTION LOW-NOISE IMAGE SENSOR AND INSPECTION
SYSTEMS INCORPORATING AN IMAGE SENSOR", filed by Chuang et al. on
Aug. 3, 2012, and incorporated by reference herein.
FIG. 6 illustrates exemplary driving voltages for the clock signals
of any of the image sensors described herein that incorporate CCDs.
In a CCD, charge needs to be transferred from one storage element
to another until the charge reaches the output amplifier. Multiple
clock signals are needed to transfer the charge. Depending on the
design of the CCD, typically 2, 3 or 4 clock signals are needed. In
some preferred embodiments, those clock signals are sinusoidal, or
substantially sinusoidal, in shape, in preference to substantially
square waveforms used in traditional CCD devices. The advantages of
using sinusoidal waveforms are that the charge transfer is smoother
(which is particularly an advantage in allowing TDI sensors to
track the motion of the image more accurately), and the clock
signals generate less electrical noise and heat because of the
minimal content of harmonics of the fundamental frequency. FIG. 6
illustrates the clock voltages for a 3-phase CCD. Clock signal 601
shows the voltage on the first clock signal as a function of time.
Clock signal 601 is a substantially sinusoidal waveform. The second
clock signal 602 also has a voltage that varies as a function of
time, but is substantially 120.degree. phase-delayed with respect
to clock signal 601. The voltage of the third clock signal 603 also
varies as a function of time, but is substantially 120.degree.
phase-delayed with respect to clock signal 602, and hence
substantially 240.degree. phase-delayed with respect to clock
signal 601. Line 604 illustrates the sum of the three clock signals
601, 602, and 603, which is substantially zero all the time. The
substantially zero sum voltage means that little current from the
clock signals flows in the ground signal of solid-state image
sensor 502, thereby resulting in lower electrical noise levels.
This is in contrast to the sum of three out-of-phase square-wave
clock signals, which would have non-zero sums voltages essentially
all the time.
In an image sensor including a 2-phase CCD (not shown), the two
clock signals would be substantially 180.degree. out of phase with
one another. In a 4-phase CCD (not show), the second clock signal
would be substantially 90.degree. phase-delayed with respect to the
first clock signal, the third clock signal would be substantially
180.degree. phase-delayed with respect to the first clock signal,
and the fourth clock signal would be substantially 270.degree.
phase-delayed with respect to the first clock signal.
More details of the use of sinusoidal and other clock signals for
driving CCD image sensors can be found in U.S. Pat. No. 7,952,633,
entitled "Apparatus for continuous clocking of TDI sensors" by
Brown et al., which issued May 31, 2011, and in U.S. Pat. No.
7,952,633, entitled "Continuous clocking of TDI sensors" by Brown
et al., which issued Oct. 27, 2009. Both of these patents are
incorporated by reference herein.
FIG. 7A illustrates an exemplary split-readout image sensor 700
including two sets of readout circuits 701A and 701B positioned on
either side of an image region 703. Image region 703 includes a
pure boron layer on its light sensitive surface as described
herein. Readout circuits 701A and 701B can include serial registers
702A and 702B and readout amplifiers 704A and 704B, as well as
other components such as transfer gates. Exemplary embodiments of
readout circuits 701A and 701B, as well as other components of
sensor 700 are described in U.S. Pat. No. 7,609,309, entitled
"Continuous Clocking of TDI Sensors", issued Oct. 27, 2009, which
is incorporated by reference herein. Image region 703 is a
two-dimensional (2D) array of pixels, and each line of the image is
read out concurrently in each direction A and B. Each line is then
read out one pixel at a time in the simplest case. Therefore, in
preferred embodiments, the serial registers 702A and 702B can be
divided into a plurality of register segments (e.g. FIG. 7A shows
each serial register being divided into six segments, thereby
allowing parallel read out using a plurality of amplifiers 704A and
704B.
Notably, readout circuits 701A and 701B can be operated
independently, thereby allowing image sensor 700 to provide two
readout directions A and B. In a split-readout mode, each side of
image region 703 (i.e. sides 703A and 703B) can be synchronously
clocked to read out one image line into their respective output
channels. In one embodiment, image region 703 may have 1000 lines,
each line formed by a column of pixels. Therefore, during the
split-readout mode, 500 lines could be read out in direction A and,
concurrently, 500 lines could be read out in direction B.
This split-readout mode is possible based on the timed activation
of the charge-coupled device (CCD) drivers in the image sensor. For
example, a plurality of CCD drivers P1a, P2a, P3a, P1b, P2b, and
P3b can be used to provide phases. As shown in FIG. 7B, CCD drivers
P1a, P2a, P3a, P1b, P2b, and P3b can be characterized as driving
sets of gate electrodes (hereinafter gates), each set having six
gates. In one preferred embodiment of the image sensor, three gates
are provided for each pixel to provide three phases. In FIG. 7B,
two pixels 710 and 711 are shown, wherein gates 731, 732, and 733
are positioned over pixel 710 and gates 734, 735, and 736 are
positioned over pixel 711. In the image sensor, pixels 710 and 711
are aligned along the read-out axis to form part of a column of the
2D array of pixels forming image region 703.
Image region 703 can be implemented as an optical sensor or a
charged particle sensor. In one optical sensor embodiment, image
region 703 can include a photo-sensitive p-type silicon substrate
714 and an n-type buried channel 713. The electrostatic forces in
silicon substrate 714 are determined by the voltage level applied
to a particular gate by a clock input signal (e.g. one of clock
signals from CCD drivers P1a, P2a, P3a, P1b, P2b, and P3b). High
level voltages induce the formation of a potential "well" beneath
the gate, whereas low level voltages form a potential barrier to
electron movement. To ensure that charge from one pixel is not
mixed with other pixels, a gate voltage is driven high when an
adjacent gate voltage is driven low. At an initial state at time
770, gates 731 and 734 of pixels 710 and 711, respectively, have
high level voltages that form potential wells with integrated
charge (i.e. electrons), and gates 732, 733 (of pixel 710) and 735,
736 (of pixel 711) have low level voltages that form potential
barriers. At a subsequent time 721, gates 732 and 735 of pixels 710
and 711, respectively, have high level voltages that form potential
wells with integrated charge (i.e. electrons), and gates 731, 733
(of pixel 710) and 734, 736 (of pixel 711) have low level voltages
that form potential barriers. At yet a subsequent time 771, gates
733 and 736 of pixels 710 and 711, respectively, have high level
voltages that form potential wells with integrated charge (i.e.
electrons), and gates 731, 732 (of pixel 710) and 734, 735 (of
pixel 711) have low level voltages that form potential barriers.
Note that adjacent gates when shifting charge preferably both have
a high level voltage for a short time to facilitate charge
transfer. Thus from time 770 to time 771, the charge is shifted
from left to right, i.e. from pixel 710 to pixel 711. A similar
directional shifting of charge can be take place from time 771 to
time 772.
Additional details of split-readout image sensor 700 are provided
in U.S. Provisional Patent Application 61/735,427, entitled "METHOD
AND APPARATUS FOR HIGH SPEED ACQUISITION OF MOVING IMAGES USING
PULSED ILLUMINATION", filed by David Brown et al. on Dec. 10, 2012,
and incorporated by reference herein. Additional details regarding
other exemplary image sensors are provided in U.S. Pat. No.
7,528,943 entitled "METHOD AND APPARATUS FOR SIMULTANEOUS
HIGH-SPEED ACQUISITION OF MULTIPLE IMAGES" by Brown et al., issued
May 5, 2009, and incorporated by reference herein.
FIG. 8 shows a reticle, photomask or wafer inspection system 800
that simultaneously detects two channels of image or signal on one
sensor 870. Image sensor 870 comprises a split-readout image sensor
as described above. Illumination source 809 may incorporate a 193
nm or sub-200-nm laser. The two channels may comprise reflected and
transmitted intensity when an inspected object 830 is transparent
(for example a reticle or photomask), or may comprise two different
illumination modes, such as angles of incidence, polarization
states, wavelength ranges or some combination thereof. The light is
directed to inspected object 830 using channel one illumination
relay 815 and channel two illumination relay 820.
The inspected object 830 may be a reticle, a photomask, a
semiconductor wafer or other article to be inspected. Image relay
optics 840 can direct the light that is reflected and/or
transmitted by inspected object 830 to a channel one image mode
relay 855 and to a channel two image mode relay. Channel one image
mode relay 855 is tuned to detect the reflection/transmission
corresponding to channel one illumination illumination relay 815,
whereas channel two image mode relay sensor 860 is tuned to detect
the reflection/transmission corresponding to channel two
illumination relay 820. Channel one image mode relay 855 and
channel two image mode relay sensor 860 in turn direct their
outputs to sensor 870. The data corresponding to the detected
signals or images for the two channels is shown as data 890 and is
transmitted to a computer (not shown) for processing.
Other details of reticle and photomask inspection systems and
methods that may be configured to measure transmitted and reflected
light from a reticle or photomask are described in U.S. Pat. No.
7,352,457, which issued to Kvamme et al. on Apr. 1, 2008, and in
U.S. Pat. No. 5,563,702, which issued to Emery et al. on Oct. 8,
1996, both of which are incorporated by reference herein.
FIG. 9 illustrates an exemplary detector assembly 900 incorporating
an image sensor 904, a silicon interposer 902 and other electronics
in accordance with certain embodiments of the present
invention.
In one aspect of the present invention, the detector assembly 900
may include one or more light sensitive sensors 904 disposed on the
surface of an interposer 902. In some embodiments, the one or more
interposers 902 of the assembly 100 may include, but are not
limited to, a silicon interposer. In a further aspect of the
present invention, the one or more light sensitive sensors 904 of
the assembly 900 are back-thinned and further configured for
back-illumination including a boron layer deposited on the back
surface as described above.
In another aspect of the present invention, various circuit
elements of the assembly 900 may be disposed on or built into the
interposer 902. In one embodiment, one or more amplification
circuits (e.g., charge conversion amplifier) (not shown) may be
disposed on or built into the interposer 902. In another
embodiment, one or more conversion circuits 908 (e.g.,
analog-to-digital conversion circuits, i.e. digitizers 908) may be
disposed on or built into the interposer 902. In another
embodiment, one or more driver circuits 906 may be disposed on or
built into the interposer 902. For example, the one or more driver
circuits 906 may include a timing/serial drive circuit. For
instance, the one or more driver circuits 906 may include, but are
not limited to, clock driver circuitry or reset driver circuitry.
In another embodiment, one or more decoupling capacitors (not
shown) may be disposed on or built into the interposer 902. In a
further embodiment, one or more serial transmitters (not shown in
FIG. 9) maybe disposed on or built into the interposer 102.
In another aspect of the present invention, one or more support
structures may be disposed between the bottom surface of the light
sensitive array sensor 904 and the top surface of the interposer
902 in order to provide physical support to the sensor 904. In one
embodiment, a plurality of solder balls 916 may be disposed between
the bottom surface of the light sensitive array sensor 904 and the
top surface of the interposer 902 in order to provide physical
support to the sensor 904. It is recognized herein that while the
imaging region of the sensor 904 might not include external
electrical connections, the back-thinning of the sensor 904 causes
the sensor 904 to become increasingly flexible. As such, solder
balls 916 may be utilized to connect the sensor 904 to the
interposer 902 in a manner that reinforces the imaging portion of
the sensor 904. In an alternative embodiment, an underfill material
may be disposed between the bottom surface of the light sensitive
array sensor 904 and the top surface of the interposer 902 in order
to provide physical support to the sensor 904. For example, an
epoxy resin may be disposed between the bottom surface of the light
sensitive array sensor 904 and the top surface of the interposer
902.
In another aspect of the present invention, the interposer 902 and
the various additional circuitry (e.g., amplification circuit,
driver circuits 906, digitizer circuits 908, and the like) are
disposed on a surface of a substrate 910. In a further aspect, the
substrate 910 includes a substrate having high thermal conductivity
(e.g., ceramic substrate). In this regard, the substrate 910 is
configured to provide physical support to the sensor 904/interposer
902 assembly, while also providing a means for the assembly 900 to
efficiently conduct heat away from the imaging sensor 904 and the
various other circuitry (e.g., digitizer 906, driver circuitry 908,
amplifier, and the like). It is recognized herein that the
substrate may include any rigid highly heat conductive substrate
material known in the art. For example, the substrate 910 may
include, but is not limited to, a ceramic substrate. For instance,
the substrate 110 may include, but is not limited to, aluminum
nitride.
In another embodiment, the substrate 910 may be configured to
provide an interface to a socket or an underlying printed circuit
board (PCB). For example, as shown in FIG. 9, the substrate 910 may
provide interconnection between the interposer 902 and a socket or
a PCB via interconnects 912. Those skilled in the art will
recognize that the substrate 910 may be operatively coupled to an
underlying PCB and further electrically coupled to a socket or PCB
in a variety of ways, all of which are interpreted to be within the
scope of the present invention.
More details of detector assemblies incorporating image sensors,
silicon interposers, and other electronics can be found in U.S.
patent application Ser. No. 13/622,155, entitled "INTERPOSER BASED
IMAGING SENSOR FOR HIGH-SPEED IMAGE ACQUISITION AND INSPECTION
SYSTEMS", filed by Brown et al. on Sep. 18, 2012, and incorporated
by reference herein.
FIG. 10 illustrates an exemplary sensor module array 1000 including
a plurality of time delay integration (TDI) sensor modules 1001.
Each sensor module 1001 includes one of the above-described image
sensors. In some embodiments, the image sensors may have a few nm
(such as 1 or 2 nm) thick coating of Ru or other refractory metal
on top of the boron in order to protect the boron during cleaning.
In one embodiment, each TDI sensor module 1001 can include
localized driving and signal processing circuitry. This circuitry
can include a TDI sensor (the center block), processing circuits
for processing the signals from the TDI sensor, timing and serial
drive circuits, and pixel gate driver circuits. The
driving/processing circuits are positioned around the TDI sensor.
Thus, the TDI sensors in adjacent rows can be aligned such that at
least 100% image coverage is achieved when used in a continuous
scanning configuration.
For example, in the embodiment shown in FIG. 10, the upper row 1002
can be offset with respect to the lower row 1004 such that the TDI
sensor is positioned in the gap produced by the driving/processing
circuits of an adjacent row. To ensure no gaps in image coverage,
the width of each TDI sensor is equal to or greater than the space
between TDI sensors. In this configuration, as the inspected
wafer/mask/reticle is being moved in a TDI image scan direction
1006, sensor module array 1000 can ensure 100% EUV wavelength image
capture. In one embodiment, some minimal overlap between TDI
sensors from adjacent rows can provide redundant data. This
redundant data can, for example, ensure accurate alignment of the
image data generated by TDI sensor modules 1001. In one embodiment
of minimal overlap, the inspection system can arbitrarily select
the data from one TDI sensor module to be used for the edge pixels.
In another embodiment, a detection system can combine and align,
using sub-pixel digital processing, the data from multiple TDI
sensor modules, to achieve improved quality data near edge
pixels.
More details of detector arrays for a EUV inspection system are
described in US Published Patent Application 2011/0116077, entitled
"EUV HIGH THROUGHPUT INSPECTION SYSTEM FOR DEFECT DETECTION ON
PATTERNED EUV MASKS, MASK BLANKS, AND WAFERS", by Chuang et al.,
published on May 19, 2011, and incorporated by reference
herein.
FIG. 11 illustrates an exemplary inspection system 1100 configured
to measure a sample 1108 such as a wafer, reticle, or photomask.
Sample 1108 is placed on a stage 1112 in facilitate movement to
different regions of sample 1108 underneath the optics. Stage 1112
may comprise an X-Y stage or an R-.theta. stage. In some
embodiments, stage 1112 can adjust the height of sample 1108 during
inspection to maintain focus. In other embodiments, an objective
lens 1105 can be adjusted to maintain focus.
An illumination source 1102 may comprise one or more lasers and/or
a broad-band light source. Illumination source 1102 may emit DUV
and/or VUV radiation. Optics 1103 including an objective lens 1105
can direct that radiation towards, and focuses it on, sample 1108.
Optics 1103 may also comprise mirrors, lenses, and/or beam
splitters. Light reflected or scattered from sample 1108 can be
collected, directed, and focused by optics 1103 onto a detector
1106, which is within a detector assembly 1104.
Detector 1106 may include one, or more, of the image sensors
described herein, including boron-coated back-illuminated CCD
sensors, boron-coated back-illuminated CMOS sensors, and
electron-bombarded images sensors incorporating a boron-coated
back-thinned solid state image sensor. Detector 1106 may include a
two-dimensional array sensor or a one-dimensional line sensor. In
one embodiment, the output of detector 1106 can be provided to a
computing system 1114, which analyzes the output. Computing system
1114 can be configured by program instructions 1118, which can be
stored on a carrier medium 1116.
In one embodiment, illumination source 1102 may be a continuous
source such as an arc lamp, a laser-pumped plasma light source, or
a CW laser. In another embodiment, illumination source 1102 may be
a pulsed source such as a mode-locked laser, a Q-switched laser, or
a plasma light source pumped by a Q-switched laser. In some
embodiments of inspection system 1100 incorporating a Q-switched
laser, the image sensor or sensors within detector 1106 are
synchronized with the laser pulses. In such embodiments, the image
sensor may operate in a TDI mode during the laser pulse and then
may readout the data through multiple outputs on both sides of the
sensor in between laser pulses.
Some embodiments of inspection system 1100 illuminate a line on
sample 1108, and collect scattered and/or reflected light in one or
more dark-field and/or bright-field collection channels. In such
embodiments, the image sensor may be a line sensor or an
electron-bombarded line sensor.
Some embodiments of inspection system 1100 illuminate multiple
spots on sample 1108, and collect scattered and/or reflected light
in one or more dark-field and/or bright-field collection channels.
In such embodiments, the image sensor may be a two-dimensional
array sensor or an electron-bombarded two-dimensional array
sensor.
Additional details of various embodiments of inspection system
1100, incorporating one or more images described herein, can be
found in U.S. Provisional Application 61/506,892, entitled "SAMPLE
INSPECTION SYSTEM", filed on Jul. 12, 2011 by Romanovsky et al.,
U.S. patent application Ser. No. 13/554,954, entitled "WAFER
INSPECTION SYSTEM", filed on Jul. 9, 2012 by Romanovsky et al.,
U.S. Published Patent Application 2009/0180176, by Armstrong et
al., which published on Jul. 16, 2009, U.S. Published Patent
Application 2007/0002465 by Chuang et al., which published on Jan.
4, 2007, U.S. Pat. No. 5,999,310, by Shafer et al., which issued on
Dec. 7, 1999, and U.S. Pat. No. 7,525,649 by Leong et al., which
issued on Apr. 28, 2009. All of these patents and patent
applications are incorporated by reference herein.
The various embodiments of the structures and methods of this
invention that are described above are illustrative only of the
principles of this invention and are not intended to limit the
scope of the invention to the particular embodiments described. For
example, additional steps may be added to the flow charts depicted
in FIGS. 1 and 2, or some of the steps shown may be done in
different sequence than shown. Thus, the invention is limited only
by the following claims and their equivalents.
* * * * *
References