U.S. patent number 7,888,710 [Application Number 11/874,129] was granted by the patent office on 2011-02-15 for cmos fabrication process utilizing special transistor orientation.
This patent grant is currently assigned to Intel Corporation. Invention is credited to Mark Armstrong, Kelin J. Kuhn, Paul A. Packan, Gerhard Schrom, Scott Thompson, Sunit Tyagi.
United States Patent |
7,888,710 |
Armstrong , et al. |
February 15, 2011 |
CMOS fabrication process utilizing special transistor
orientation
Abstract
Complementary metal oxide semiconductor transistors are formed
on a silicon substrate. The substrate has a {100} crystallographic
orientation. The transistors are formed on the substrate so that
current flows in the channels of the transistors are parallel to
the <100> direction. Additionally, longitudinal tensile
stress is applied to the channels.
Inventors: |
Armstrong; Mark (Hillsboro,
OR), Schrom; Gerhard (Hillsboro, OR), Tyagi; Sunit
(Portland, OR), Packan; Paul A. (Beaverton, OR), Kuhn;
Kelin J. (Aloha, OR), Thompson; Scott (Portland,
OR) |
Assignee: |
Intel Corporation (Santa Clara,
CA)
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Family
ID: |
29583672 |
Appl.
No.: |
11/874,129 |
Filed: |
October 17, 2007 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20080036005 A1 |
Feb 14, 2008 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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09727296 |
Nov 29, 2000 |
7312485 |
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Current U.S.
Class: |
257/255; 257/418;
257/358; 257/254; 257/369; 257/417 |
Current CPC
Class: |
H01L
21/823878 (20130101); H01L 21/823807 (20130101); H01L
29/7846 (20130101); H01L 27/1446 (20130101); H01L
29/045 (20130101); H01L 29/7843 (20130101); H01L
27/0922 (20130101) |
Current International
Class: |
H01L
27/148 (20060101) |
Field of
Search: |
;257/358,369,254,417,418,255 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0703628 |
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Mar 1996 |
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EP |
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928562 |
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Jun 1963 |
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GB |
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1222251 |
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Feb 1971 |
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GB |
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1-162362 |
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Jun 1989 |
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JP |
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Other References
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Performance", IBM Technical Disclosure Bulletin, vol. 30, No.
9.02.1988, Feb. 1, 1988, pp. 330-333. cited by other .
PCT/US01/44162--PCT International Preliminary Examination Report,
dated Jun. 25, 2003. cited by other .
EP 01 998 998.7-1235--EP Examination Report, dated Mar. 31, 2008.
cited by other .
Office Action mailed on May 31, 2007, U.S. Appl. No. 09/727,296,
filed Nov. 29, 2000. cited by other .
Office Action dated Mar. 31, 2008, European Application No. 01 998
998.7-1235, Filed Nov. 6, 2001. cited by other .
Matsuda, T. et al., "Electrical Characteristics of
0.degree./.+-.45.degree./90.degree.--Orientation CMOSFET with
Source/Drain Fabricated by Various Ion-Implantation Methods", IEEE
Transactions on Electron Devices, vol. 46, No. 4, Apr. 1999. cited
by other .
Sayama, H. et al., "Effect of <100> Channel Direction for
High Performance SCE Immune pMOSFET with Less Than 0.15 .mu.m Gate
Length", IEEE, 1999. cited by other .
Scott, G. et al., "NMOS Drive Current Reduction Caused by
Transistor Layout and Trench Isolation Induced Stress", IEEE, 1999.
cited by other .
Scott, G. et al., "The Effect of Stress and Dopant Redistribution
on Trench-Isolated Narrow Devices", in Challenges in Process
Integration and Device Technology, Proceeding of SPIE vol. 4181,
2000. cited by other .
Welser, J. et al., "Strain Dependence of the Performance
Enhancement in Strained-Sl n-MOSFETs", IEEE, 1994. cited by other
.
PCT International Search Report, PCT/US01/44162, Aug. 26, 2002.
cited by other.
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Primary Examiner: Gurley; Lynne A
Assistant Examiner: Gebremariam; Samuel A
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor &
Zafman LLP
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a continuation of U.S. application Ser.
No. 09/727,296, filed Nov. 29, 2000.
Claims
What is claimed is:
1. An integrated circuit comprising: an n-type metal oxide
semiconductor (NMOS) device formed on a semiconductor substrate; a
p-type metal oxide semiconductor (PMOS) device formed on the
semiconductor substrate, wherein the NMOS device and the PMOS
device are oriented so that the current flows in a
<100>direction of the semiconductor substrate; and a stressor
to apply a stress to the semiconductor substrate to create a first
longitudinal tensile stress on a channel of the NMOS device and to
create a second longitudinal tensile stress on a channel of the
PMOS device, wherein the first longitudinal tensile stress is the
same as the second longitudinal tensile stress.
2. The integrated circuit of claim 1 wherein the stressor is a
high-tensile nitride dielectric.
3. The integrated circuit of claim 1 wherein the stressor is a
tensile shallow trench isolation fill.
4. The integrated circuit of claim 1 wherein the devices are
transistors.
5. The integrated circuit of claim 1, wherein the semiconductor
substrate is formed from {100} silicon.
6. The integrated circuit of claim 1, wherein the semiconductor
substrate includes crystalline silicon having an orientation
corresponding to a {100} plane, and wherein the <100>
direction is a direction normal to the {100} plane.
7. The integrated circuit of claim 1, wherein at least one of the
NMOS or PMOS devices is a transistor having a source region and a
drain region, wherein the current flows between the source region
and the drain region along the <100> direction.
8. An apparatus comprising: a semiconductor substrate formed from
{100} silicon; a p-type metal oxide semiconductor (PMOS) transistor
formed on the semiconductor substrate, the PMOS transistor having a
PMOS channel for carrying current and oriented so that current
flows in a <100> direction; an n-type metal oxide
semiconductor (NMOS) transistor formed on said semiconductor
substrate, said NMOS transistor having a NMOS channel for carrying
current and oriented so that current flows in a <100>
direction; and a stressor to apply a stress to the semiconductor
substrate to create a first longitudinal tensile stress on a
channel of the NMOS device and to create a second longitudinal
tensile stress on a channel of the PMOS device, wherein the first
longitudinal tensile stress is the same as the second longitudinal
tensile stress.
9. The integrated circuit of claim 8 wherein the stressor is a
high-tensile nitride dielectric or a tensile shallow trench
isolation fill.
10. The integrated circuit of claim 8 wherein the stressor is a
tensile shallow trench isolation fill.
11. The apparatus of claim 8, wherein the {100} silicon includes
crystalline silicon having an orientation corresponding to a {100}
plane, and wherein the <100> direction is a direction normal
to the {100} plane.
12. The apparatus of claim 8, wherein at least one of the NMOS and
PMOS transistors has a source region and a drain region, wherein
the current flows between the source region and the drain region
along the <100> direction.
Description
TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor transistors, and
more particularly, to a transistor structure oriented having a
current flow parallel to a specific crystal direction.
BACKGROUND OF THE INVENTION
Complementary metal oxide semiconductor (CMOS) integrated circuits
include both N-type devices (NMOS) and P-type devices (PMOS), the
former utilizing electrons as the carriers and the latter utilizing
holes as the carriers. CMOS technology is employed in the large
majority of integrated circuits manufactured today.
An important factor in the performance of CMOS integrated circuits
is the presence of good mobility for both holes and electrons. The
mobility of both carriers should be as high as possible to enhance
both PMOS and NMOS performance. The overall CMOS circuit
performance depends similarly on both NMOS and PMOS performance,
and thus in turn, on both electron and hole mobility.
It is known that the application of stress on a semiconductor
material, such as silicon, changes the mobility of electrons and
holes, which in turn modifies the performance of NMOS and PMOS
devices formed thereon. An increase in mobility results in
increased performance. However, it has also been found that the
electron and hole mobilities do not always react the same way to
stress, thereby complicating the process. In addition, the
dependence of mobility on stress depends on the surface orientation
of the crystalline semiconductor material and the directions of
stress and current flow. For example, for current flow along the
<110> directions on {100} planes, longitudinal tensile stress
tends to increase the mobility of electrons and decrease the
mobility of holes. In contrast, for current flow along the
<100> directions on {100} planes, longitudinal tensile stress
tends to increase the mobility of both electrons and holes.
Currently, semiconductor devices are oriented such that the current
flows along the <100> direction on {100} silicon. This can be
seen in FIG. 2, which shows a top view of a semiconductor wafer
201. The semiconductor wafer 201 is commonly referred to as "{100}
silicon," which is the predominant type of semiconductor wafer
being used today. In the prior art, NMOS and PMOS transistors 203
are oriented in such a manner so that the current flow between
source and drain is aligned with the <110> direction,
relative to the semiconductor wafer 201. Thus, the transistors 203
are oriented as shown in FIG. 2.
In this orientation, the mobilities of electrons and holes change
inversely in reaction to longitudinal stress. In other words, when
stress is applied to the underlying silicon along the direction of
current flow, either the electron mobility is increased and the
hole mobility is decreased or the hole mobility is increased and
the electron mobility is decreased. Thus, in such an arrangement,
the overall CMOS circuit performance is not enhanced.
For this reason, selective stressing of the silicon material must
be employed to increase the carrier mobility of one type of device
without degrading the mobility of the other type of device. Thus,
stress may be applied to the wafer 201 in the location of
transistor 203a, but not transistor 203b, or vice versa. This
requires costly processing steps that may include masking,
deposition, or etching.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the three types of
crystalline orientation for silicon.
FIG. 2 is a schematic diagram showing a prior art orientation of
CMOS devices on a semiconductor wafer.
FIG. 3 is a schematic diagram showing an orientation of CMOS
devices on a semiconductor wafer in accordance with the present
invention.
FIG. 4A is a chart showing the piezoresistive coefficients for a
P-type {100} silicon substrate as a function of current flow
direction.
FIG. 4B is a chart showing the piezoresistive coefficients for an
N-type {100} silicon substrate as a function of current flow
direction.
FIG. 5 shows a transistor that is undergoing longitudinal tensile
stress.
FIG. 6 shows a transistor that is undergoing transverse tensile
stress.
DETAILED DESCRIPTION
Silicon (Si) is presently the most important semiconductor for the
electronics industry. Most silicon that is used to form silicon
wafers is formed from single crystal silicon. The silicon wafers
serve as the substrate on which CMOS devices are formed. The
silicon wafers are also referred to as a semiconductor substrate or
a semiconductor water.
In crystalline silicon, the atoms which make up the solid are
arranged in a periodic fashion. If the periodic arrangement exists
throughout the entire solid, the substance is defined as being
formed of a single crystal. If the solid is composed of a myriad of
single crystal regions the solid is referred to as polycrystalline
material.
Silicon, as used in integrated circuits, can be in one of three
forms: (1) single crystal silicon, (2) polycrystalline silicon
(polysilicon), and (3) amorphous silicon. As noted above, silicon
wafers are fabricated to have single crystal form.
The periodic arrangement of atoms in a crystal is called the
lattice. The crystal lattice also contains a volume which is
representative of the entire lattice and is referred to as a unit
cell that is regularly repeated throughout the crystal.
Silicon has a diamond cubic lattice structure, which can be
represented as two interpenetrating face centered cubic lattices.
Thus, the simplicity of analyzing and visualizing cubic lattices
can be extended to characterization of silicon crystals. In the
description herein, references to various planes in silicon
crystals will be made, especially to the {100}, {110}, and {111}
planes.
These planes describe the orientation of the plane of silicon atoms
relative to the principle crystalline axes. The numbers {xyz} are
referred to as Miller indices and are determined from the
reciprocals of the points at which the crystal plane of silicon
intersects the principle crystalline axes. Thus, FIG. 1 shows three
orientations of the crystal plane of silicon. In FIG. 1(A), the
crystal plane of silicon intersects the x-axis at 1 and never
intersects the y or z-axis. Therefore, the orientation of this type
of crystalline silicon is {100}. Similarly, FIG. 1(B) shows {110}
crystalline silicon and FIG. 1(C) shows {111} silicon. The {111}
and {100} orientations are the two primary wafer orientations in
commercial use.
Note that for any given plane in a cubic crystal there are five
other equivalent planes. Thus, the six sides of the cube comprising
the basic unit cell of the crystal are all considered {100} planes.
The notation {xyz} refers to all six of the equivalent planes.
Reference will also be made herein to the crystal directions,
especially the <100>, <110> and <111> directions.
These are defined as the normal direction to the respective plane.
Thus, the <100> direction is the direction normal to the
{100} plane. The notation <xyz> refers to all six equivalent
directions.
As noted above, in the prior art, most MOS transistors are
fabricated on {100} silicon with the gates oriented such that
current flows parallel to the <110> directions. This is shown
in FIG. 2.
In accordance with the present invention, the MOS transistors are
oriented so that current flow is substantially along the
<100> direction as shown in FIG. 3. FIG. 3 shows a top view
of a semiconductor wafer 301 formed from {110} silicon. Transistor
devices, formed on the semiconductor wafer 301, are represented by
transistors 303a and 303b. The orientation of the transistors 303a
and 303b are such that current that flows between the source and
drain of the transistors is substantially along the <100>
direction of the semiconductor wafer 301. Clearly, the transistors
303a and 303b are not drawn to scale and are meant to be
exemplary.
Thus, in accordance with one embodiment of the present invention,
devices formed on the silicon wafer have a specific device
orientation and a fabrication process is used that induces
longitudinal tensile stress in the channel region of the devices.
The longitudinal tensile stress on the channel will increase the
mobility of electrons without degrading the mobility of holes.
In the prior art, devices were oriented such that the current flows
substantially along the <110> directions on {100} silicon. In
this orientation, the mobilities of electrons and holes change in
opposite directions in reaction to longitudinal tensile stress.
Thus, the overall CMOS circuit performance is not enhanced. For
this reason, selective stressing is employed to increase the
carrying mobility of one type of device without degrading the
other. This requires costly processing steps.
By orienting the devices to have their current flow in the
<100> direction, this reduces or reverses the relative
degradation of one carrier mobility commensurate with a given
amount of increase in the mobility of the other type of carrier due
to stress. This eliminates the need for selective stressing to
realize an acceptable overall performance gain. The orientation of
the present invention enables stress to be used as a tool to
increase CMOS circuit performance.
The piezoresistive coefficients for silicon are anisotropic
relative to the direction of current flow. FIG. 4a shows the
piezoresistive coefficient for a p-type region of a semiconductor
substrate and FIG. 4b shows the piezoresistive coefficient for an
n-type region of a semiconductor substrate as a function of
direction of current flow oil the {100} surfaces. NMOS transistors
are known to behave similarly to n-type regions and have similar
piezoresistive coefficients, as do PMOS transistors and p-type
regions. Thus, FIGS. 4a and 4b are applicable to NMOS and PMOS
transistors.
The piezoresistive coefficients relate the change in resistance
along various directions when stress is applied. Positive values
indicate an increase in resistance for tensile stress. The change
in resistance is inversely proportional to the change in mobility,
which is directly proportional to the speed of the transistor.
Thus, a higher resistance results in a slower transistor.
A longitudinal tensile stress is defined as a "stretching" of the
channel in the same direction in which current flows. For example,
as seen in FIG. 5, a transistor 601 is seen that has a gate 603, a
source 605, and a drain 607. When an appropriate voltage is applied
to the gate 603, current flows between the source 605 and the drain
607 along the direction arrow 609. A longitudinal tensile stress
would be stress that tends to move the source 605 and drain 607
apart along direction 609. Additionally, a longitudinal compressive
stress would be stress that tends to move the source 605 and drain
607 closer together along direction 609.
Ax transverse tensile stress is defined as a "stretching" of the
channel in a direction orthogonal to which the current flows. For
example as seen in FIG. 6, a transistor 701 is seen that has a gate
703, a source 705, and a drain 707. When an appropriate voltage is
applied to the gate 703, current flows between the source 705 and
the drain 707 along the direction arrow 709. A transverse tensile
stress would be stress that is in a direction 711 that is
orthogonal to the direction of current flow 709.
As seen in FIG. 4b, when a longitudinal tensile stress (as
indicated by solid line 401) is applied to an n-type region of a
semiconductor wafer, the piezoresistive coefficient is at a minimum
(approx -100 units) in the <100> direction. As seen in FIG.
4a, when the same longitudinal tensile stress (as indicated by
solid line 403) is applied to a p-type region of the semiconductor
wafer, the piezoresistive coefficient is only slightly above the
neutral condition (0 units).
Thus, in accordance with one embodiment of the present invention,
transistors should be oriented to have current flowing in the
<100> direction and applying longitudinal tensile stress in
the <100> direction. This will result in an increase in the
speed of NMOS transistors without affecting the PMOS transistors.
This is preferable to the <110> orientation of the prior art,
where the PMOS transistor is degraded with the addition of such
stress, necessitating a cumbersome selective stress processing to
enable an overall gain.
In accordance with an alternative embodiment, it is possible to
orient the transistor devices to have current flow in the
<110> direction while applying a transverse stress (as
indicated by the dashed lines 405 and 407). For PMOS transistors,
this gives about a -70 value and for NMOS transistors, this gives
about a -25 value. However, in practice, this is difficult to
accomplish because transistors are typically many times wider than
they are long. Thus, a force applied on the side of the channel,
which would cause transverse stress, is greatly diminished in the
middle of the channel.
The particular details of introducing a longitudinal tensile stress
on a substrate are well known in the art and will not be discussed
in detail herein. For example, in one embodiment, application of
high-tensile nitride dielectric is used. The high-tensile nitride
dielectric is also referred to herein as a "stressor" structure
that will implement the tensile stress. Alternatively, in another
embodiment, the stressor structure may be a tensile shallow trench
isolation (STI) fill. Although two examples of stressors are given
as an example, the term "stressor" as used herein shall mean any
structure that causes tensile stress. Additionally, the formation
of transistors oriented to have their current flow in the
<100> direction is relatively straightforward. This can be
done, for example, by rotating either the underlying semiconductor
wafer or the production masks 45 degrees relative to the prior art
orientation (for a {100} silicon wafer).
While specific embodiments and applications of the present
invention have been illustrated and described it is to be
understood that the invention is not limited to the precise
configuration and components disclosed herein. Various
modifications, changes, and variations, which will be apparent to
those skilled in the art, may be made in the arrangement,
operation, and details of the methods and systems of the present
invention disclosed herein without departing from the spirit and
scope of the invention.
These modifications can be made to the invention in light of the
above detailed description. The terms used in the following claims
should not be construed to limit the invention to the specific
embodiments disclosed in the specification and the claims. Rather,
the scope of the invention is to be determined entirely by the
following claims, which are to be construed in accordance with
established doctrines of claim interpretation.
* * * * *