PACKAN; Paul A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for PACKAN; Paul A..The latest application filed is for "diffused tip extension transistor".

Company Profile

2.12.9

PACKAN; Paul A. - Beaverton OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Diffused Tip Extension Transistor App 20210050448 - PATEL; Pratik A. ; et al.	2021-02-18
Diffused tip extension transistor Grant 10,872,977 - Patel , et al. December 22, 2	2020-12-22
Diffused Tip Extension Transistor App 20190245088 - PATEL; Pratik A. ; et al.	2019-08-08
Diffused tip extension transistor Grant 10,304,956 - Patel , et al.	2019-05-28
Diffused Tip Extension Transistor App 20160380102 - PATEL; Pratik A. ; et al.	2016-12-29
CMOS fabrication process utilizing special transistor orientation Grant 7,888,710 - Armstrong , et al. February 15, 2	2011-02-15
Cmos Fabrication Process Utilizing Special Transistor Orientation App 20080036005 - Armstrong; Mark ; et al.	2008-02-14
CMOS fabrication process utilizing special transistor orientation Grant 7,312,485 - Armstrong , et al. December 25, 2	2007-12-25
Nitrogen controlled growth of dislocation loop in stress enhanced transistor Grant 7,226,824 - Weber , et al. June 5, 2	2007-06-05
Nitrogen controlled growth of dislocation loop in stress enhanced transistor Grant 7,187,057 - Weber , et al. March 6, 2	2007-03-06
Nitrogen controlled growth of dislocation loop in stress enhanced transistor App 20050017309 - Weber, Cory E. ; et al.	2005-01-27
Nitrogen controlled growth of dislocation loop in stress enhanced transistor App 20050014351 - Weber, Cory E. ; et al.	2005-01-20
Nitrogen controlled growth of dislocation loop in stress enhanced transistor Grant 6,800,887 - Weber , et al. October 5, 2	2004-10-05
Nitrogen Controlled Growth Of Dislocation Loop In Stress Enhanced Transistor App 20040191975 - Weber, Cory E. ; et al.	2004-09-30
CMOS fabrication process utilizing special transistor orientation App 20020063292 - Armstrong, Mark ; et al.	2002-05-30
Transistor with ultra shallow tip and method of fabrication Grant 6,326,664 - Chau , et al. December 4, 2	2001-12-04
Channel dopant implantation with automatic compensation for variations in critical dimension Grant 6,020,244 - Thompson , et al. February 1, 2	2000-02-01
Low damage doping technique for self-aligned source and drain regions Grant 5,976,939 - Thompson , et al. November 2, 1	1999-11-02
Transistor with ultra shallow tip and method of fabrication Grant 5,710,450 - Chau , et al. January 20, 1	1998-01-20

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