Tyagi; Sunit

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tyagi; Sunit.The latest application filed is for "system and method for dynamic balancing power in a battery pack".

Company Profile

2.17.22

Tyagi; Sunit - Karnataka IN
Tyagi; Sunit - Bangalore IN
Tyagi; Sunit - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System And Method For Dynamic Balancing Power In A Battery Pack App 20220021221 - Tyagi; Sunit ; et al.	2022-01-20
DC-DC power conversion system Grant 11,183,839 - Apte , et al. November 23, 2	2021-11-23
Surface Modification Control Stations And Methods In A Globally Distributed Array For Dynamically Adjusting The Atmospheric, Ter App 20190265387 - Tyagi; Sunit	2019-08-29
Dc-dc Power Conversion System App 20180102646 - Apte; Jitendra ; et al.	2018-04-12
Power conversion for distributed DC source array Grant 9,577,548 - Tyagi , et al. February 21, 2	2017-02-21
Power Conversion For Distributed Dc Source Array App 20140008987 - Tyagi; Sunit ; et al.	2014-01-09
Power conversion for distributed DC source array Grant 8,552,587 - Tyagi , et al. October 8, 2	2013-10-08
Power Conversion For Distributed Dc Source Array App 20120019072 - Tyagi; Sunit ; et al.	2012-01-26
CMOS fabrication process utilizing special transistor orientation Grant 7,888,710 - Armstrong , et al. February 15, 2	2011-02-15
Method and apparatus to lower operating voltages for memory arrays using error correcting codes Grant 7,581,154 - Rai , et al. August 25, 2	2009-08-25
Active region spacer for semiconductor devices and method to form the same Grant 7,560,780 - Curello , et al. July 14, 2	2009-07-14
Transistor with strain-inducing structure in channel Grant 7,473,591 - Cea , et al. January 6, 2	2009-01-06
Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions App 20080311720 - Hoffman; Thomas ; et al.	2008-12-18
Strained silicon MOS device with box layer between the source and drain regions Grant 7,422,950 - Curello , et al. September 9, 2	2008-09-09
Device with stepped source/drain region profile Grant 7,335,959 - Curello , et al. February 26, 2	2008-02-26
Cmos Fabrication Process Utilizing Special Transistor Orientation App 20080036005 - Armstrong; Mark ; et al.	2008-02-14
CMOS fabrication process utilizing special transistor orientation Grant 7,312,485 - Armstrong , et al. December 25, 2	2007-12-25
Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance App 20070145495 - Curello; Giuseppe ; et al.	2007-06-28
Active region spacer for semiconductor devices and method to form the same App 20070132057 - Curello; Giuseppe ; et al.	2007-06-14
Strained silicon MOS device with box layer between the source and drain regions App 20070134859 - Curello; Giuseppe ; et al.	2007-06-14
Isolation body for semiconductor devices and method to form the same App 20070132034 - Curello; Giuseppe ; et al.	2007-06-14
Method and apparatus to lower operating voltages for memory arrays using error correcting codes App 20070022360 - Rai; Nivruti ; et al.	2007-01-25
Sacrificial capping layer for transistor performance enhancement App 20070004114 - Lee; Seok-Hee ; et al.	2007-01-04
Device with stepped source/drain region profile App 20060145273 - Curello; Giuseppe ; et al.	2006-07-06
Transistor with strain-inducing structure in channel App 20060084216 - Cea; Stephen M. ; et al.	2006-04-20
Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions App 20060065937 - Hoffmann; Thomas ; et al.	2006-03-30
Transistor with strain-inducing structure in channel Grant 7,019,326 - Cea , et al. March 28, 2	2006-03-28
Transistor with strain-inducing structure in channel App 20050106792 - Cea, Stephen M. ; et al.	2005-05-19
Method for making a semiconductor device having an ultra-thin high-k gate dielectric Grant 6,787,440 - Parker , et al. September 7, 2	2004-09-07
Method for making a semiconductor device having an ultra-thin high-k gate dielectric App 20040110361 - Parker, Christopher G. ; et al.	2004-06-10
Compact input/output signal driver for electrostatic discharge protection App 20040080356 - Hareland, Scott A. ; et al.	2004-04-29
CMOS fabrication process utilizing special transistor orientation App 20020063292 - Armstrong, Mark ; et al.	2002-05-30
Asymmetric MOSFET devices Grant 6,384,457 - Tyagi , et al. May 7, 2	2002-05-07
Process for making semiconductor device with epitaxially grown source and drain Grant 6,372,583 - Tyagi April 16, 2	2002-04-16
Methods to produce asymmetric MOSFET devices Grant 6,297,104 - Tyagi , et al. October 2, 2	2001-10-02
Asymmetric Mosfet Devices App 20010013628 - TYAGI, SUNIT ; et al.	2001-08-16
High power PMOS device Grant 6,177,705 - Tyagi , et al. January 23, 2	2001-01-23

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