U.S. patent number 11,004,771 [Application Number 16/390,669] was granted by the patent office on 2021-05-11 for cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices.
This patent grant is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The grantee listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Tsung-Yu Chen, Cheng-Chieh Hsieh, Wensen Hung, Shin-Puu Jeng, Chi-Hsi Wu.
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United States Patent |
11,004,771 |
Hsieh , et al. |
May 11, 2021 |
Cooling devices, packaged semiconductor devices, and methods of
packaging semiconductor devices
Abstract
Cooling devices, packaged semiconductor devices, and methods of
packaging semiconductor devices are disclosed. In some embodiments,
a cooling device for a semiconductor device includes a reservoir
having a first plate and a second plate coupled to the first plate.
A cavity is between the first plate and the second plate. A phase
change material (PCM) is in the cavity. The cooling device is
adapted to dissipate heat from a packaged semiconductor device.
Inventors: |
Hsieh; Cheng-Chieh (Tainan
County, TW), Wu; Chi-Hsi (Hsinchu, TW),
Jeng; Shin-Puu (Hsinchu, TW), Chen; Tsung-Yu
(Hsinchu, TW), Hung; Wensen (Zhubei, TW) |
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
N/A |
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd. (Hsin-Chu, TW)
|
Family
ID: |
1000005543463 |
Appl.
No.: |
16/390,669 |
Filed: |
April 22, 2019 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20190252294 A1 |
Aug 15, 2019 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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14880030 |
Oct 9, 2015 |
10269682 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
23/4275 (20130101); H01L 23/3675 (20130101); H01L
23/427 (20130101); H01L 25/105 (20130101); H01L
24/20 (20130101); H01L 2224/32225 (20130101); H01L
2224/24137 (20130101); H01L 2924/1436 (20130101); H01L
2224/04105 (20130101); H01L 2224/9222 (20130101); H01L
24/19 (20130101); H01L 2224/32145 (20130101); H01L
23/3128 (20130101); H01L 2924/18162 (20130101); H01L
2224/73204 (20130101); H01L 2224/12105 (20130101); H01L
2224/73267 (20130101); H01L 2224/32245 (20130101); H01L
2924/1436 (20130101); H01L 2924/00012 (20130101) |
Current International
Class: |
H01L
23/427 (20060101); H01L 23/367 (20060101); H01L
23/373 (20060101); H01L 23/00 (20060101); H01L
25/10 (20060101); H01L 21/56 (20060101); H01L
23/34 (20060101); H01L 23/31 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
Fujikura, "Heat Pipe", product description,
http://www.directindustry.com/prod/fujikura/heat-pipes-16619-1083149.html-
, downloaded May 28, 2015, 21 pages. cited by applicant .
Sharma, S.D., et al., "Phase Change Materials for Low Temperature
Solar Thermal Applications," Res. Rep. Fac. Eng. Mie Univ., vol.
29, pp. 31-64 (2004). cited by applicant .
"Heat Pipe Technology: Passive Heat Transfer for Greater
Efficiency," Thermacore Thermal Management Solutions,
http://www.thermacore.com/thermal-basics/heat-pipe-technology.aspx,
downloaded May 28, 2015, 2 pages. cited by applicant .
Wikipedia, "Heat Pipe", http://en.wikipedia.org/wiki/Heat_pipe,
downloaded May 28, 2015, 11 pages. cited by applicant.
|
Primary Examiner: Malek; Maliheh
Attorney, Agent or Firm: Slater Matsil, LLP
Parent Case Text
PRIORITY CLAIM AND CROSS-REFERENCE
This application is a divisional of U.S. patent application Ser.
No. 14/880,030, entitled "Cooling Devices, Packaged Semiconductor
Devices, and Methods of Packaging Semiconductor Devices," filed on
Oct. 9, 2015, which application is incorporated herein by
reference.
Claims
What is claimed is:
1. A semiconductor device comprising: an integrated circuit die
coupled to an interconnect structure; a molding compound
surrounding sidewalls of the integrated circuit die; a cooling
device attached to the integrated circuit die and the molding
compound, the cooling device comprising: a reservoir comprising a
first plate and a second plate coupled to the first plate; a cavity
disposed between the first plate and the second plate; and a phase
change material (PCM) disposed in the cavity, wherein the cooling
device is adapted to dissipate heat from the integrated circuit
die; an adhesive extending from the molding compound to the cooling
device; and a thermal interface material extending from the
integrated circuit die to the cooling device, an entire surface of
the integrated circuit die being in contact with the thermal
interface material, the thermal interface material contacting the
adhesive at an interface extending from the molding compound to the
cooling device, the thermal interface material comprising a
material different from a material of the adhesive.
2. The semiconductor device according to claim 1, wherein the first
plate or the second plate comprises a plurality of protruding
features disposed thereon.
3. The semiconductor device according to claim 1, wherein the PCM
comprises a material adapted to change phase between a solid and a
liquid, a liquid and a gas, or a solid and a gas.
4. The semiconductor device according to claim 1, wherein the
cavity comprises a first cavity, wherein the PCM comprises a first
PCM, and wherein the cooling device comprises a second cavity
disposed between the first plate and the second plate, and a second
PCM disposed in the second cavity.
5. The semiconductor device according to claim 4, wherein a first
portion of the cooling device comprising the first cavity is
coupled to a second portion of the cooling device comprising the
second cavity by a conformable member.
6. The semiconductor device according to claim 1, wherein the
cooling device further comprises an opening in the first plate or
the second plate and a plug disposed in the opening, and wherein
the plug is adapted to retain the PCM within the cavity.
7. The semiconductor device according to claim 1, wherein the first
plate or the second plate comprises a metal or a semiconductive
material.
8. A packaged semiconductor device comprising: an integrated
circuit die; an interconnect structure coupled to the integrated
circuit die; a molding material disposed around the integrated
circuit die and over the interconnect structure; and a cooling
device coupled to the integrated circuit die and the molding
material, the cooling device comprising: a reservoir including a
first plate and a second plate coupled to the first plate; a cavity
disposed between the first plate and the second plate; and a phase
change material (PCM) disposed in the cavity, wherein edges of the
second plate are coupled to edges of the first plate, and wherein
the cooling device is adapted to dissipate heat from the integrated
circuit die, the interconnect structure, or the molding material;
and a heat sink coupled to the cooling device through an adhesive,
the cooling device being disposed within a recess of the heat
sink.
9. The packaged semiconductor device according to claim 8, wherein
the first plate and the second plate of the cooling device comprise
a conformable material.
10. The packaged semiconductor device according to claim 8, wherein
the cooling device is coupled to the integrated circuit die and the
molding material through a thermal interface material.
11. The packaged semiconductor device according to claim 8, wherein
surfaces of the adhesive, the cooling device, and the heat sink are
level with one another.
12. The packaged semiconductor device according to claim 8, wherein
the heat sink comprises copper, aluminum, or magnesium.
13. The packaged semiconductor device according to claim 8, wherein
the adhesive comprises a heat conductive adhesive.
14. The packaged semiconductor device according to claim 8, wherein
the adhesive has a thickness from 50 .mu.m to 200 .mu.m.
15. A semiconductor device comprising: a cooling device comprising:
a first phase change material disposed in a first cavity, the first
phase change material changing phase upon application of heat to a
first portion of the cooling device; a second phase change material
disposed in a second cavity, the second cavity being completely
sealed from the first cavity, the second phase change material
changing phase upon application of heat to a second portion of the
cooling device; a first integrated circuit die; a second integrated
circuit die; a thermal interface material coupling the first
portion of the cooling device to the first integrated circuit die
and coupling the second portion of the cooling device to the second
integrated circuit die; and a molding compound attached to the
cooling device by an adhesive, the adhesive contacting the thermal
interface material.
16. The semiconductor device of claim 15, further comprising a
substrate, wherein the substrate is coupled to a first surface of
the first integrated circuit die and a first surface of the second
integrated circuit die, wherein the first portion of the cooling
device is coupled to a second surface of the first integrated
circuit die opposite the first surface of the first integrated
circuit die, and wherein the second portion of the cooling device
is coupled to a second surface of the second integrated circuit die
opposite the first surface of the second integrated circuit
die.
17. The semiconductor device of claim 15, wherein the first
integrated circuit die has a height that is greater than a height
of the second integrated circuit die, and wherein the first cavity
is coupled to the second cavity by a conformable material.
18. The semiconductor device of claim 15, further comprising a
system part coupled to the cooling device, the system part
comprising a case, a housing, or a chassis.
19. The semiconductor device of claim 15, wherein the molding
compound surrounds the first integrated circuit die and the second
integrated circuit die, the molding compound extending between the
first integrated circuit die and the second integrated circuit die,
the molding compound extending between the first integrated circuit
die and the cooling device and between the second integrated
circuit die and the cooling device.
20. The semiconductor device of claim 15, wherein a first plurality
of protrusions are disposed in the first cavity, and wherein a
second plurality of protrusions are disposed in the second cavity.
Description
BACKGROUND
Semiconductor devices are used in a variety of electronic
applications, such as personal computers, cell phones, digital
cameras, and other electronic equipment. Semiconductor devices are
typically fabricated by sequentially depositing insulating or
dielectric layers, conductive layers, and semiconductive layers of
material over a semiconductor substrate, and patterning the various
material layers using lithography to form circuit components and
elements thereon. Dozens or hundreds of integrated circuits are
typically manufactured on a single semiconductor wafer. The
individual dies are singulated by sawing the integrated circuits
along scribe lines. The individual dies are then packaged
separately, in multi-chip modules, or in other types of
packaging.
The semiconductor industry continues to improve the integration
density of various electronic components (e.g., transistors,
diodes, resistors, capacitors, etc.) by continual reductions in
minimum feature size, which allow more components to be integrated
into a given area. These smaller electronic components also require
smaller packages that utilize less area than packages of the past,
in some applications.
One type of smaller packages for semiconductor devices that has
been developed are wafer level packages (WLPs), in which integrated
circuits are packaged in packages that typically include a
redistribution layer (RDL) or post passivation interconnect (PPI)
that is used to fan-out wiring for contact pads of the package so
that electrical contacts may be made on a larger pitch than contact
pads of the integrated circuit. WLPs are often used to package
integrated circuits (ICs) demanding high speed, high density, and
greater pin count, as examples.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the
following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
FIGS. 1 through 3 are cross-sectional views that illustrate a
method of coupling a cooling device to a packaged semiconductor
device in accordance with some embodiments of the present
disclosure.
FIGS. 4 and 5 are cross-sectional views showing a portion of a
cooling device in accordance with some embodiments.
FIG. 6 is a more detailed view of FIG. 5 that illustrates some
dimensions of protruding features and plates of the cooling device
in accordance with some embodiments.
FIG. 7 is a cross-sectional view showing a portion of a cooling
device in accordance with some embodiments.
FIG. 8 shows various shapes of protruding features of a cooling
device in top or bottom views in accordance with some
embodiments.
FIGS. 9 and 10 illustrate perspective views of protruding features
of a cooling device in accordance with some embodiments.
FIG. 11 is a cross-sectional view that illustrates a cooling
principle of a cooling device in accordance with some
embodiments.
FIG. 12 shows a more detailed view of a portion of FIG. 11 in
accordance with some embodiments.
FIGS. 13 and 14 are cross-sectional views that illustrate phase
changes of a phase change material (PCM) of a cooling device in
accordance with some embodiments.
FIG. 15 is a cross-sectional view that shows a packaged
semiconductor device that includes a cooling device coupled thereto
being coupled to a system part in accordance with some
embodiments.
FIG. 16 is a top view of a portion of the packaged semiconductor
device shown in FIG. 15 that illustrates hot spots on an integrated
circuit die in accordance with some embodiments.
FIG. 17 is a cross-sectional view that shows a packaged
semiconductor device that includes two integrated circuit dies
being coupled to a cooling device and system part in accordance
with some embodiments.
FIG. 18 is a top view showing two regions of the cooling device
shown in FIG. 17 in accordance with some embodiments.
FIG. 19 is a cross-sectional view of the two regions of the cooling
device shown in FIG. 18 in accordance with some embodiments.
FIG. 20 is a cross-sectional view that shows a cooling device that
is integrated with a heat sink being coupled to a packaged
semiconductor device in accordance with some embodiments.
FIG. 21 illustrates a cross-sectional view of a cooling device that
includes a conformable member in accordance with some
embodiments.
FIG. 22 shows a cross-sectional view of a cooling device that is
coupled to a heat pipe in accordance with some embodiments.
FIG. 23 is a cross-sectional view illustrating a cooling device
coupled to a packaged semiconductor device that includes a
plurality of horizontally and vertically packaged integrated
circuit dies in accordance with some embodiments.
FIG. 24 is a flow chart that illustrates a method of packaging a
semiconductor device in accordance with some embodiments.
FIG. 25 is a block diagram that illustrates a method of disposing a
PCM in a cooling device in accordance with some embodiments.
FIG. 26 is a cross-sectional view that shows a cooling device
coupled to a package-on-package (POP) device in accordance with
some embodiments.
FIGS. 27 and 28 are graphs that illustrate simulation results for
PCM properties in accordance with some embodiments of the present
disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or
examples, for implementing different features of the provided
subject matter. Specific examples of components and arrangements
are described below to simplify the present disclosure. These are,
of course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
Further, spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element or feature's relationship to
another element(s) or feature(s) as illustrated in the figures. The
spatially relative terms are intended to encompass different
orientations of the device in use or operation in addition to the
orientation depicted in the figures. The apparatus may be otherwise
oriented (rotated 90 degrees or at other orientations) and the
spatially relative descriptors used herein may likewise be
interpreted accordingly.
Cooling devices, packaged semiconductor devices, and methods of
packaging semiconductor devices are disclosed in the present
disclosure. The cooling devices comprise portable heat reservoirs
or heat reservoir bags that are implementable in portable
electronic equipment, such as cellular phones, smart phones,
tablets, notebooks, and other applications. The cooling devices are
implementable on packaged semiconductor devices that may comprise
one substrate attached to another substrate, wherein each substrate
may be a die, wafer, printed circuit board, packaging substrate, or
the like. The cooling devices thereby allowing for cooling of
die-to-die, wafer-to-die, wafer-to-wafer, die or wafer to printed
circuit board or packaging substrate types of packaging, or the
like. Throughout the various views and illustrative embodiments,
like reference numerals are used to designate like elements.
FIGS. 1 through 3 are cross-sectional views that illustrate a
method of coupling a cooling device 120 (see FIG. 3) to a packaged
semiconductor device 100 at various stages in accordance with some
embodiments of the present disclosure. Referring first to FIG. 1, a
packaged semiconductor device 100 is provided that includes an
integrated circuit die 110 that has been packaged. The packaged
semiconductor device 100 includes an interconnect structure 112
coupled to the integrated circuit die 110, and a molding material
114 disposed around the integrated circuit die 110 and over the
interconnect structure 112. The packaged semiconductor device 100
comprises fan-out structures in some embodiments. For example,
conductive wiring of the interconnect structure 112 may be spaced
apart farther than conductive wiring of the integrated circuit die
110 is spaced. Likewise, the footprint of contact pads of the
interconnect structure 112 may be larger than the footprint of
contacts (not shown) of the integrated circuit die 110. The
packaged semiconductor device 100 comprises an integrated fan-out
(InFO) device or a WLP device in some embodiments. The packaged
semiconductor device 100 may also comprise other types of
packages.
The integrated circuit die 110 may comprise a substrate having
electrical circuitry formed within or thereon. The substrate may
comprise, for example, doped or undoped bulk silicon or an active
layer of a semiconductor-on-insulator (SOI) substrate. The
electrical circuitry of the substrate of the integrated circuit die
110 may be any type of circuitry suitable for a particular
application. The integrated circuit die 110 may comprise a logic,
memory, processor, or other type of device. As other examples,
electrical circuitry formed within or on the substrate of the
integrated circuit die 110 may include various N-type metal-oxide
semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS)
devices, such as transistors, capacitors, resistors, diodes,
photo-diodes, fuses, and the like, that are interconnected to
perform one or more functions. The functions may include memory
structures, logic structures, processing structures, sensors,
amplifiers, power distribution, input/output circuitry, and/or the
like. One of ordinary skill in the art will appreciate that the
above examples are provided for illustrative purposes to further
explain applications of some illustrative embodiments and are not
meant to limit the disclosure in any manner. Other circuitry may be
used as appropriate for a given application. The integrated circuit
die 110 typically has been fabricated by forming a plurality of the
integrated circuit dies 110 on a semiconductor wafer, and
singulating the individual integrated circuit dies 110 along scribe
lines.
A packaging process for the integrated circuit die 110 in some
embodiments comprises providing a carrier (not shown), and
attaching the integrated circuit die 110 to the carrier. The
carrier may comprise a wafer, tape, or other type of support,
substrate, or device that may be used for the packaging process as
a platform for packaging one or more integrated circuit dies 110.
The carrier is later removed after packaging a plurality of the
integrated circuit dies 110 in some embodiments, for example.
In some embodiments, through-vias (not shown in FIGS. 1 through 3;
see through-vias 142 shown in FIG. 23) are also formed over the
carrier. The through-vias 142 may be plated on a seed layer formed
on the carrier, for example. In some embodiments, through-vias 142
are not included. A plurality of the through-vias 142 may be formed
in some embodiments over the carrier by plating, lithography, or
other methods, before or after the plurality of the integrated
circuit dies 110 is coupled to the carrier. The plurality of
through-vias 142 may be formed using an electro-plating process, by
depositing a seed layer over the carrier, and forming a patterned
mask with a desired pattern for the through-vias 142 over the seed
layer. The through-vias 142 are plated onto the carrier through the
patterned mask, and the patterned mask is then removed. The exposed
portions of the seed layer are also removed. The through-vias 142
may comprise copper, a copper alloy, or other metals or conductive
materials. Dozens or hundreds of through-vias 142 may be included
in a package for each of the integrated circuit dies 110 or groups
of integrated circuit dies 110 that are packaged together, for
example. The plurality of through-vias 142 provides electric
connections in a vertical direction for the packaged semiconductor
devices 100 in some embodiments. Each of the plurality of
through-vias 142 may be positioned so that they will be coupled to
a conductive portion of the interconnect structure 112 that will
later be formed, for example.
A plurality of the integrated circuit dies 110 is coupled to the
carrier between some of the plurality of through-vias 142 in some
embodiments. The plurality of integrated circuit dies 110 is
coupled to the carrier using a die attach film (DAF) (not shown)
disposed on a bottom surface of the integrated circuit dies 110.
The plurality of integrated circuit dies 110 may be placed on the
carrier using a pick-and-place machine or manually, for example.
Only one integrated circuit die 110 is shown in the drawings; in
some embodiments, a plurality of the integrated circuit dies 110 is
coupled to the carrier and is packaged simultaneously. The
integrated circuit dies 110 or two or more integrated circuit dies
110 are later singulated along scribe lines (i.e., of the package
or interconnect structure 112) to form a plurality of packaged
semiconductor devices 100.
The molding material 114 is then formed over the carrier, over the
integrated circuit die 110 and the through-vias 142, in embodiments
wherein the through-vias 142 are included. The molding material 114
may comprise a molding compound comprised of an insulating
material, such as an epoxy, a filler material, a stress release
agent (SRA), an adhesion promoter, other materials, or combinations
thereof, as examples. The molding material 114 may comprise a
liquid or gel when applied so that it flows between a plurality of
integrated circuit dies 110 being simultaneously packaged and
around the through-vias 142, in some embodiments. The molding
material 114 is then cured or allowed to dry so that it forms into
a solid. A molding compound clamp may be applied during a curing
process and a plasma treatment process of the molding material 114
in some embodiments. In some embodiments, as deposited, the molding
material 114 extends over top surfaces of the plurality of
integrated circuit dies 110 and the through-vias 142, and after the
molding material 114 is applied, a top portion of the molding
material 114 is removed using a planarization process, such as a
chemical mechanical polish (CMP) process, a grinding process, an
etch process, or combinations thereof, as examples. Other methods
may also be used to planarize the molding material 114. A top
portion of the integrated circuit dies 110 and/or through-vias 142
may also be removed during the planarization process for the
molding material 114. In some embodiments, an amount of the molding
material 114 applied may be controlled so that top surfaces of the
integrated circuit die 110 and through-vias 142 are exposed. Other
methods may also be used to form the molding material 114.
The interconnect structure 112 may then be formed over the
planarized molding material 114, the integrated circuit dies 110,
and the through-vias 142. The interconnect structure 112 comprises
an RDL or PPI in some embodiments. The interconnect structure 112
may include one, two, or several conductive line layers and via
layers. Some of the conductive lines of the interconnect structure
112 are coupled to contact pads (not shown) of the integrated
circuit die 110. The conductive features or wiring of the
interconnect structure may comprise copper, a copper alloy, or
other metals formed by plating processes, lithography processes,
and/or other methods formed within one or more insulating material
layers, in some embodiments.
The carrier wafer is then removed. In some embodiments, a plurality
of the packaged semiconductor devices 100 is then singulated to
form the packaged semiconductor device 100 shown in FIG. 1 (for
example, in an inverted view, with the interconnect structure 112
at the bottom). The packaged semiconductor devices 100 may be
singulated using a saw or laser (not shown), which may include a
blade comprising diamond or other materials in some embodiments,
for example. One or more carriers may be used to package a
semiconductor device.
In some embodiments, the interconnect structure 112 comprises a
first interconnect structure formed on a first side of the
integrated circuit die 110, and a second interconnect structure
(not shown) is formed in addition to the first interconnect
structure 112 on a second side of the integrated circuit die 110,
the second side being opposite the first side, before singulating a
plurality of the packaged semiconductor devices 100. For example,
the previously described carrier may comprise a first carrier, and
after the formation of the first interconnect structure 112, a
second carrier may be attached to the first interconnect structure.
The first carrier is removed, and the second interconnect structure
is formed over the second side of the integrated circuit die 110,
the through-vias 142, and the molding material 114. The second
carrier is then removed, and the packaged semiconductor devices 100
are then singulated. The first interconnect structure 112 and the
second interconnect structure may provide electrical connections in
a horizontal direction for a plurality of packaged semiconductor
devices 100 in some embodiments, for example. The second
interconnect structure may comprise back-side routing, and the
first interconnect structure 112 comprises front-side routing, or
vice versa, e.g., relative to the integrated circuit die 110, for
the packaged semiconductor devices 100 in some embodiments.
The methods of packaging semiconductor devices using one or more
carriers described herein is merely an example: the integrated
circuit dies 110 may be packaged using different methods or orders
of methods of a packaging process.
In some embodiments, the packaged semiconductor device 100 is
coupled to a substrate or printed circuit board (PCB) 102 by a
plurality of connectors 104, as shown in FIG. 1. The connectors 104
may comprise a eutectic material such as solder, and the connectors
104 may be arranged in a ball grid array (BGA) that is fully or
partially populated, for example. The use of the word "solder"
herein includes both lead-based and lead-free solders, such as
Pb--Sn compositions for lead-based solder; lead-free solders
including InSb; tin, silver, and copper ("SAC") compositions; and
other eutectic materials that have a common melting point and form
conductive solder connections in electrical applications. For
lead-free solder, SAC solders of varying compositions may be used,
such as SAC 105 (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405,
as examples. Lead-free conductive materials such as solder balls
may be formed from SnCu compounds as well, without the use of
silver (Ag). Lead-free solder connectors 104 may also include tin
and silver, Sn--Ag, without the use of copper. In some embodiments,
the connectors 104 may comprise solder bumps or solder balls, as
examples. The connectors 104 comprise conductive balls having a
shape of a partial sphere in some embodiments. The connectors 104
may also comprise other shapes, such as non-spherical conductive
connectors, for example. In some embodiments, the connectors 104
may comprise metal pillars (such as a copper pillars) formed by a
sputtering, printing, electro plating, electroless plating,
chemical vapor deposition (CVD), or the like. The metal pillars may
be solder free and have substantially vertical sidewalls. In some
embodiments, a metal cap layer (not shown) is formed on the top of
the metal pillar connectors 104. The metal cap layer may include
nickel, tin, tin-lead, gold, silver, palladium, indium,
nickel-palladium-gold, nickel-gold, the like, or a combination
thereof and may be formed by a plating process. The connectors 104
may also be used to couple the packaged semiconductor device 100 to
other types of devices, such as to another packaged semiconductor
device, an unpackaged semiconductor device, or directly in an end
application, as examples.
In some embodiments, the interconnect structure 112 of the packaged
semiconductor device 100 is coupled to the substrate or PCB 102
using the plurality of connectors 104, as illustrated in FIG. 1.
The connectors 104 are coupled between contact pads (not shown) on
the substrate or PCB 102 and contact pads of the interconnect
structure 112. The connectors 104 are coupled to the contact pads
of the substrate or PCB 102 by aligning the connectors 104 with the
contact pads of the substrate or PCB 102, and heating the
connectors 104 to the melting point of the eutectic material of the
connectors 104, which reflows the material of the connectors 104.
The material of the connectors 104 is allowed to cool, leaving the
connectors 104 electrically and mechanically coupled to the contact
pads of the substrate or PCB 102, and coupling the packaged
semiconductor device 100 to the substrate or PCB 102.
An underfill material 106 may be applied between the connectors 104
and between the interconnect structure 112 and the substrate or PCB
102. The underfill material 106 may comprise a similar material as
described for the molding material 114, for example. The underfill
material 106 may be dispensed along one or more sides of the
interconnect structure 112 along edge connectors 104, for example,
and the underfill material 106 flows beneath the packaged
semiconductor device 100 to the other side(s). The underfill
material 106 is then cured or allowed to cure. In some embodiments,
the underfill material 106 is not included.
In other embodiments, the packaged semiconductor device 100 is not
coupled to a substrate or PCB 102, as shown in the embodiments
illustrated in FIGS. 23 and 26, which will be described further
herein. Likewise, the embodiments illustrated in FIGS. 1 through 3
and some of the other embodiments illustrated in the present
disclosure may not be coupled to a substrate or PCB 102.
The integrated circuit die 110 may include hot spots 108 that
become heated during operation. In accordance with some embodiments
of the present disclosure, heat from the hot spots 108 is
dissipated by implementing a cooling device 120 attached to the
packaged semiconductor device 100, as shown in FIG. 3, which will
be described further herein.
To attach the cooling device 120, a thermal interface material
(TIM) 116 is applied to a top surface of the integrated circuit die
110 and a top surface of the molding material 114 in some
embodiments, as illustrated in FIG. 2. The TIM 116 may comprise a
polymer material or a solder material. In embodiments wherein the
TIM 116 comprises a polymer material, the polymer material polymer
material may form as a matrix-based polymer or an inorganic
material such as a lightly crosslinked silicone polymer, one or
more matrix polymers, a polymer with one or more thermally
conductive fillers, as examples. The TIM 116 may comprise a
thickness of about 20 .mu.m to about 150 .mu.m, as examples. The
TIM 116 may also comprise other materials and dimensions. The TIM
116 may be applied by dispensing the TIM 116 onto the top surface
of the integrated circuit die 110 and molding material 114. The
dispensing process may be conducted using automatic dispenser
equipment which may control the TIM 116 dispensing volume and
patterns, such as serpentine, spiral, or other patterns, in order
to achieve full coverage and a desired TIM 116 bond line thickness.
The TIM 116 may also be applied using other methods. In some
embodiments, the TIM 116 is applied to the cooling device 120, as
shown in FIG. 17.
Referring next to FIG. 3, the cooling device 120 is coupled to the
TIM 116 using an automated pick-and-place machine or equipment, or
other methods. The cooling device 120 is coupled to the integrated
circuit die 110 and the molding material 114 by the TIM 116 in some
embodiments, for example. The cooling device 120 comprises a
reservoir with a cavity inside (not shown in FIG. 3; see cavity 121
shown in FIG. 4) that contains a phase change material (PCM) 122.
The PCM 122 comprises a high heat storage material, for example, in
some embodiments. The PCM 112 may comprise heat storage properties
with a latent heat of fusion larger than about 100 kJ/kg, for
example. The PCM 122 may also comprise other levels of heat storage
properties. The PCM 122 is adapted to change phase, such as between
solid and a liquid, a liquid and a gas, or a solid and a gas. The
PCM 122 may also be adapted to change phase between other
states.
The PCM 122 comprises a material that changes phase at a relatively
low melting point, such as about 100 degree C. or less, about 5
degrees C. to about 80 degrees C., or about 50 degrees C. or less,
as examples. The PCM 122 may also be adapted to change phase at
other temperatures. The PCM 122 may comprise wax, water, salt
water, Agarose gel, N-Tetradeca, Formic Acid, N-Pentadeca, Acetic
Acid, N-Hexadeca, Caprilone, Docasyle, N-Henicosan, Phenol,
N-Lauric, P-Joluidine, Cynamide, N-Docosane, N-Tricosane,
Hydrocinna, Cetyl, O-Nitroanili, Camphene, Diphenyl, N-Penta
Cosane, Myristic Acid, Oxolate, Tristearin, O-Xylene,
.beta.-Chloroacetic, N-Hexacosane, Nitro Naphthalene,
.alpha.-Chloroacetic, N-Octacosane, Palmitic Acid, Bees Wax,
Glyolic Acid, P-Bromophenol, Azobenzene, Acrylic Acid, Dintro
Toluene, Phenylacetic Acid, Thiosinamine, or a combination thereof,
in some embodiments. The PCM 122 comprises a material having a
relatively low melting temperature, such as less than about 50
degrees C. to about 100 degrees C. in some embodiments. The PCM 122
may comprise a material that is adapted to store a relatively large
amount of heat per unit mass and volume and that is adapted to
enable a phase change effect in some embodiments, as another
example. The PCM 122 may also comprise other materials and
properties.
The PCM 122 is applied inside the cavity 121 of the reservoir of
the cooling device 120 through an opening 123 that is later closed
or plugged with a plug 125 in some embodiments. The plug 125 is
adapted to retain the PCM 122 within the cavity. The cooling device
120 advantageously provides cooling and thermal dissipation for the
hot spot 108 of the integrated circuit die 110. The cooling device
120 is adapted to dissipate heat from the integrated circuit die
110, the interconnect structure 112, and/or the molding material
114 in some embodiments, for example.
FIGS. 4 and 5 are cross-sectional views showing a portion of a
cooling device 120 in accordance with some embodiments. The cooling
device 120 includes a first plate 118a and a second plate 118b
coupled to the first plate 118a. Edges of the first plate 118a and
the second plate 118b are coupled together to form a reservoir
having a cavity 121 between the two plates 118a and 118b. The PCM
122 is disposed between the first plate 118a and the second plate
118b within the cavity 121. The first plate 118a and the second
plate 118b of the cooling device 120 may comprise a metal or a
semiconductive material in some embodiments. The first plate 118a
and the second plate 118b may comprise Cu, Cu/Ni, or Si, as
examples. The first plate 118a and the second plate 118b may
comprise relatively high thermal conductivity materials in some
embodiments, for example, such as having a thermal conductivity of
Si or greater. In some embodiments, the first plate 118a and the
second plate 118b comprise a conformable material. A surface
topology of the first plate 118a and the second plate 118b is
adapted to conform to a surface of a package or packaged
semiconductor device 100 in some embodiments, for example. The
first plate 118a and the second plate 118b may also comprise other
materials and properties.
The first plate 118a and/or the second plate 118b comprises a
plurality of protruding features 126a or 126b, respectively,
disposed thereon, in some embodiments. For example, in FIG. 4, the
second plate 118b comprises a plurality of protruding features 126b
that extend towards the first plate 118a. In FIG. 5, both the first
plate 118a and the second plate 118b comprise a plurality of
protruding features 126a or 126b, respectively, disposed thereon.
The first plate 118a comprises a plurality of protruding features
126a that extend towards the second plate 118b, and the second
plate 118b comprises a plurality of protruding features 126b that
extend towards the first plate 118a. In some embodiments,
protruding features 126a/126b are not included on the first plate
118a or the second plate 118b. The protruding features 126a/126b
assist in heat dissipation of the cooling device 120 in some
embodiments by, for example, increasing the surface area of the
plates 118a/118b.
In some embodiments, the PCM 122 includes a filler material 124, as
illustrated in FIGS. 4 and 5. The filler material 124 comprises a
material that does not change phase in some embodiments. The filler
material 124 may comprise indium, silver, tin, copper, bismuth
particles, or a combination thereof, as examples. The filler
material 124 may also comprise other materials. In some
embodiments, a filler material 124 is not included in the PCM 122.
The filler material 124 is combined with the phase change material
of the PCM 122 in some embodiments, for example.
FIG. 6 is a more detailed view of FIG. 5 that illustrates some
dimensions of the protruding features 126a and 126b and the plates
118a and 118b of the cooling device 120, and the cooling device
120, in accordance with some embodiments. The protruding features
126a and 126b may have a height comprising dimension A, wherein
dimension A comprises about 10 .mu.m to about 1,000 .mu.m in some
embodiments. The first plate 118a (and also the second plate 118b)
may comprise a thickness comprising dimension B, wherein dimension
B comprises about 50 .mu.m to about 2,000 .mu.m in some
embodiments. The overall thickness of the cooling device 120 may
comprise a thickness comprising dimension C, wherein dimension C
comprises about 150 .mu.m to about 4,000 .mu.m in some embodiments.
In some embodiments, dimension C comprises about 0.6 mm or less, as
another example. The protruding features 126a and 126b may have a
width comprising dimension D, wherein dimension D comprises about 5
.mu.m to about 500 .mu.m in some embodiments. The protruding
features 126a and 126b may be spaced apart from adjacent protruding
features 126a and 126b by a distance comprising dimension E,
wherein dimension E comprises about 5 .mu.m to about 500 .mu.m in
some embodiments. Dimensions A, B, C, D, and E may also comprise
other values.
FIG. 6 also illustrates at 120' that edges of the first plate 118a
and the second plate 118b of the cooling device 120 are coupled
together. The cooling device 120 is formed using mechanical
forging, sintered powder, or pressing methods in some embodiments,
as examples. Thus, the first plate 118a and the second plate 118b
comprise a continuous piece of material having a flask-like or
flattened container shape in some embodiments. The exterior portion
of the cooling device 120 comprises a sealed assembly of the first
plate 118a and the second plate 118b, for example. The cooling
device 120 is hermetically sealed in some embodiments, for example.
The cooling device 120 may also be formed using other methods. In
some embodiments, the opening 123 (see FIG. 3) may be located
proximate an edge of the first plate 118a, proximate an edge of the
second plate 118b, or proximate both an edge of the first plate
118a and an edge of the second plate 118b (see FIG. 25 at 123'),
for example. The edges of the first plate 118a and the second plate
118b may be sealed except at the opening 123 or 123' in some
embodiments, for example (not shown).
In FIGS. 5 and 6, the protruding features 126a and 126b are
aligned. FIG. 7 is a cross-sectional view showing a portion of a
cooling device 120 in accordance with some embodiments, wherein the
protruding features 126a and 126b of the first plate 118a and the
second plate 118b, respectively, are staggered.
FIG. 8 is a top view (or bottom view) showing some exemplary shapes
of protruding features 126a and 126b of a cooling device 120 in
accordance with some embodiments. The protruding features 126a and
126b may comprise a shape of a square, rectangle, circle, cross,
ring, trapezoid, L, or mesh, in a top or bottom view, as examples.
The protruding features 126a and 126b may also comprise other
shapes in a top or bottom view of the cooling device 120.
FIGS. 9 and 10 illustrate perspective views of protruding features
126b of a second plate 118b of a cooling device 120 in accordance
with some embodiments. In FIG. 9, the protruding features 126b of
the second plate 118b of the cooling device 120 comprise a
plurality of square or rectangular shaped features, and in FIG. 10,
the protruding features 126b of the second plate 118b of the
cooling device 120 comprise a plurality of cylindrical shaped
features. Likewise, protruding features 126a of a first plate 118a
of the cooling device 120 may comprise similar shapes. The
protruding features 126a and 126b may also comprise other shapes in
a perspective view.
FIG. 11 is a cross-sectional view that illustrates a cooling
principle of the cooling device 120 in accordance with some
embodiments. As a hot spot 108 of the integrated circuit die 110 of
the packaged semiconductor device 100 becomes hot during operation,
heat 128 generated from the hot spot 108 dissipates through the TIM
116 to the second plate 118b of the cooling device 120. FIG. 12 is
a more detailed view of a portion of FIG. 11 in accordance with
some embodiments, illustrating the heat 128 transferred to the
second plate 118b and dissipating through the protruding features
126b and a base of the second plate 118b from which the protruding
features 126b extend. The protruding features 126b advantageously
increase a surface area of the second plate 118b and improve the
heat 128 transfer from the hot spot 108 to the PCM 122. The second
plate 118b and the protruding features 126b of the second plate
118b dissipate the heat 128 to the PCM 122, which changes the phase
of the PCM 122, i.e., melting the PCM 122 (e.g., changing a solid
to a liquid) or changing a solid or liquid to a gas, depending on
the material of the PCM 122. The phase change of the PCM 122 also
results in a cooling or reduction in temperature of the hot spot
108 of the integrated circuit die 110.
The PCM 122 comprises a latent heat storage material, for example.
As the PCM 122 is exposed to an increase in temperature such as the
heat 128, the chemical bonds within the PCM 122 break up as the
material changes phase. The phase change is a heat-seeking
(endothermic) process and thus, the PCM 122 absorbs the heat 128.
Upon storing the heat 128 in the PCM 122, which functions as a heat
storage material, the PCM 122 begins to change phase when the phase
change temperature is reached. The temperature of the PCM 122 then
remains substantially constant until the phase change process is
finished. After reaching a phase change condition, the PCM 122
stays in the phase change state (e.g., such as a liquid state)
until the device temperature cools down below the melting point, at
which point the PCM 122 begins to transform back to the non-phase
change state (e.g., such as a solid state). The PCM 122 is then
ready to store heat for another device heating cycle. Thus, the PCM
122 absorbs the heat 128, which results in the cooling of the hot
spot 108.
FIGS. 13 and 14 further illustrate phase changes of a PCM 122 of a
cooling device in accordance with some embodiments, in some
embodiments wherein the PCM 122 comprises a material with a solid
or liquid to gas phase change. A phase-change heat transfer occurs
during the phase change of the PCM 122, for example. In FIG. 13,
when a hot spot 108 proximate the second plate 118b and protruding
features 126b of the second plate 118b increases in temperature, a
capillary flow is generated in the PCM 122, and the PCM 122 becomes
more fluid and eventually at least part gas or vapor phase. After
the hot spot 108 has cooled from the phase change, the PCM 122
returns to the original solid or liquid state, due to condensation
during the cooling process, as shown in FIG. 14. Other phase
changes may take place during the heating and cooling of the hot
spot 108, depending on the material of the PCM 122, such as solid
to liquid back to solid, for example.
In FIGS. 4 through 7 and 14, a PCM 122 is shown in the drawings
that substantially fills the cavity 121. However, in accordance
with some embodiments of the present disclosure, the PCM 122 volume
when in a solidified or liquid state comprises about 30% to 80% of
the cavity 121 volume, to allow for expansion during a phase change
to a liquid state or gas/vapor state within the cavity 121. For
example, the cavity 121 may comprise a first volume, and the PCM
122 in a non-phase-changed state may comprise a second volume,
wherein the second volume comprises about 30% to 80% of the first
volume.
FIG. 15 is a cross-sectional view that shows a packaged
semiconductor device 100 that includes a cooling device 120 coupled
thereto being coupled to a system part 130 of a system 131 in
accordance with some embodiments. The system part 130 may comprise
a case, chassis, or housing in some embodiments. The system part
130 may also comprise other components or elements of the system
131. In some embodiments wherein the cooling device 120 is
implemented in a hand-held device (which is also referred to herein
generally as a system 131), the system part 130 may comprise a case
or housing of the hand-held device or system 131, for example. The
cooling device 120 includes a first side and a second side opposite
the first side. The first side of the cooling device 120 is coupled
to the integrated circuit die 110 and the molding material 114, and
the second side of the cooling device 120 is coupled to the system
part 130 of the system 131.
In some handheld applications, a term T.sub.skin is sometimes used,
which refers to a temperature of a portion of a handheld device
such as a case, chassis, or housing that may have physical contact
with human skin. The maximum temperature for T.sub.skin is
sometimes referred to as Max Tskin, which refers to a maximum
allowable temperature of the portion of the device that human skin
can tolerate to avoid discomfort while holding or wearing the
device, for example. The value of Max T.sub.skin that is sometimes
used is 45 degrees C., for example. An advantage of some
embodiments of the present disclosure in the implementation of the
cooling device 120 in a handheld electronic device or system 131 is
that maintaining a temperature of Max T.sub.skin or less may be
achieved of a system part 130 such as a case, chassis, or housing,
without degrading integrated circuit die 110 performance. Thermal
run-away of integrated circuit dies 110 from hot spots 108 and
thermal cross-talk may be avoided by implementing the cooling
devices 120 described herein, and improved electrical performance
and reliability may be achieved. The cooling device 120 thermally
contacts an exposed integrated circuit die 110 in some of the
embodiments shown herein, for example. The cooling device 120 may
provide improved heat conduction and more effective integrated
circuit die 110 transient cooling, as another example.
FIG. 15 also illustrates a gap filler material 132 that may be
coupled between the system part 130 and the cooling device 120 in
some embodiments. The gap filler material 132 may comprise a TIM
such as a grease, a gel, or an elastomer, as examples, or other
materials. In other embodiments, the gap filler material 132 is not
included. A first side of the cooling device 120 is coupled to the
integrated circuit die 110 and the molding material 114, and a
second side of the cooling device 120 is coupled to a system part
130 of the system 131 by the gap filler material 132 in some
embodiments, for example.
An adhesive 134 such as an epoxy, a glue, a thermally conductive
adhesive, or other materials may also be disposed between the
molding material 114 and the cooling device 120 in some
embodiments. The adhesive 134 may comprise a thickness of about 10
.mu.m to about 100 .mu.m, for example. The adhesive 134 may also
comprise other dimensions. The TIM 116 is disposed between the
integrated circuit die 110 and the cooling device 120. In other
embodiments, the adhesive 134 is not included, and the TIM 116 is
also disposed between the molding material 114 and the cooling
device 120, as shown in FIG. 3.
FIG. 16 is a top view of a portion of the packaged semiconductor
device 100 shown in FIG. 15 along a view shown at 15-15' in FIG.
15, illustrating hot spots 108 on an integrated circuit die 110 in
accordance with some embodiments. One or more hot spots 108 may
reside in regions of an integrated circuit die 110 of a packaged
semiconductor device 100 in some applications, for example. The hot
spots 108 may occur because of increased current flow or
chip-consuming power to activate the circuitry of the integrated
circuit die 110 in those regions while executing different
operation workloads, for example. The cooling device 120
advantageously provides cooling for, and heat diffusion and
transfer, away from the hot spots 108 of the integrated circuit die
110.
FIG. 17 is a cross-sectional view illustrating a packaged
semiconductor device 100 that includes two integrated circuit dies
110a and 110b that is being coupled to a cooling device 120 in
accordance with some embodiments. In accordance with some
embodiments, different materials may be used for the PCM 122 within
the cooling device 120 for each of the integrated circuit dies 110a
and 110b. FIG. 18 is a top view showing two regions of the cooling
device 120 shown in FIG. 17, and FIG. 19 is a cross-sectional view
of the two regions of the cooling device 120 shown in FIG. 18 in
accordance with some embodiments. The cooling device 120 includes
two cavities 121a and 121b with a different PCM 122a and 122b,
respectively, disposed within each cavity 121a and 121b in the two
regions, respectively. The PCMs 122a and 122b may also include a
filler material 124a and 124b, respectively. In other embodiments,
a filler material 124a and/or 124b is not included.
Thus, in some embodiments, a cooling device 120 for a semiconductor
device includes a reservoir comprising a first plate 118a and a
second plate 118b coupled to the first plate 118a, and a first
cavity 121a disposed between the first plate 118a and the second
plate 118b. A first PCM 122a is disposed in the first cavity 121a.
The cooling device 120 comprises a second cavity 121b disposed
between the first plate 118a and the second plate 118b, and a
second PCM 122b disposed in the second cavity 121b. The second PCM
122b comprises a different material than the first PCM 122a in some
embodiments.
Some of the embodiments shown in FIGS. 17 through 19 enable
different heat dissipation rates or amounts and different cooling
rates for the various integrated circuit dies 110a and 110b of the
packaged semiconductor device 100. The first PCM 122a may comprise
wax and the second PCM 122b may comprise water, as an example. The
cooling device 120 may also comprise three or more regions that
have two or more different PCMs in the various regions,
corresponding to cooling requirements for three or more integrated
circuit dies 110 included in a packaged semiconductor device 100,
for example.
In some embodiments, the second PCM 122b may comprise the same
material as the first PCM 122a. In other embodiments, the first PCM
122a may include a filler material 124a, and the second PCM 122b
may not include a filler material, as another example. The first
PCM 122a and the second PCM 122b may advantageously be custom
designed to provide adequate cooling for the respective integrated
circuit dies 110a and 110b that will be positioned proximate the
cavities 121a and 121b, respectively, in the packaged semiconductor
device 100 and/or the system 131, in some embodiments.
FIG. 17 also illustrates that the cooling device 120 may first be
coupled to the system part 130, and the TIM 116 may be applied to
the cooling device 120, in some embodiments. The TIM 116 is then
coupled to the integrated circuit dies 110a and 110b and the
molding material 114. FIG. 17 further illustrates that a portion of
the molding material 114 may reside over top surfaces of an
integrated circuit die or dies 110a and 110b, in some
embodiments.
FIG. 20 is a cross-sectional view that shows a cooling device 120
that is integrated with a heat sink 136 that is being coupled to a
packaged semiconductor device 100 in accordance with some
embodiments. Note that in FIGS. 15 and 17, the systems 131 are
shown at a stage in which they are in the process of being
assembled. After the connections indicated by the arrows, the gap
including the arrows has been removed and the elements of the
system 131 are connected vertically. Likewise, the system 131 shown
in FIG. 20 including the heat sink 136 comprises elements that are
connected vertically after the connections indicated by the
arrows.
In FIG. 20, the cooling device 120 is an integral part of the heat
sink 136 in some embodiments, for example. The heat sink 136 may
comprise a material such a copper, aluminum, magnesium, or alloys
thereof, as examples. The heat sink 136 may comprise a thickness of
about 0.22 mm to about 2 mm in some embodiments. The heat sink 136
may also comprise other materials and dimensions.
For example, the heat sink 136 illustrated in FIG. 20 has a recess
formed therein, and the cooling device 120 is disposed within the
recess. The cooling device 120 is retained within the recess in the
heat sink 136 by an adhesive 137 comprising a thermal conductive
adhesive, an alloy soldering material, a combination thereof, or
other materials, as examples. The adhesive 137 may comprise a
thickness of about 50 .mu.m to about 200 .mu.m, for example. The
adhesive 137 may also comprise other dimensions. The overall
package or system 131 z-profile (e.g., in a z direction) may
advantageously be reduced by integrating the cooling device 120
into a heat sink 136 as illustrated in FIG. 20. Furthermore,
effective integrated circuit die 110 transient cooling is provided
by including the cooling device 120 in the heat sink 136.
FIG. 21 illustrates a cross-sectional view of a cooling device 120
that includes a conformable member 138 and that is implemented in a
system 131 in accordance with some embodiments. The system part 130
comprises a thicker portion proximate packaged semiconductor device
100a to accommodate for package height variations. The cooling
device 120 includes conformal thermal contact features, for
example. In some embodiments, the conformable member 138 comprises
a bendable region of the first plate 118a and the second plate
118b. The first plate 118a and the second plate 118b may comprise a
material that is conformable, for example. The first plate 118a and
second plate 118b may comprise a bending region that is fabricated
via a mechanical bending process with a molding tool in some
embodiments, for example. The first plate 118a and the second plate
118b may also comprise a material having a sufficient thickness so
that it is conformable, in some embodiments. Cooling devices 120
having thin first plate 118a and second plate 118b material may be
bendable in a packaging process line by an operator or a machine,
for example. The PCM 122 may be contained in a single cavity 121 as
described for the embodiments shown in FIGS. 3 through 7, or the
PCM 122a and 122b may be contained in two cavities 121a and 121b as
described for the embodiments shown in FIGS. 17 through 19.
In other embodiments, the conformable member 138 comprises an
elastomer sheet, elastomer membrane, or other conformable and
bendable material. The elastomer materials may comprise high
temperature polyimide films or other materials. For example,
polyimide may sustain a high temperature environment up to about
400 degrees C. The cooling device 120 may comprise a composite
cooling device comprised of two cooling portions, with each cooling
portion having a cavity 121a and 121b formed therein, respectively,
that contains the PCM 122. The PCM 122 may comprise the same
material in each cavity 121a and 121b as described for the
embodiments shown in FIGS. 3 through 7, or the PCM 122a and 122b
may comprise different materials in each cavity 121a and 121b,
respectively, as described for the embodiments shown in FIGS. 17
through 19.
Thus, in some embodiments, a first portion of the cooling device
120 comprising a first cavity 121a is coupled to a second portion
of the cooling device 120 comprising a second cavity 121b by a
conformable member 138. The first cavity 121a may comprise a first
PCM 122a, and the second cavity 121b may comprise a second PCM
122b. The first PCM 122a and the second PCM 122b may comprise the
same or different materials.
A cooling device 120 including a conformable member 138
advantageously provides an ability to accommodate multiple package
heights on the same substrate or PCB 102 within the system 131. For
example, in FIG. 21, packaged semiconductor device 100a and
connectors 104 comprise a height comprising dimension d.sub.1, and
packaged semiconductor device 100b and connectors 104 comprise a
height comprising dimension d.sub.2, wherein dimension d.sub.2 is
greater than dimension d.sub.1. Dimension d.sub.1 may comprise
about 100 .mu.m to about 500 .mu.m, and dimension d.sub.2 may
comprise about 100 .mu.m to about 800 .mu.m, as examples.
Dimensions d.sub.1 and d.sub.2 may also comprise other values. The
conformable member 138 also provides the ability to accommodate a
variety of shapes of the system part 130.
FIG. 21 also illustrates that two different types of packaged
semiconductor devices 100a and 100b may be coupled to a substrate
or PCB 102 in a system 131. Packaged semiconductor device 100a
includes one integrated circuit die 110a, as described for the
embodiments shown in FIG. 15. Packaged semiconductor device 100b
includes an integrated circuit die 110a that is packaged
horizontally with a stack of vertically stacked integrated circuit
dies 110c. Four integrated circuit dies 110c are shown in the
vertical stack; however, two, three, or five or more integrated
circuit dies 110c may be vertically stacked. Electrical connections
between the integrated circuit dies 110c may be made by contact
pads and/or through-vias, as examples. Other methods and structures
may also be used to establish vertical electrical connections
between the integrated circuit dies 110c. The interconnect
structure 112 of the packaged semiconductor device 100b may include
horizontal connections between integrated circuit die 110b and the
vertical stack of integrated circuit dies 110c, for example. The
substrate or PCB 102 may, or may not, include wiring that provides
horizontal electrical connections between the two packaged
semiconductor devices 100a and 100b within the system 131, for
example.
Thus, in accordance with some embodiments, a first packaged
semiconductor device 100a that includes the integrated circuit die
110a, the interconnect structure 112, and the molding material 114
is coupled to the cooling device 120, and a second packaged
semiconductor device 100b is also coupled to the cooling device
120. Additional packaged semiconductor devices (not shown) may also
be coupled to the cooling device 120 and may have different
heights, by the inclusion of the conformable members 138 in the
cooling device 120, in some embodiments.
FIG. 22 shows a cross-sectional view of a cooling device 120 that
is coupled to a heat pipe 140 in accordance with some embodiments.
A cooling device 120 described herein may be integrated with a heat
pipe 140, for example, by a conformable member 138 comprising an
elastomer sheet, an elastomer membrane, or other object or
material. A cooling device 120 including a conformable member 138
and coupled to a heat pipe 140 advantageously provides an ability
to accommodate multiple package heights on the same substrate or
PCB 102. The cooling device 120 may be coupled to a first packaged
semiconductor device 100a, and the heat pipe 140 may be coupled to
a second packaged semiconductor device 100b. Likewise, the cooling
device 120 may be coupled to a first integrated circuit die 110a,
and the heat pipe 140 may be coupled to a second integrated circuit
die 110b and/or 110c, in some embodiments.
In other embodiments, the heat pipe 140 may be coupled to the
cooling device 120 using a non-conformable member, not shown. The
cooling device 120 and the heat pipe 140 may also be coupled to the
same packaged semiconductor device 100a or 100b, for example, also
not shown.
FIG. 23 is a cross-sectional view illustrating a cooling device 120
coupled to a packaged semiconductor device 100 that includes a
plurality of horizontally and vertically packaged integrated
circuit dies 110 in accordance with some embodiments. The packaged
semiconductor device 100 may comprise an InFO hybrid vertical
stacking device in some of the embodiments shown, for example. The
packaged semiconductor device 100 includes two horizontally
positioned integrated circuit dies 110 that are disposed in a first
molding material 114 over an interconnect structure 112.
Through-vias 142 are formed in the first molding material 114
around the integrated circuit dies 110. An integrated circuit die
110 is vertically stacked over each of the horizontally positioned
circuit dies 110, and the vertically stacked integrated circuit
dies 110 are horizontally positioned within a second molding
material 114'. The cooling device 120 is coupled to the upper
integrated circuit dies 110 and the second molding material 114' by
the TIM 116. Thus, the cooling device 120 may be implemented in
packaged semiconductor devices 100 that include a plurality of
horizontally oriented integrated circuit dies 110, a plurality of
vertically stacked integrated circuit dies 110, or both a plurality
of horizontally oriented integrated circuit dies 110 and a
plurality of vertically stacked integrated circuit dies 110, in
accordance with some embodiments.
FIG. 24 is a flow chart 150 of a method of packaging a
semiconductor device in accordance with some embodiments of the
present disclosure. In step 152, an integrated circuit die 110 is
provided. In step 154, the integrated circuit die 110 is coupled to
an interconnect structure 112. In step 156, a molding material 114
is formed around the integrated circuit die 110 and over the
interconnect structure 112. In step 158, a cooling device 120 is
coupled to the integrated circuit die 110 and the molding material
114, the cooling device 120 including a reservoir having a first
plate 118a and a second plate 118b coupled to the first plate 118a,
a cavity 121 disposed between the first plate 118a and the second
plate 118b, and a PCM 122 disposed in the cavity 121, wherein the
cooling device 120 is adapted to dissipate heat 128 from the
integrated circuit die 110, the interconnect structure 112, or the
molding material 114.
Dissipating heat from a hot spot 108 of an integrated circuit die
or dies 110 is described herein. The interconnect structure 112 may
also generate hot spots during operation, and the heat from the hot
spots may dissipate through the molding material 114. The cooling
devices 120 described herein advantageously are also adapted to
dissipate heat from the interconnect structure 112 and/or the
molding material 114 of packaged semiconductor devices 100, in some
embodiments.
In some embodiments, the method of packaging the semiconductor
device described in the flow chart 150 shown in FIG. 24 further
comprises coupling the interconnect structure 112 to a substrate or
PCB 102 using a plurality of connectors 104, as shown in FIG. 1. In
some embodiments, the integrated circuit die 110, the interconnect
structure 112, and the molding material 114 comprise a first
packaged semiconductor device 100a, and the method further
comprises coupling a second packaged semiconductor device 100b to
the cooling device 120, as shown in FIG. 21. In yet other
embodiments, the integrated circuit die 110, the interconnect
structure 112, and the molding material 114 comprise a first
packaged semiconductor device 100a, and the method further
comprises coupling a second packaged semiconductor device 100b to
the first packaged semiconductor device 100a, as shown in FIG. 26,
which will be described further herein.
FIG. 25 is a block diagram that illustrates a method of disposing a
PCM 122 in a cooling device 120 in accordance with some
embodiments. A tube 166 is bonded to an opening 123 in the first
plate 118a of the cooling device 120. The opening 123 may also be
disposed on the second plate 118b, not shown, or the opening 123
may be disposed on an edge of the cooling device 120 between the
first plate 118a and the second plate 118b, as shown in phantom
(e.g., in dashed lines) in FIG. 25 at 123'. The opening 123 or 123'
may also be located on an edge of the first plate 118a or on an
edge of the second plate 118b, for example.
The opening 123 may be circular and have a diameter of about 2 mm
to about 4 mm, for example. The opening 123 may also comprise other
shapes and dimensions. The tube 166 comprises a glass tube having a
length of about 10 mm to about 15 mm and a diameter of about 2 mm
to about 4 mm in some embodiments, for example. The glass tube may
comprise borosilicate glass in some embodiments. In other
embodiments, the tube 166 may comprise plastic, rubber, silicone,
or metal-based tubes or pipes. The tube 166 may also comprise other
materials and dimensions.
A gas 169 (i.e., air or other gas) is then removed from the cavity
121 in the cooling device 120 through the tube 166 using a vacuum
pump 164 that is controlled by a valve 168a. The PCM 122 is then
flowed in liquid form in some embodiments from a container 162,
also controlled by a valve 168b, through the tube 166 and into the
cavity 121 of the cooling device 120. The tube 166 is then melted
to form a plug 125 (not shown in FIG. 25; see FIG. 3) and seal the
cooling device 120, i.e., using a high temperature flame gun at a
temperature of about 850 degrees C. to about 1,000 degrees C. The
cooling device 120 may also be sealed by soldering, welding, or an
adhesive curing process, as examples. Other methods may also be
used to seal the cooling device 120 or to form a plug 125. The plug
125 is adapted to retain the PCM 122 within the cavity 121 in the
cooling device 120. The PCM 122 may also be introduced into the
cooling device 120 using other methods.
Some dimensions of the cooling device 120 are also illustrated in
FIG. 25. The cooling device 120 may comprise a substantially square
or rectangular shape in a top view or a perspective view (shown in
FIG. 25). The cooling device 120 comprising dimension C that was
previously described herein with reference to FIG. 6. The cooling
device 120 (and also the first plate 118a and the second plate 118b
of the cooling device 120) may comprise a length comprising
dimension F and a width comprising dimension G in some embodiments,
wherein dimensions F and G comprise about 5 mm to about 60 mm in
some embodiments, for example. Dimensions F and G may also comprise
other dimensions, e.g., as a function of an end application that
the cooling device 120 will be used in. The cooling device 120 may
also comprise several smaller sized cooling devices placed side by
side, not shown. The cooling device 120 may also comprise other
dimensions and shapes.
In accordance with some embodiments of the present disclosure, a
method of manufacturing a cooling device 120 for packaged
semiconductor device 100 includes forming a reservoir comprising a
first plate 118a, a second plate 118b coupled to the first plate
118a, and a cavity 121 disposed between the first plate 118a and
the second plate 118b. The method includes disposing a PCM 122 in
the cavity 121. In some embodiments, the first plate 118a, the
second plate 118b, or an edge between the first plate 118a and the
second plate 118b comprises an opening 123 or 123' therein as shown
in FIG. 25, and disposing the PCM 122 comprises disposing the PCM
122 through the opening 123 or 123' into the cavity 121. The method
may also comprise closing the opening 123 or 123' using a plug 125
(see FIG. 3). Referring again to FIG. 25, the method may further
comprise removing a gas 169 from the cavity 121, before disposing
the PCM 122. In some embodiments, the method may further comprise
coupling a tube 166 to the opening 123 or 123', and disposing the
PCM 122 through the tube 166 into the opening 123 or 123'. The
method may further comprise removing the tube 166, after disposing
the PCM 122.
FIG. 26 is a cross-sectional view that shows a cooling device 120
coupled to a package-on-package (POP) device 170 in accordance with
some embodiments. In some embodiments, the integrated circuit die
110a, interconnect structure 112, and molding material 114a
comprise a first packaged semiconductor device 100a. A second
packaged semiconductor device 100b is coupled to the first packaged
semiconductor device 100a by a plurality of connectors 104b,
forming a POP device 170, before the cooling device 120 is coupled
to the integrated circuit die 110a and the molding material 114a of
the first packaged semiconductor device 100a via the second
packaged semiconductor device 100b, in some embodiments. The
cooling device 120 may also be coupled to the second packaged
semiconductor device 100b before the first packaged semiconductor
device 100a is coupled to the second packaged semiconductor device
100b, in other embodiments.
To manufacture the POP device 170, in some embodiments, before the
first packaged semiconductor devices 100a are singulated, and after
the molding material 114a is formed (and also planarized in some
embodiments), a plurality of the second packaged semiconductor
devices 100b is provided, and each of the plurality of second
packaged semiconductor devices 100b is coupled to one of the first
packaged semiconductor devices 100a using the plurality of
connectors 104b. The plurality of second packaged semiconductor
devices 100b is coupled to the unsingulated plurality of first
packaged semiconductor devices 100a by a method such as manually by
an operator or technician, the use of an automated machine such as
a pick-and-place machine, or other methods. The eutectic material
of the connectors 104b is heated, reflowing the eutectic material,
and after the eutectic material cools, the second packaged
semiconductor devices 100b are electrically and mechanically
coupled to the first packaged semiconductor devices 100a. The
plurality of first packaged semiconductor devices 100a is then
singulated to form a plurality of the POP devices 170, one of which
is illustrated in FIG. 26. The cooling device 120 is then coupled
to a top surface of the second packaged semiconductor device 100b,
in some embodiments.
The second packaged semiconductor device 100b may comprise a
substrate 172 that includes a plurality of contact pads disposed
on. The substrate 172 may include one or more interconnect
structures (not shown) formed thereon that provide horizontal
connections for the second packaged semiconductor device 100b in
some embodiments. The substrate 172 may also include a plurality of
through-vias (also not shown) formed therein. One or more
integrated circuit dies 110b may be coupled to a top surface of the
substrate 172. The second packaged semiconductor device 100b
comprises two vertically stacked integrated circuit dies 110b in
the embodiments shown in FIG. 26, for example. Two or more
integrated circuit dies 110b may also be packaged together
horizontally in the second packaged semiconductor device 100b in
some embodiments, not shown.
In some of the embodiments shown, the integrated circuit dies 110b
are coupled to contact pads disposed on a top surface of the
substrate 172 by bond wires 174. The bond wires 174 and
through-vias in the substrate 172 provide vertical electrical
connections for the second packaged semiconductor device 100b in
some embodiments. A molding material 114b is disposed over the
integrated circuit dies 110b, the bond wires 174, and the substrate
172. The molding material 114b may comprise similar materials as
described for the molding material 114 (labeled 114a in FIG. 26) of
the first packaged semiconductor device 100a, for example.
In some embodiments, the integrated circuit die or dies 110b of the
second packaged device 100b may comprise dynamic random access
memory (DRAM) devices, for example. The integrated circuit dies
110b may also comprise other types of devices. The integrated
circuit dies 110b may be packaged in a wire bond type of package as
shown in FIG. 26, or the integrated circuit dies 110b may be
packaged in other types of packages and using other types of
packaging techniques.
The POP device 170 coupled to the cooling device 120 may be coupled
to another device or object using a plurality of connectors 104a
disposed on the bottom surface of the POP devices 170 that are
coupled to the interconnect structure 112, e.g., using a surface
mount technology (SMT) process. In some embodiments, the POP
devices 170 may be coupled to a substrate or PCB 102, shown in
phantom in FIG. 26.
The cooling device 120 is coupled to the first packaged
semiconductor device 100a via the second packaged semiconductor
device 100b and the plurality of connectors 104b, for example. The
cooling device 120 is adapted to dissipate heat from integrated
circuit die 110a and/or integrated circuit dies 110b, and also to
dissipate heat from other components of the POP device 170, such as
the interconnect structure 112 and molding material 114a of the
first packaged semiconductor device 100a and interconnect
structures within the substrate 172 and molding material 114b of
the second packaged semiconductor device 100b.
In some embodiments, the integrated circuit dies 110a of the first
packaged semiconductor device 100a comprise logic devices or
processors and the interconnect structure 112 of the first packaged
semiconductor device 100a comprises fan-out wiring, e.g., in some
embodiments wherein the second integrated circuit dies 110b
comprise memory devices such as DRAM devices, forming an InFO POP
device 170. The first integrated circuit dies 110a, the second
integrated circuit dies 110b, the first packaged semiconductor
device 100a, and the second packaged semiconductor device 100b may
also comprise other types of devices, and the cooling devices 120
described herein may also be implemented in other types of
applications.
FIGS. 27 and 28 are graphs that illustrate simulation results of
implementing a cooling device 120 described herein in accordance
with some embodiments. In FIG. 27, a PCM 122 comprising wax was
used in a transient thermal simulation analysis. The graph 180
illustrates solid specific heat or specific heat capacity (Cp) in
units of joule/kgKelvin (J/KgK) on the y axis over a range of
temperatures of the wax in degrees C. on the x axis. The Cp of the
wax (i.e., paraffin wax) was assumed for the simulation to be about
180,000 J/(KgK) at the wax melting point of about 45 degrees C., as
shown at 182. FIG. 28 is a graph showing temperature in degrees C.
(.degree. C.) on the y axis for a range of times in seconds (s) on
the x axis. A graph of wax temperature/time is shown at 184, and a
graph of water temperature/time is shown at 186. A maximum
temperature for contact of a handheld device for contact with skin,
Max. T.sub.skin is indicated at 45 degrees C. A steady state region
is shown in the graphs at 188. The simulation results shown in the
graphs indicate that wax has a better transient thermal performance
as a PCM 122 than water. For example, wax was found to stay below
the Max T.sub.skin temperature for a longer period of time than
water by about 1.6 seconds. Thus, using wax as a PCM 122 achieves
about 25% of operation time saving for chips (i.e., integrated
circuit dies 110), thus advantageously providing longer chip
retention time at below skin temperature T.sub.skin.
Some embodiments of the present disclosure are implementable in and
are particularly beneficial when used with packaged semiconductor
devices that comprise InFO devices. The cooling devices 120 also
have useful application in WLPs, wafer-level chip scale packages
(WLCSPs), POP devices, system-on-a chip (SOC) devices,
chip-on-wafer-on-substrate (CoWoS) devices, or other types of 3DICs
in some embodiments, as examples. Embodiments of the present
disclosure are also beneficial for and may be implemented in other
types of devices or wafer level packaging that include integrated
circuit dies with hot spots and other elements with elevated
temperatures during operation of the devices, as other
examples.
Some embodiments of the present disclosure include cooling devices
120 and packaged semiconductor devices 100, systems 131, and POP
devices 170 that include the cooling devices 120 described herein.
Other embodiments include methods of packaging semiconductor
devices that include the cooling devices 120.
Advantages of some embodiments of the present disclosure include
providing cooling devices, packaging methods, and structures that
are cost effective and dissipate heat away from hot spots of
integrated circuit dies and other elements of the packaged
semiconductor devices, such as interconnect structures and molding
materials. Low cost cooling solutions are provided by the
PCM-containing cooling devices, which also provide improved
transient thermal performance and improved reliability. Max
T.sub.skin of mobile and handheld devices may be achieved without
degrading electrical performance, such as delay time and retention
time of integrated circuit dies, and operation time can be
lengthened. The cooling devices advantageously enable cooling of
packaged semiconductor devices below Max T.sub.skin in some
embodiments. Thermal run-away of integrated circuit dies due to hot
spots or thermal cross-talk may be reduced or eliminated by
implementing the cooling devices on the packaged semiconductor
devices. More than one type of PCM may be included in the cooling
devices, enabling different heat dissipation and cooling rates for
integrated circuit dies coupled to the cooling devices.
Some embodiments involve using the cooling devices as an integral
part of a heat sink, reducing package z-profiles and resulting in
effective device transient cooling. Other embodiments include a
conformable member, which accommodates multiple package heights on
a substrate or PCB. Some embodiments include cooling devices
coupled to a heat pipe. The cooling devices are flexibly integrated
to InFO and CoWoS devices, and are suitable for handheld devices
and for use with system parts. The cooling devices have thin
profiles and are easily integratable with packaged semiconductor
devices. Furthermore, the cooling devices described herein are
easily implementable into existing packaging process flows and
structures.
In some embodiments, a cooling device for a semiconductor device
includes a reservoir having a first plate and a second plate
coupled to the first plate, and a cavity disposed between the first
plate and the second plate. A PCM is disposed in the cavity. The
cooling device is adapted to dissipate heat from a packaged
semiconductor device.
In other embodiments, a packaged semiconductor device includes an
integrated circuit die, an interconnect structure coupled to the
integrated circuit die, and a molding material disposed around the
integrated circuit die and over the interconnect structure. A
cooling device is coupled to the integrated circuit die and the
molding material. The cooling device includes a reservoir including
a first plate and a second plate coupled to the first plate, and a
cavity disposed between the first plate and the second plate. A PCM
is disposed in the cavity. Edges of the second plate are coupled to
edges of the first plate. The cooling device is adapted to
dissipate heat from the integrated circuit die, the interconnect
structure, or the molding material.
In yet other embodiments, a method of packaging a semiconductor
device includes coupling an integrated circuit die to an
interconnect structure. A molding material is formed around the
integrated circuit die and over the interconnect structure. A
cooling device is coupled to the integrated circuit die and the
molding material. The cooling device includes a reservoir
comprising a first plate and a second plate coupled to the first
plate, and a cavity disposed between the first plate and the second
plate. A PCM is disposed in the cavity. The cooling device is
adapted to dissipate heat from the integrated circuit die, the
interconnect structure, or the molding material.
The foregoing outlines features of several embodiments so that
those skilled in the art may better understand the aspects of the
present disclosure. Those skilled in the art should appreciate that
they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *
References