U.S. patent application number 17/178029 was filed with the patent office on 2021-11-04 for power distribution structure and method.
The applicant listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.. Invention is credited to Te-Hsin CHIU, Shih-Wei PENG, Jiann-Tyng TZENG.
Application Number | 20210343650 17/178029 |
Document ID | / |
Family ID | 1000005444743 |
Filed Date | 2021-11-04 |
United States Patent
Application |
20210343650 |
Kind Code |
A1 |
PENG; Shih-Wei ; et
al. |
November 4, 2021 |
POWER DISTRIBUTION STRUCTURE AND METHOD
Abstract
An IC package includes a first die including a front side and a
back side, the front side including a first signal routing
structure, the back side including a first power distribution
structure, and a second die including a front side and a back side,
the front side including a second signal routing structure, the
back side including a second power distribution structure. The IC
package includes a third power distribution structure positioned
between the first and second power distribution structures and
electrically connected to each of the first and second power
distribution structures.
Inventors: |
PENG; Shih-Wei; (Hsinchu,
TW) ; CHIU; Te-Hsin; (Hsinchu, TW) ; TZENG;
Jiann-Tyng; (Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
Hsinchu |
|
TW |
|
|
Family ID: |
1000005444743 |
Appl. No.: |
17/178029 |
Filed: |
February 17, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
63018028 |
Apr 30, 2020 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/50 20130101;
H01L 27/0688 20130101; H01L 24/94 20130101; H01L 23/5386 20130101;
H01L 23/5286 20130101 |
International
Class: |
H01L 23/538 20060101
H01L023/538; H01L 23/50 20060101 H01L023/50; H01L 23/528 20060101
H01L023/528; H01L 27/06 20060101 H01L027/06; H01L 23/00 20060101
H01L023/00 |
Claims
1. An integrated circuit (IC) package, the IC package comprising: a
first die comprising a front side and a back side, the front side
comprising a first signal routing structure, the back side
comprising a first power distribution structure; a second die
comprising a front side and a back side, the front side comprising
a second signal routing structure, the back side comprising a
second power distribution structure; and a third power distribution
structure positioned between the first and second power
distribution structures and electrically connected to each of the
first and second power distribution structures.
2. The IC package of claim 1, further comprising: a third die
comprising a front side and a back side, the front side comprising
a third signal routing structure electrically connected to the
first signal routing structure, the back side comprising a fourth
power distribution structure; a fourth die comprising a front side
and a back side, the front side comprising a fourth signal routing
structure, the back side comprising a fifth power distribution
structure; and a sixth power distribution structure positioned
between the fourth and fifth power distribution structures and
electrically connected to each of the fourth and fifth power
distribution structures.
3. The IC package of claim 1, further comprising a third die
comprising a front side and a back side, the front side comprising
a third signal routing structure and the back side comprising a
fourth power distribution structure electrically connected to the
third power distribution structure.
4. The IC package of claim 3, further comprising a first substrate
electrically connected to each of the first signal routing
structure and the third signal routing structure.
5. The IC package of claim 4, further comprising a second substrate
electrically connected to the second signal routing structure.
6. The IC package of claim 5, further comprising a plurality of via
structures electrically connected to each of the first and second
substrates, wherein the plurality of via structures extends through
the third power distribution structure and is electrically isolated
from the third power distribution structure.
7. The IC package of claim 5, further comprising a fourth die
electrically connected to the second substrate, wherein the second
substrate is positioned between the second die and the fourth
die.
8. The IC package of claim 5, further comprising a via structure
electrically connected to the third power distribution structure
and the second substrate.
9. The IC package of claim 1, wherein at least one of the back side
of the first die or the back side of the second die comprises a
power rail.
10. The IC package of claim 1, wherein each of the first, second,
and third power distribution structures comprises a mesh
structure.
11. A method of forming an integrated circuit (IC) package, the
method comprising: constructing a first power distribution
structure on a first die included in the IC package, thereby
electrically connecting the first power distribution structure to a
second power distribution structure positioned on a back side of
the first die; and bonding a third power distribution structure to
the first power distribution structure, the third power
distribution structure being positioned on a back side of a second
die.
12. The method of claim 11, wherein the constructing the first
power distribution structure on the first die comprises forming a
mesh structure on a mesh structure of the second power distribution
structure.
13. The method of claim 12, further comprising forming a via
structure extending through the mesh structure of the first power
distribution structure and electrically isolated from the first
power distribution structure.
14. The method of claim 11, wherein the third power distribution
structure comprises topmost metal segments extending in a first
direction and having a first pitch, the first power distribution
structure comprises topmost metal segments extending in a second
direction and having the first pitch, and the bonding the third
power distribution structure to the first power distribution
structure comprises aligning the first direction with the second
direction, the topmost metal segments of the third power
distribution structure thereby aligning with the topmost metal
segments of the first power distribution structure.
15. The method of claim 11, wherein the third power distribution
structure comprises topmost metal segments extending in a first
direction, the first power distribution structure comprises topmost
metal segments extending in a second direction, and the bonding the
third power distribution structure to the first power distribution
structure comprises aligning the first direction perpendicular to
the second direction, thereby aligning the topmost metal segments
of the third power distribution structure orthogonal to the topmost
metal segments of the first power distribution structure.
16. The method of claim 11, wherein the bonding the third power
distribution structure to the first power distribution structure
comprises performing a thermo-compression operation.
17. The method of claim 11, further comprising: constructing a
fourth power distribution structure electrically connected to a
fifth power distribution structure positioned on a back side of a
third die; bonding a sixth power distribution structure to the
fourth power distribution structure, the sixth power distribution
structure being positioned on a back side of a fourth die; and
including the third die and the fourth die in the IC package.
18. The method of claim 11, further comprising bonding a fourth
power distribution structure to the first power distribution
structure, the fourth power distribution structure being positioned
on a back side of a third die.
19. A method of distributing power in an integrated circuit (IC)
package, the method comprising: receiving a power supply voltage at
a first power distribution structure in the IC package; receiving
the power supply voltage from the first power distribution
structure at a second power distribution structure, the second
power distribution structure being positioned on a back side of a
first die in the IC package; and receiving the power supply voltage
from the first power distribution structure at a third power
distribution structure, the third power distribution structure
being positioned on a back side of a second die in the IC
package.
20. The method of claim 19, further comprising: receiving a
reference voltage at the first power distribution structure;
receiving the reference voltage from the first power distribution
structure at the second power distribution structure; and receiving
the reference voltage from the first power distribution structure
at the third power distribution structure.
Description
PRIORITY CLAIM
[0001] The present application claims the priority of U.S.
Provisional Application No. 63/018,028, filed Apr. 30, 2020, which
is incorporated herein by reference in its entirety.
BACKGROUND
[0002] Integrated circuits (ICs) on separate wafers are frequently
combined in IC packages. IC package components commonly include
combinations of individual dies, wafers, substrates, printed
circuit boards (PCBs), interposers, solder bumps, through-vias,
metal interconnects, and dielectric and molding materials. The IC
package components are sometimes arranged as a stack in a 3DIC
package or side-by-side in a fan-out configuration, often referred
to as an integrated fan-out (InFO) 2.5D package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIGS. 1A-1Cb are cross-sectional views of IC packages, in
accordance with some embodiments.
[0005] FIGS. 2A and 2B are cross-sectional views of IC structures,
in accordance with some embodiments.
[0006] FIGS. 3A and 3B are plan views of IC structures, in
accordance with some embodiments.
[0007] FIGS. 4A and 4B are cross-sectional views of IC structures,
in accordance with some embodiments.
[0008] FIGS. 4C and 4D are perspective views of IC structures, in
accordance with some embodiments.
[0009] FIGS. 5A-5E are cross-sectional views of intermediate stages
in the formation of an IC package, in accordance with some
embodiments.
[0010] FIGS. 6A-6E are cross-sectional views of intermediate stages
in the formation of an IC package, in accordance with some
embodiments.
[0011] FIGS. 7A-7G are cross-sectional views of intermediate stages
in the formation of an IC package, in accordance with some
embodiments.
[0012] FIG. 8 is a flowchart of a method of forming an IC package,
in accordance with some embodiments.
[0013] FIG. 9 is a flowchart of a method of distributing power in
an IC package, in accordance with some embodiments.
DETAILED DESCRIPTION
[0014] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components,
values, operations, materials, arrangements, or the like, are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. Other
components, values, operations, materials, arrangements, or the
like, are contemplated. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0015] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0016] In various embodiments, an IC package includes a power
distribution structure electrically connected to back side power
distribution structures of each of at least two dies. Compared to
approaches that do not include a power distribution structure
electrically connected to back side power distribution structures
of each of at least two dies, such IC packages are capable of
having lower power distribution path resistance and greater
arrangement flexibility.
[0017] FIGS. 1A-1Cb are cross-sectional views of respective IC
packages 100A-100C, in accordance with some embodiments. In
addition to IC package 100A, 100B, or 100C, each of FIGS. 1A-1Cb
also includes an X direction and a Z direction perpendicular to the
X direction. In some embodiments, one or more of IC packages 100A,
100B, or 100C is manufactured in accordance with a method 800 of
forming an IC package discussed below with respect to FIGS.
5A-8.
[0018] In various embodiments, each of FIGS. 1A-1Cb depicts
elements of IC packages 100A-100C corresponding to a finished IC
package or to an IC package in an unfinished manufacturing state.
In various embodiments, IC package 100A corresponds to a finished
or unfinished state of a manufacturing process illustrated in FIGS.
5A-5E, IC package 100B corresponds to a finished or unfinished
state of a manufacturing process illustrated in FIGS. 6A-6E, and/or
IC package 100C corresponds to a finished or unfinished state of a
manufacturing process illustrated in FIGS. 7A-7G, each discussed
below with respect to method 800 and FIG. 8.
[0019] Each of FIGS. 1A-1Cb is simplified for the purpose of
illustration. The relative sizes, shapes, and positions of the
elements depicted in FIGS. 1A-1Cb are non-limiting examples used to
illustrate the embodiments discussed below. In various embodiments,
one or more of IC packages 100A-100C includes one or more elements,
e.g., dies, substrates, or insulation layers, in addition to the
elements depicted in FIGS. 1A-1Cb that are not shown for the
purpose of clarity.
[0020] In the embodiments depicted in FIGS. 1A-1Cb, each of IC
packages 100A-100C includes some or all of dies D1-D4. A die, e.g.,
a die D1-D4 is a portion of a semiconductor wafer including one or
more IC devices. In the embodiments depicted in FIGS. 1A-1Cb, each
of dies D1-D4 represents a single die cut from a corresponding
wafer. In various embodiments, one or more of IC packages 100A-100C
includes one or more of dies D1-D4 representing an entire wafer or
wafer portion including a plurality of dies that includes the
corresponding die D1-D4.
[0021] In various embodiments, one or more of IC packages 100A-100C
includes one or more dies in addition to the some or all of dies
D1-D4 depicted in FIGS. 1A-1Cb, and/or one more of IC packages
100A-100C includes fewer than the some or all of dies D1-D4
depicted in FIGS. 1A-1Cb.
[0022] In the embodiments depicted in FIGS. 1A-1Cb, each of IC
packages 100A-100C includes one or more of power distribution
structures CPD1-CPD4, further discussed below. In various
embodiments, one or more of IC packages 100A-100C includes one or
more power distribution structures in addition to the one or more
of power distribution structures CPD1-CPD4 depicted in FIGS.
1A-1Cb. In some embodiments, IC package 100A does not include power
distribution structure CPD2 depicted in FIG. 1A. In some
embodiments, IC package 100C does not include one or more of power
distribution structures CPD1-CPD4 depicted in FIGS. 1Ca and
1Cb.
[0023] Each of dies D1-D4 extends along the X direction and along a
Y direction (not shown in FIGS. 1A-1Cb) perpendicular to the X and
Z directions, and includes a front side FS and a back side BS, each
extending in the X-Y plane. The front side FS of a given die, e.g.,
a die D1-D4, corresponds to a surface on which one or more IC
devices are formed in a manufacturing process, and the back side BS
corresponds to the opposing surface of the semiconductor wafer on
which the one or more circuits are formed. In some embodiments, the
back side BS of a given wafer corresponds to a surface resulting
from a thinning operation. As depicted in FIGS. 1A-1Cb, each of
dies D1-D4 is oriented either positively or negatively in the Z
direction according to the corresponding front side FS and back
side BS arrows.
[0024] The front side FS of each of dies D1-D4 includes the one or
more IC devices (not shown) electrically connected to a
corresponding signal routing structure SR1-SR4, and the back side
BS of each of dies D1-D4 includes a corresponding back side power
distribution structure BSPD1-BSPD4 electrically connected to the
corresponding one or more IC devices. In some embodiments, a signal
routing structure, e.g. a signal routing structure SR1-SR4, is
considered to include the one or more IC devices.
[0025] In various embodiments, the one or more IC devices include
one or a combination of a logic, signal, or application processor,
a memory, a high-bandwidth memory (HBM), a system on an IC (SoIC),
a transmitter and/or receiver, an application-specific IC (ASIC), a
large-scale integration (LSI) or very large-scale integration
(VLSI) circuit, a voltage or current regulator, or the like.
[0026] A signal routing structure, e.g., a signal routing structure
SR1-SR4, includes a plurality of conductive segments supported and
electrically separated by a plurality of insulation layers and
arranged in accordance with functionality of the corresponding one
or more IC devices. Conductive segments include conductive lines,
vias, contact pads, and/or under-bump metallization (UBM)
structures including one or more conductive materials, e.g., a
metal such as copper, aluminum, tungsten, or titanium, polysilicon,
or another material capable of providing a low resistance signal
path. Insulation layers include one or more dielectric materials,
e.g., silicon dioxide, silicon nitride, or one or more high-k
dielectric materials, molding compounds, or other materials capable
of electrically insulating adjacent conductive segments from each
other.
[0027] A power distribution structure, e.g., a back side power
distribution structure BSPD1-BSPD4 or power distribution structure
CPD1-CPD4, also referred to as a power distribution network in some
embodiments, includes a plurality of conductive segments supported
and electrically separated by a plurality of insulation layers and
arranged in accordance with power delivery requirements, e.g., of
one or more IC devices of a corresponding front side FS. In various
embodiments, a power distribution structure includes one or a
combination of a through-silicon via (TSV), a through-dielectric
via (TDV), a power rail, a super power rail, a buried power rail,
conductive segments arranged in a grid or mesh structure, or
another arrangement suitable for distributing power to one or more
IC devices. In some embodiments, a power distribution structure
includes one or more elements electrically isolated from power
distribution elements and configured to provide one or more
corresponding signal routing paths, e.g., via structures VT
discussed below with respect to FIGS. 1Ca, 1Cb, 2B, 3B, and 7F.
Non-limiting examples of power distribution structures are
discussed below with respect to FIGS. 2A-4D.
[0028] In various embodiments, one or more of a signal routing
structure, e.g., a signal routing structure SR1-SR4, or a power
distribution structure, e.g., a back side power distribution
structure BSPD1-BSPD4 or power distribution structure CPD1-CPD4,
includes one or more conductive segments arranged as one or more of
an inductive device or a capacitive device, e.g., a
metal-insulator-metal (MIM) capacitor or a high density MIM (HDMIM)
capacitor (not shown).
[0029] IC package 100A depicted in FIG. 1A includes dies D1-D4
aligned in the Z direction, and is referred to as a 3D IC 100A, an
IC stack 100A, or a cube 100A in some embodiments. Each of dies D1
and D3 has a negative orientation in the Z direction corresponding
to back side BS being aligned relative to front side FS in the
positive Z direction, and each of dies D2 and D4 has a positive
orientation in the Z direction corresponding to front side FS being
aligned relative to back side BS in the positive Z direction.
[0030] Power distribution structure CPD1 is positioned between and
electrically connects back side power distribution structure BSPD1
of die D1 to back side power distribution structure BSPD2 of die D2
by directly contacting each of back side power distribution
structures BSPD1 and BSPD2. Power distribution structure CPD2 is
positioned between and electrically connects back side power
distribution structure BSPD3 of die D3 to back side power
distribution structure BSPD4 of die D4 by directly contacting each
of back side power distribution structures BSPD3 and BSPD4.
[0031] In the embodiment depicted in FIG. 1A, signal routing
structure SR2 of die D2 is electrically connected to signal routing
structure SR3 of die D3 at an interface HB1. In various
embodiments, an interface, e.g., interface HB1, includes a hybrid
bond structure, e.g., including a sealing layer, a plurality of
solder bumps, or another structure capable of providing a plurality
of electrical connections between adjacent signal routing
structures, e.g., signal routing structures SR2 and SR3.
[0032] In some embodiments, IC package 100A does not include
interface HB1, and signal routing structure SR2 of die D2 is
electrically connected to signal routing structure SR3 of die D3
through one or more additional elements, e.g., a substrate,
interposer, or one or more additional dies (not shown). In some
embodiments, one or both of signal routing structure SR2 of die D2
or signal routing structure SR3 of die D3 is electrically connected
to a back side power structure of an adjacent die through an
interface (not shown).
[0033] In the embodiment depicted in FIG. 1A, IC package 100A
thereby includes dies D1 and D2 arranged as a first pair of dies,
and dies D3 and D4 arranged as a second pair of dies, the first and
second pairs of dies electrically connected to each other, e.g., at
interface HB1. In various embodiments, IC package 100A does not
include one of the first or second pairs of dies, or includes one
or more pairs of dies (not shown) in addition to the first and
second pairs of dies and aligned with the first and second pairs of
dies in the Z direction. In various embodiments, IC package 100A
includes one or more individual dies (not shown) in addition to one
or both of the first and second pairs of dies and aligned with the
first and second pairs of dies in the Z direction.
[0034] In the embodiment depicted in FIG. 1A, IC package 100A
includes each of power distribution structures CPD1 and CPD2
electrically connected to two back side power distribution
structures. In various embodiments, IC package 100A includes one or
more power distribution structures, e.g., power distribution
structure CPD1 or CPD2, electrically connected to more than two
back side power distribution structures, e.g., a back side power
distribution structure of one or more dies (not shown) adjacent to
one of dies D1-D4 in the X and/or Y direction.
[0035] By the configuration discussed above, IC package 100A
includes some or all of dies D1-D4, each electrically connected to
an adjacent one or more of dies D1-D4, the some or all of dies
D1-D4 thereby being arranged as an electrically integrated assembly
having a functional capability based on the some or all of dies
D1-D4.
[0036] By including at least one power distribution structure CPD1
or CDP2 electrically connected to at least two back side power
distribution structures, e.g., BSPD1 and BSPD2, or BSPD3 and BSPD4,
IC package 100A is capable of having lower power distribution path
resistance and greater arrangement flexibility compared to
approaches that do not include a power distribution structure
electrically connected to back side power distribution structures
of each of at least two dies.
[0037] IC package 100B depicted in FIG. 1B includes die D1 aligned
with each of dies D2 and D3 in the Z direction, and is referred to
as an InFO package 100B in some embodiments. Die D1 has a negative
orientation in the Z direction, and each of dies D2 and D3 has a
positive orientation in the Z direction.
[0038] Power distribution structure CPD1 is positioned between and
electrically connects back side power distribution structure BSPD1
of die D1 to each of back side power distribution structure BSPD2
of die D2 and back side power distribution structure BSPD3 of die
D3 by directly contacting each of back side power distribution
structures BSPD1, BSPD2, and BSPD3.
[0039] IC package 100B also includes a substrate INT1 aligned with
each of dies D2 and D3 in the Z direction, an insulation layer DL
positioned between dies D2 and D3 in the X direction and between
die D1 and substrate INT1 in the Z direction. A plurality of via
structures V extends through insulation layer DL in the Z
direction.
[0040] A plurality of connecting bumps B includes a first subset
(labeled) positioned between and electrically connecting power
distribution structure CPD1 to the plurality of via structures V, a
second subset positioned between and electrically connecting the
plurality of via structures V to substrate INT1, a third subset
positioned between and electrically connecting signal routing
structure SR2 of die D2 to substrate INT1, and a fourth subset
positioned between and electrically connecting signal routing
structure SR3 of die D3 to substrate INT1.
[0041] A substrate, e.g., substrate INT1, is one or more rigid
insulation layers including a plurality of conductive segments
arranged to provide signal paths from a first side to a second side
(not labeled) positioned further along the positive Z direction
than the first side. In various embodiments, a first pitch of
conductive segments arranged as first side electrical connections
in the signal paths is the same as, or smaller or larger than a
second pitch of conductive segments arranged as second side
electrical connections in the signal paths. In some embodiments, an
arrangement including the first pitch smaller or larger than the
second pitch is referred to as a fan-out arrangement. In some
embodiments, a substrate, e.g., substrate INT1, having a fan-out
arrangement is referred to as an interposer, e.g., an interposer
INT1. In some embodiments, a substrate includes some or all of a
carrier wafer, e.g., a carrier wafer C1-C5 discussed below with
respect to method 800 and FIGS. 5A-8.
[0042] A via structure, e.g., a via structure V, is a conductive
segment extending through an insulation layer in a direction, e.g.,
the Z direction, perpendicular to a plane, e.g., the X-Y plane, in
which conductive lines, e.g., conductive lines of power
distribution structure CPD1, are arranged. In some embodiments, a
via structure V is also referred to as a TSV V or a TDV V. In
various embodiments, a cross-section of a via structure in a
perpendicular plane has a circular, elliptical, square,
rectangular, hexagonal, or other suitable two-dimensional
shape.
[0043] A connecting bump, e.g., a connecting bump B, is a volume
including one or more conductive materials configured to be capable
of mechanically bonding and electrically connecting adjacent
conductive surfaces, e.g., conductive segments of a power
distribution structure such as power distribution structure CPD1 or
signal paths such as signal paths of substrate INT1. In various
embodiments, a connecting bump has a spherical, ellipsoidal,
columnar, or other suitable three dimensional shape. In various
embodiments, a connecting bump includes one or more of lead,
copper, aluminum, tin, zinc, gold, or other suitable material. In
some embodiments, a connecting bump is also referred to as a solder
bump.
[0044] In the embodiment depicted in FIG. 1B, IC package 100B
includes via structures V electrically connected to power
distribution structure CPD1 through the first subset of connecting
bumps B. In some embodiments, IC package 100B includes via
structures V directly contacting power distribution structure CPD1,
and thereby electrically connected to power distribution structure
CPD1.
[0045] In the embodiment depicted in FIG. 1B, IC package 100B
includes die D2 electrically connected to substrate INT1 through
the third subset of connecting bumps B, and die D3 electrically
connected to substrate INT1 through the fourth subset of connecting
bumps B. In various embodiments, IC package 100B includes a single
one of dies D2 and D3 electrically connected to substrate INT1, or
includes one or more dies (not shown) in addition to dies D2 and D3
and electrically connected to substrate INT1 through one or more
corresponding additional subsets of connecting bumps B.
[0046] In the embodiment depicted in FIG. 1B, IC package 100B
includes back side power distribution structures BSPD1 of die D1,
BSPD2 of die D2, and BSPD3 of die D3 electrically connected to
power distribution structure CPD1. In various embodiments, IC
package 100B includes a single one of back side power distribution
structures BSPD2 of die D2 and BSPD3 of die D3 electrically
connected to power distribution structure CPD1, or includes one or
more additional back side power distribution structures of one or
more corresponding additional dies (not shown) electrically
connected to power distribution structure CPD1, i.e., aligned in
the X and/or Y direction with die D1 or with dies D2 and D3. In
various embodiments, one or more of dies D1-D3 is included in a die
stack, e.g., IC package 100A discussed above with respect to FIG.
100A, included in IC package 100B.
[0047] In the embodiment depicted in FIG. 1B, IC package 100B
includes each of dies D2 and D3 positioned between and electrically
connected to both substrate INT1 and power distribution structure
CPD1 as discussed above. In various embodiments, IC package 100B
includes a single one of dies D2 and D3 positioned between and
electrically connected to both substrate INT1 and power
distribution structure CPD1, or includes one or more dies (not
shown) in addition to dies D2 and D3 positioned between and
electrically connected to both substrate INT1 and power
distribution structure CPD1.
[0048] In the embodiment depicted in FIG. 1B, IC package 100B
includes power distribution structure CPD1 electrically connected
to each of dies D1-D3 and plurality of via structures V. In various
embodiments, IC package 100B includes power distribution structure
CPD1 electrically connected to a subset of dies D1-D3 and plurality
of via structures V, and one or more additional power distribution
structures (not shown) electrically connected to one or more
corresponding additional subsets of dies D1-D3 and plurality of via
structures V.
[0049] In the embodiment depicted in FIG. 1B, IC package 100B
includes an entirety of plurality of via structures V positioned
between dies D2 and D3, thereby providing electrical connections
between substrate INT1 and power distribution structure CPD1. In
various embodiments, IC package 100B includes some or all of
plurality of via structures V otherwise positioned relative to dies
D2 and D3 so as to provide electrical connections between substrate
INT1 and power distribution structure CPD1. In some embodiments, IC
package 100B includes some or all of plurality of via structures V
positioned so as to provide electrical connections between
substrate INT1 and one or more power distribution structures (not
shown) in addition to power distribution structure CPD1.
[0050] In the embodiment depicted in FIG. 1B, IC package 100B
includes a total of three via structures V. In various embodiments,
IC package 100B includes fewer or greater than three via structures
V.
[0051] By the configuration discussed above, IC package 100B
includes some or all of dies D1-D3 electrically connected to
substrate INT1 through the at least one power distribution
structure CPD1, the some or all of dies D1-D3 thereby being
arranged as an electrically integrated assembly capable of
receiving power through substrate INT1 and having a functional
capability based on the some or all of dies D1-D3.
[0052] By including at least one power distribution structure CPD1
electrically connected to at least two back side power distribution
structures, e.g., BSPD1 and BSPD2 or BSPD3, IC package 100B is
capable of having lower power distribution path resistance and
greater arrangement flexibility compared to approaches that do not
include a power distribution structure electrically connected to
back side power distribution structures of each of at least two
dies.
[0053] IC package 100C depicted in FIGS. 1Ca and 1Cb, referred to
as an InFO package 100C in some embodiments, includes dies D1-D3,
substrate INT1, power distribution structure CPD1, and a first
subset of via structures V extending through an insulation layer DL
between dies D2 and D3, the elements being arranged in accordance
with the various embodiments discussed above with respect to IC
package 100B. In some embodiments, substrate INT1 of IC package
100C is referred to as a baseboard INT1.
[0054] In the embodiments depicted in FIGS. 1Ca and 1Cb, IC package
100C also includes power distribution structures CPD2-CPD4, a
substrate INT2, a die DA, second and third subsets of via
structures V, and additional insulation layers DL arranged as
discussed below.
[0055] In the embodiment depicted in FIG. 1Ca, subsets of
connecting bumps B contact substrate INT1 and either signal routing
structure SR2 of die D2 or signal routing structure SR3 of die D3,
IC package 100C thereby being configured to include signal path
connections from substrate INT1 to signal routing structures SR2
and SR3. In the embodiment depicted in FIG. 1Cb, the subsets of
connecting bumps B contact substrate INT1 and a carrier wafer C5
which contacts signal routing structure SR2 of die D2 and signal
routing structure SR3 of die D3. Carrier wafer C5 includes a
plurality of conductive paths, e.g., TSV and/or TDV structures (not
labeled), and IC package 100C is thereby configured to include
signal path connections from substrate INT1 to signal routing
structures SR2 and SR3. Carrier wafer C5 is further discussed below
with respect to method 800 and FIGS. 7A-8.
[0056] In the embodiment depicted in FIG. 1Ca, IC package 100C
corresponds to a first case in which carrier wafer C5 is removed
prior to substrate INT1 being attached, and in the embodiment
depicted in FIG. 1Cb, IC package 100C corresponds to a second case
in which carrier wafer C5 is not removed prior to substrate INT1
being attached, as discussed below with respect to FIGS. 7G and
8.
[0057] In the embodiments depicted in FIGS. 1Ca and 1Cb, power
distribution structure CPD1 is positioned between and electrically
connects back side power distribution structure BSPD1 of die D1 to
power distribution structure CPD4 by directly contacting each of
back side power distribution structure BSPD1 and power distribution
structure CPD4; power distribution structure CPD2 is positioned
between and electrically connects back side power distribution
structure BSPD2 of die D2 to power distribution structure CPD4 by
directly contacting each of back side power distribution structure
BSPD2 and power distribution structure CPD4; and power distribution
structure CPD3 is positioned between and electrically connects back
side power distribution structure BSPD3 of die D3 to power
distribution structure CPD4 by directly contacting each of back
side power distribution structure BSPD3 and power distribution
structure CPD4. Power distribution structure CPD4 is positioned
between and electrically connects power distribution structure CPD1
to each of power distribution structures CPD2 and CPD3 by directly
contacting each of power distribution structures CPD1-CPD3.
[0058] In some embodiments, IC package 100C does not include one or
more of power distribution structures CPD1-CPD3, and power
distribution structure CPD4 directly contacts, and is thereby
electrically connected to, the corresponding one or more of back
side power distribution structures BSPD1-BSPD3.
[0059] Power distribution structure CPD4 includes via structures VT
positioned between and electrically connected through corresponding
connecting bumps B to the first subset of via structures V and the
second subset of via structures V positioned in an insulation layer
DL adjacent to die D1 along the positive X direction. As discussed
below with respect to FIGS. 2B and 3B, via structures VT are
electrically isolated from power distribution elements of power
distribution structure CPD4.
[0060] IC package 100C thereby includes the first and second
subsets of via structures V, power distribution structure CPD4
including via structures VT, connecting bumps B, and carrier wafer
C5 in the embodiment depicted in FIG. 1Cb, configured to provide
signal routing paths between substrates INT1 and INT2 through power
distribution structure CPD4 and electrically isolated from power
distribution elements of power distribution structure CPD4. In some
embodiments, IC package 100C includes one of both of the first or
second subsets of via structures V directly contacting via
structures VT, and thereby includes the first and second subsets of
via structures V, power distribution structure CPD4, connecting
bumps B if present, and carrier wafer C5 in the embodiment depicted
in FIG. 1Cb, configured to provide signal routing paths between
substrates INT1 and INT2 through power distribution structure CPD4
and electrically isolated from power distribution elements of power
distribution structure CPD4.
[0061] The third subset of via structures V is positioned in an
insulation layer DL adjacent to die D1 along the negative X
direction, and is thereby electrically connected to power
distribution structure CPD1 and substrate INT2. In some embodiments
in which IC package 100C does not include power distribution
structure CPD1, the third subset of via structures V is thereby
electrically connected to power distribution structure CPD4 and
substrate INT2.
[0062] The numbers of via structures V included in each of the
first through third subsets depicted in FIGS. 1Ca and 1Cb are
non-limiting examples provided for the purpose of illustration. In
various embodiments, IC package 100C includes one or more of first
through third subsets of via structures V having fewer or greater
than the numbers depicted in FIGS. 1Ca and 1Cb. In various
embodiments, IC package 100C does not include one or more of first
through third subsets of via structures V. In some embodiments, a
given one of the first through third subsets of via structures V is
referred to as TSV V or TDV V.
[0063] Power distribution structure CPD4 is thereby electrically
connected to substrate INT2 through the second subset of via
structures V and corresponding connecting bumps B, and through
power distribution structure CPD1, the third subset of via
structures V, and corresponding connecting bumps B. Die D1,
substrate INT2, and die DA are aligned in the Z direction, and
substrate INT2 is electrically connected to die DA through
corresponding connecting bumps B.
[0064] Compared to dies D1-D4 that include electrical connections
on both front side FS and back side BS, die DA includes electrical
connections solely on front side FS, the electrical connections
including both signal and power distribution paths. In some
embodiments, die DA is also referred to as a flip-chip DA, and
substrate INT2 electrically connected to die DA through the
corresponding connecting bumps B is referred to as a flip-chip
arrangement.
[0065] In some embodiments, each of dies D1-D3 includes the one or
more IC devices having feature sizes based on a first reference
dimension, and die DA includes one or more IC devices having
feature sizes based on a second reference dimension different from
the first reference dimension. In some embodiments, the second
reference dimension is larger than the first reference
dimension.
[0066] In the embodiments depicted in FIGS. 1Ca and 1Cb, IC package
100C includes a single die DA electrically connected to substrate
INT2. In some embodiments, IC package 100C includes one or more
additional dies DA (not shown) electrically connected to substrate
INT2.
[0067] By the configuration discussed above, IC package 100C
includes some or all of dies D1-D3 electrically connected to
substrate INT1 through at least one power distribution structure
CPD4, and die DA electrically connected to substrate INT1 through
substrate INT2 and, in some embodiments, via structures VT of power
distribution structure CPD4. The some or all of dies D1-D3 and die
DA are thereby arranged as an electrically integrated assembly
capable of receiving power through substrate INT1 and having a
functional capability based on the some or all of dies D1-D3 and
die DA.
[0068] By including at least one power distribution structure CPD4
electrically connected to at least two back side power distribution
structures, e.g., BSPD1 and BSPD2 or BSPD3, IC package 100C is
capable of having lower power distribution path resistance and
greater arrangement flexibility compared to approaches that do not
include a power distribution structure electrically connected to
back side power distribution structures of each of at least two
dies.
[0069] FIGS. 2A-4D depict non-limiting examples of IC structures
usable as combinations of portions of back side power distribution
structures BSPD1-BSPD3 and/or power distribution structures
CPD1-CPD4, in accordance with the various embodiments discussed
above with respect to FIGS. 1A-1Cb. Each of FIGS. 2A-4D is
simplified for the purpose of illustration. The numbers and
relative sizes, shapes, and positions of the elements depicted in
FIGS. 2A-4D are non-limiting examples used to illustrate the
embodiments discussed below. In various embodiments, one or more of
the IC structures depicted in FIGS. 2A-4D includes one or more
elements, e.g., conductive lines, via structures, power rails,
connective bumps, UBM structures, capacitive and/or inductive
devices, or insulation layers, in addition to the elements depicted
in FIGS. 2A-4D that are not shown for the purpose of clarity.
[0070] FIGS. 2A and 2B are cross-sectional views of IC structures,
in accordance with one or more embodiments. Each of FIGS. 2A and 2B
depicts a non-limiting example of an X-Z plane cross-section of a
mesh structure including elements of power distribution structures
BSPDA and BSPDB and a common power distribution structure CPD. Each
of power distribution structures BSPDA and BSPDB is usable as some
or all of back side power distribution structures BSPD1-BSPD3
and/or power distribution structures CPD1-CPD3, and common power
distribution structure CPD is usable as some or all of power
distribution structures CPD1-CPD4, each discussed above with
respect to FIGS. 1A-1Cb.
[0071] Each of the mesh structures depicted in FIGS. 2A and 2B
includes conductive lines BM0A, BM2A, BM4A, BM6A, BM4B, BM2B, and
BM0B extending in the X direction and conductive lines BM1A, BM3A,
BM5A, BM5B, BM3B, and BM1B extending in the Y direction (not
shown). Via structures VG (a portion labeled) are positioned
between and electrically connect subsets of the conductive lines of
adjacent layers to each other, the subsets of conductive lines
corresponding to distributed power voltage levels.
[0072] In the embodiments depicted in FIGS. 2A and 2B, IC
structures are configured to distribute two power voltage levels,
e.g., a ground voltage level and a power supply voltage level, and
accordingly include two subsets of conductive lines in each layer.
A first subset corresponds to the X-Z plane of the cross-sectional
view and is indicated by the continuous boundary of conductive
lines BM0A-BM0B and connecting via structures VG. A second subset
corresponds to another X-Z plane (offset from the cross-sectional
view X-Z plane in the Y direction) in which conductive lines BM0A,
BM2A, BM4A, BM6A, BM4B, BM2B, and BM0B are not visible, and each of
conductive lines BM1A, BM3A, BM5A, BM5B, BM3B, and BM1B and
connecting via structures VG is indicated by an individual
boundary. Plan views corresponding to FIGS. 2A and 2B are discussed
below with respect to FIGS. 3A and 3B.
[0073] In some embodiments, an IC structure is configured to
distribute more than two power voltage levels and includes more
than two subsets of conductive lines and connecting via
structures.
[0074] Conductive lines BM0A-BM0B include conductive materials,
e.g., one or more metals, positioned in insulation layers (not
shown) of an IC package, e.g., an IC package 100A-100C. In the
embodiments depicted in FIGS. 2A and 2B, the layers including
conductive lines BM0A-BM5A and corresponding connecting via
structures VG are included in power distribution structure BSPDA,
the layers including conductive lines BM6A-BM2B and corresponding
connecting via structures VG are included in common power
distribution structure CPD, and the layers including the conductive
lines BM1B and BM0B and corresponding connecting via structures VG
are included in power distribution structure BSPDB.
[0075] In some embodiments, the layers including conductive lines
BM0A-BM5A are referred to as respective first through sixth back
side metal layers of power distribution structure BSPDA, and the
layers including conductive lines BM0B and BM1B are referred to as
respective first and second back side metal layers of power
distribution structure BSPDB. In various embodiments, the layers
including conductive lines BM6A-BM2B are referred to as respective
first through fifth or respective fifth through first back side
metal layers of common power distribution structure CPD.
[0076] The numbers of layers of conductive lines in each of power
distribution structures BSPDA and BSPDB and common power
distribution structure CPD depicted in FIGS. 2A and 2B are
non-limiting examples used to illustrate an IC structure. In
various embodiments, one or more of power distribution structures
BSPDA or BSPDB or common power distribution structure CPD includes
one or more layers in addition to those depicted in FIGS. 2A and
2B, or does not include one or more of the layers depicted in FIGS.
2A and 2B.
[0077] In various embodiments, conductive lines in a layer of
common power distribution structure CPD adjacent to a layer of one
of power distribution structures BSPDA or BSPDB, e.g., conductive
lines BM6A or BM2B, correspond to conductive lines CPDL1 discussed
below with respect to FIGS. 4A-4D.
[0078] In the embodiment depicted in FIG. 2A, each of power
distribution structures BSPDA and BSPDB and common power
distribution structure CPD includes a same number of conductive
lines BM0A-BM0B such that entireties of power distribution
structures BSPDA and BSPDB and common power distribution structure
CPD align in the Z direction. In various embodiments, power
distribution structures BSPDA and BSPDB and common power
distribution structure CPD include varying numbers of conductive
lines BM0A-BM0B such that portions of one or more of power
distribution structures BSPDA or BSPDB or common power distribution
structure CPD align in the Z direction and other portions of one or
more of power distribution structures BSPDA or BSPDB or common
power distribution structure CPD extend beyond the other(s) of
power distribution structures BSPDA or BSPDB or common power
distribution structure CPD in the X and/or Y direction.
[0079] In the embodiment depicted in FIG. 2B, common power
distribution structure CPD includes conductive lines BM6A-BM2B
extending in the positive X direction beyond conductive lines
BM0A-BM5A of power distribution structure BSPDA and conductive
lines BM1B and BM0B of power distribution structure BSPDB.
[0080] In the embodiment depicted in FIG. 2B, via structures VT
extend in the Z direction and between adjacent conductive lines
BM6A-BM2B in the extended portion of common power distribution
structure CPD. Via structures VT are electrically isolated from
each of the subsets of conductive lines BM6A-BM2B and via
structures VG corresponding to the two power voltage level
configuration of common power distribution structure CPD, and are
thereby configured to provide signal paths separate from the power
voltage levels.
[0081] In the embodiment depicted in FIG. 2B, via structures VT
extend into power distribution structures BSPDA and BSPDB, thereby
corresponding to some or all of the first and second subsets of via
structures V discussed above with respect to FIGS. 1Ca and 1Cb. In
some embodiments, via structures VT do not extend into one or both
of power distribution structures BSPDA or BSPDB, and via structures
VT are electrically connected to the corresponding first or second
subsets of via structures V by directly contacting the
corresponding first or second subsets of via structures V or
through corresponding connecting bumps B discussed above with
respect to FIGS. 1Ca and 1Cb.
[0082] FIGS. 3A and 3B are plan views of IC structures, in
accordance with one or more embodiments. Each of FIGS. 3A and 3B
depicts a non-limiting example corresponding to adjacent layers of
conductive lines of the mesh structures depicted in FIGS. 2A and
2B.
[0083] In the embodiments depicted in FIGS. 3A and 3B, conductive
lines PDL1 extend in the Y direction, conductive lines PDL2 extend
in the X direction and overlie conductive lines PDL1, and via
structures VG are positioned between and electrically connect
conductive lines PDL1 and PDL2 at subsets of locations at which
conductive lines PDL2 overlie conductive lines PDL1. In some
embodiments, conductive lines PDL1 extend in the X direction and
conductive lines PDL2 extend in the Y direction.
[0084] Conductive lines PDL1 and PDL2 thereby correspond to
adjacent layers of conductive lines, e.g., respective conductive
lines BM0A and BM1A or respective conductive lines BM1A and BM0A,
of a mesh structure configured to distribute two power voltage
levels. In various embodiments, conductive lines PDL1 and PDL2
correspond to adjacent layers within one of power distribution
structures BSPDA or BSPDB or common power distribution structure
CPD, or to a layer of conductive lines within common power
distribution structure CPD adjacent to a layer of conductive lines
within one of power distribution structures BSPDA or BSPDB.
[0085] In the embodiment depicted in FIG. 3B, via structures VT are
positioned between and electrically isolated from adjacent
instances of each of conductive lines PDL1 and PDL2. Via structures
VT are thereby configured to provide signal paths separate from the
power voltage levels corresponding to conductive lines PDL1 and
PDL2 and via structures VG.
[0086] In the embodiment depicted in FIG. 3B, via structures VT
have a hexagonal shape in the X-Y plane. In various embodiments,
via structures VT have one or more other shapes in the X-Y plane,
e.g., circular, and are thereby positioned between and electrically
isolated from adjacent instances of each of conductive lines PDL1
and PDL2.
[0087] As depicted in FIG. 3A, conductive lines PDL1 are spaced
along the X direction according to a pitch P1, and conductive lines
PDL2 are spaced along the Y direction according to a pitch P2. In
various embodiments, a pitch, e.g., one of pitches P1 or P2, is
equal to or is a multiple of a feature size corresponding to the
one or more IC devices included in a die, e.g., a die D1-D4
discussed above with respect to FIGS. 1A-1Cb.
[0088] In some embodiments, one of conductive lines PDL1 or
conductive lines PD2 are included in a first back side metal layer,
and the corresponding pitch P1 or P2 is equal to or is a multiple
of a cell height of the one or more IC devices. In some
embodiments, the cell height corresponds to an internal die spacing
between adjacent power rails corresponding to two power voltage
levels, and the one of conductive lines PDL1 or PDL2 is configured
to distribute the two corresponding power voltage levels. In some
embodiments, one of conductive lines PDL1 or conductive lines PD2
are included in a back side metal layer above the first metal
layer, and the corresponding pitch P1 or P2 is a multiple of the
cell height.
[0089] In some embodiments, one of conductive lines PDL1 or
conductive lines PD2 are included in a back side metal layer above
the first metal layer, and the corresponding pitch P1 or P2 is a
multiple of a contact poly pitch of the one or more IC devices. In
some embodiments, the contact poly pitch corresponds to an internal
die spacing between contacts electrically connected to adjacent
gate structures or gate structure multiples.
[0090] FIGS. 4A and 4B are cross-sectional views of IC structures,
and FIGS. 4C and 4D are perspective views of IC structures, in
accordance with some embodiments. Each of FIGS. 4A-4D depicts a
non-limiting example of a junction between common power
distribution structure CPD, discussed above with respect to FIGS.
2A and 2B, and a power distribution structure BSPD corresponding to
one of power distribution structures BSPDA or BSPDB. Each of FIGS.
4A and 4B depicts common power distribution structure CPD and power
distribution structure BSPD as separate structures on the left side
of an arrow and as a combined structure on the right side of the
arrow, and each of FIGS. 4C and 4D depicts the corresponding
combined structure.
[0091] In each of the embodiments depicted in FIGS. 4A and 4B,
common power distribution structure CPD includes a topmost layer
(in the negative Z direction) of conductive lines CPDL1 extending
in the X direction, a layer adjacent to the topmost layer including
conductive lines CPDL2 extending in the Y direction, and via
structures VG electrically connecting conductive lines CPDL1 to
conductive lines CPDL2. Conductive lines CPDL1 have a thickness TC
in the Z direction.
[0092] In the embodiment depicted in FIG. 4A, power distribution
structure BSPD includes a topmost layer (in the positive Z
direction) of conductive lines BSL1 extending in the X direction, a
layer adjacent to the topmost layer including conductive lines BSL2
extending in the Y direction, and via structures VG electrically
connecting conductive lines BSL1 to conductive lines BSL2.
Conductive lines BSL1 have a thickness TB in the Z direction.
[0093] In the embodiment depicted in FIG. 4B, power distribution
structure BSPD includes conductive lines BSL1 extending in the Y
direction, and via structures VG electrically connected to
conductive lines BSL1 and extending away from conductive lines BSL1
in the positive Z direction.
[0094] In the embodiment depicted in FIGS. 4A and 4C, the combined
structure includes conductive lines CPDL1/BSL1 having a thickness
TT in the Z direction. Conductive lines CPDL1/BSL1 correspond to
conductive lines CPDL1 and BSL1 extending in the X direction and
having a same pitch in the Y direction such that the combined
structure includes electrical connections between topmost
conductive lines of common power distribution structure CPD aligned
with topmost conductive lines of power distribution structure BSPD.
In some embodiments, one of conductive lines CPDL1 or BSL1 have a
first pitch and the other of conductive lines CPDL1 or BSL1 have a
second pitch equal to a multiple of the first pitch.
[0095] In some embodiments, thickness TT is approximately equal to
a sum of thicknesses TC and TB. In some embodiments, thickness TT
is less than the sum of thicknesses TC and TB.
[0096] In accordance with the embodiment depicted in FIGS. 4A and
4C, in the non-limiting example depicted in FIGS. 2A and 2B, either
common power distribution structure CPD includes conductive lines
BM6A corresponding to conductive lines CPDL1/BSL1 and power
distribution structure BSPDA includes conductive lines BM5A
corresponding to conductive lines BSL2, or common power
distribution structure CPD includes conductive lines BM2B
corresponding to conductive lines CPDL1/BSL1 and power distribution
structure BSPDB includes conductive lines BM1B corresponding to
conductive lines BSL2.
[0097] In the embodiment depicted in FIGS. 4B and 4D, the combined
structure includes conductive lines CPDL1 having thickness TC.
Conductive lines CPDL1 extend in the X direction and conductive
lines BSL1 extend in the Y direction such that the combined
structure includes electrical connections through via structures VG
(not shown in FIG. 4D) between topmost conductive lines of common
power distribution structure CPD orthogonal to topmost conductive
lines of power distribution structure BSPD.
[0098] In the embodiment depicted in FIGS. 4B and 4D, the combined
structure is based on power distribution structure BSPD including
via structures VG extending from the topmost conductive lines. In
various embodiments, a combined structure including electrical
connections between topmost conductive lines of common power
distribution structure CPD orthogonal to topmost conductive lines
of power distribution structure BSPD is based on common power
distribution structure CPD including via structures VG extending
from the topmost conductive lines, or includes topmost conductive
lines of common power distribution structure directly connected to
topmost conductive lines of power distribution structure BSPD.
[0099] In accordance with the embodiment depicted in FIGS. 4B and
4D, in the non-limiting example depicted in FIGS. 2A and 2B, either
common power distribution structure CPD includes conductive lines
BM6A corresponding to conductive lines CPDL1 and power distribution
structure BSPDA includes conductive lines BM5A corresponding to
conductive lines BSL1, or common power distribution structure CPD
includes conductive lines BM2B corresponding to conductive lines
CPDL1 and power distribution structure BSPDB includes conductive
lines BM1B corresponding to conductive lines BSL1.
[0100] An IC structure including common power distribution
structure CPD configured in accordance with the various embodiments
discussed above with respect to FIGS. 2A-4D is thereby capable of
realizing the benefits discussed above with respect to IC packages
100A-100C. Further, in embodiments in which common power
distribution structure CPD includes conductive lines having one or
more pitches corresponding to one or more pitches of conductive
lines in one or both of power distribution structures BSPDA or
BSPDB, common power distribution structure CPD is able to be
manufactured using a same process as one used to manufacture the
one or both of power distribution structures BSPDA or BSPDB.
[0101] In accordance with various embodiments discussed below,
FIGS. 5A-5E are cross-sectional views of intermediate stages in the
formation of IC package 100A discussed above with respect to FIG.
1A, FIGS. 6A-6E are cross-sectional views of intermediate stages in
the formation of IC package 100B discussed above with respect to
FIG. 1B, FIGS. 7A-7G are cross-sectional views of intermediate
stages in the formation of IC package 100C discussed above with
respect to FIGS. 1Ca and 1Cb, and FIG. 8 is a flowchart of method
800 of forming an IC package, e.g., an IC package 100A-100C.
[0102] FIG. 5A illustrates dies D1-D4 of IC package 100A mounted on
corresponding carrier wafers C1-C4. As depicted in FIG. 5A, the
front side FS of each die D1-D4 has been mounted on the respective
carrier wafer C1-C4 by bonding the corresponding signal routing
structure SR1-SR4 to the respective carrier wafer C1-C4.
[0103] A carrier wafer, e.g., a carrier wafer C1-C4, is a substrate
having sufficient rigidity, e.g., a semiconductor, glass, or
organic material, such that one or more manufacturing operations
are able to be performed on one or more dies mounted on the carrier
wafer. In some embodiments, a carrier wafer includes one or more
signal path connections, e.g., one or more TSV and/or TDV
structures, and is thereby capable of providing one or more
electrical connections to the one or more dies mounted thereon.
[0104] In some embodiments, bonding a die to a carrier wafer
includes applying an adhesive layer or film on the carrier wafer.
In some embodiments, bonding a die to a wafer carrier includes
applying a release film including a polymer-based material, e.g., a
light-to-heat-conversion (LTHC) material, capable of being removed
in a subsequent operation.
[0105] Mounting dies D1-D4 of IC package 100A on carrier wafers
C1-C4 corresponds to operation 810 of method 800 illustrated in
FIG. 8.
[0106] FIG. 5B illustrates dies D1-D4 further including respective
back side power distribution structures BSPD1-BSPD4 constructed on
the corresponding back sides BS of dies D1-D4 of IC package
100A.
[0107] Constructing a power distribution structure, e.g., a back
side power distribution structure BSPD1-BSPD4, includes forming a
plurality of conductive segments supported and electrically
separated by a plurality of insulation layers. In some embodiments,
forming an insulation layer includes depositing one or more
insulation materials, e.g., dielectric materials, discussed above
with respect to FIGS. 1A-3B. In some embodiments, forming a
conductive segment includes performing one or more deposition
processes to deposit one or more conductive materials as discussed
above with respect to FIGS. 1A-3B.
[0108] Constructing the power distribution structure includes
performing a sequence of operations, each operation in the sequence
corresponding to forming a given layer of the power distribution
structure, e.g., conductive lines BM0A, BM2A, BM4A, BM6A, BM4B,
BM2B, BM0B, BM1A, BM5A, BM5A, BM5B, BM3B, and BM1B and vias VG
discussed above with respect to FIGS. 2A and 2B or conductive lines
PDL1 and PDL2 and vias VG discussed above with respect to FIGS. 3A
and 3B.
[0109] In various embodiments, forming a given layer includes
depositing and patterning one or more photoresist layers to define
a plurality of conductive segments and/or via structures,
performing one or more etching and deposition processes to form a
volume within an insulation layer including the one or more
conductive materials, and performing one or more planarization,
and/or cleaning processes.
[0110] Constructing the power distribution structure includes
performing the sequence of operations whereby the plurality of
conductive segments are arranged in accordance with power
distribution requirements as discussed above with respect to FIGS.
1A-3B.
[0111] Constructing back side power distribution structures
BSPD1-BSPD4 on the back sides BS of dies D1-D4 of IC package 100A
corresponds to operation 820 of method 800 illustrated in FIG.
8.
[0112] FIG. 5C illustrates dies D1 and D3 of IC package 100A
further including respective power distribution structures CPD1 and
CPD2 constructed on the corresponding back side power distribution
structures BSPD1 and BSPD3.
[0113] Constructing a common power distribution structure, e.g.,
power distribution structure CPD1 or CPD2, is performed in the
manner discussed above with respect to constructing a power
distribution structure and includes constructing the common power
distribution structure electrically connected to a portion or an
entirety of the back side power distribution structure. In various
embodiments, constructing the common power distribution structure
electrically connected to the back side power distribution
structure includes constructing the common power distribution
structure configured to distribute two or more power voltage
levels, e.g., a ground level and a power supply voltage level.
[0114] In some embodiments, constructing the common power
distribution structure electrically connected to the back side
power distribution structure includes forming a mesh structure. In
some embodiments, forming the mesh structure includes forming one
or more conductive lines having pitches corresponding to pitches of
one or more conductive lines of the back side power distribution
structure.
[0115] Constructing power distribution structures CPD1 and CPD2 of
IC package 100A on back side power distribution structures BSPD1
and BSPD3 corresponds to operation 840 of method 800 illustrated in
FIG. 8.
[0116] FIG. 5D illustrates IC package 100A including dies D1 and D3
as depicted in FIG. 5C and dies D2 and D4 as depicted in FIG. 5B.
As depicted in FIG. 5D, back side power distribution structure
BSPD2 of die D2 has been bonded to power distribution structure
CPD1, and back side power distribution structure BSPD4 of die D4
has been bonded to power distribution structure CPD2.
[0117] Bonding a back side power distribution structure to a common
power distribution structure, e.g., bonding back side power
distribution structure BSPD2 to power distribution structure CPD1
or back side power distribution structure BSPD4 to power
distribution structure CPD2, includes electrically connecting the
back side power distribution structure to the common power
distribution structure.
[0118] In some embodiments, bonding the back side power
distribution structure to the common power distribution structure
includes mechanically bonding the back side power distribution
structure to the common power distribution structure. In some
embodiments, mechanically bonding the back side power distribution
structure to the common power distribution structure includes
performing a thermo-compression operation. In some embodiments,
mechanically bonding the back side power distribution structure to
the common power distribution structure includes applying one or
more adhesive materials to one or both of the back side power
distribution structure or the common power distribution
structure.
[0119] In some embodiments, bonding the back side power
distribution structure to the common power distribution structure
includes bonding one of back side power distribution structures
BSPDA or BDPDB to common power distribution structure CPD as
discussed above with respect to FIGS. 2A-3B.
[0120] In some embodiments, the back side power distribution
structure includes topmost metal segments extending in a first
direction and having a first pitch, the common power distribution
structure includes topmost metal segments extending in a second
direction and having the first pitch, and bonding the back side
power distribution structure to the common power distribution
structure includes aligning the first direction with the second
direction, the topmost metal segments of the back side power
distribution structure thereby aligning with the topmost metal
segments of the common power distribution structure. In some
embodiments, bonding the back side power distribution structure to
the common power distribution structure includes bonding conductive
lines BSL1 of back side power distribution structure BSPD to
conductive lines CPDL1 of common power distribution structure CPD
as discussed above with respect to FIGS. 4A and 4C.
[0121] In some embodiments, the back side power distribution
structure includes topmost metal segments extending in a first
direction, the common power distribution structure includes topmost
metal segments extending in a second direction, and bonding the
back side power distribution structure to the common power
distribution structure includes aligning the first direction
perpendicular to the second direction, thereby aligning the topmost
metal segments of the back side power distribution structure
orthogonal to the topmost metal segments of the common power
distribution structure. In some embodiments, bonding the back side
power distribution structure to the common power distribution
structure includes bonding conductive lines BSL1 of back side power
distribution structure BSPD to conductive lines CPDL1 of common
power distribution structure CPD as discussed above with respect to
FIGS. 4B and 4D.
[0122] Bonding back side power distribution structures BSPD2 and
BSPD4 to power distribution structures CPD1 and CPD2 of IC package
100A corresponds to operation 870 of method 800 illustrated in FIG.
8.
[0123] FIG. 5E depicts IC package 100A including dies D1-D4 formed
into a die stack by detaching dies D2 and D3 from respective
carrier wafers C2 and C3 and bonding dies D2 and D3 to each other
at interface HB1.
[0124] In various embodiments, detaching a die from a carrier
wafer, e.g., detaching die D2 from carrier wafer C2 or die D3 from
carrier wafer C3, includes one or more of mechanically separating
the die from the carrier wafer or applying heat, e.g., to loosen or
release an adhesive layer.
[0125] Bonding dies to each other includes forming an interface
between signal routing structures on front sides of adjacent dies
e.g., by performing a hybrid or other bonding operation including
applying a sealing layer and/or forming a plurality of solder bumps
to form interface HB1 between signal routing structures SR2 and
SR3, thereby bonding dies D2 and D3 to each other.
[0126] IC package 100A discussed above with respect to FIG. 1A
corresponds to the depiction of FIG. 5E after dies D1 and D4 have
been detached from respective carrier wafers C1 and C4.
[0127] Forming the die stack by detaching dies D1-D4 from carrier
wafers C1-C4 and bonding dies D2 and D3 of IC package 100A to each
other corresponds to operation 880 of method 800 illustrated in
FIG. 8.
[0128] FIG. 6A illustrates dies D1-D3 of IC package 100B mounted on
corresponding carrier wafers C1-C3. As depicted in FIG. 6A, the
front side FS of each die D1-D3 has been mounted on the respective
carrier wafer C1-C3 by bonding the corresponding signal routing
structure SR1-SR3 to the respective carrier wafer C1-C3 in the
manner discussed above with respect to FIG. 5A.
[0129] Mounting dies D1-D3 of IC package 100B on carrier wafers
C1-C3 corresponds to operation 810 of method 800 illustrated in
FIG. 8.
[0130] FIG. 6B illustrates dies D1-D3 of IC package 100B further
including respective back side power distribution structures
BSPD1-BSPD3 constructed on the corresponding back sides BS of dies
D1-D3 in the manner discussed above with respect to FIG. 5B.
[0131] Constructing back side power distribution structures
BSPD1-BSPD3 on the back sides BS of dies D1-D3 of IC package 100B
corresponds to operation 820 of method 800 illustrated in FIG.
8.
[0132] FIG. 6C illustrates dies D1-D3 of IC package 100B with die
D1 further including power distribution structure CPD1 constructed
on back side power distribution structure BSPD1 in the manner
discussed above with respect to FIG. 5C.
[0133] Constructing power distribution structure CPD1 of IC package
100B on back side power distribution structure BSPD1 corresponds to
operation 840 of method 800 illustrated in FIG. 8.
[0134] FIG. 6D illustrates IC package 100B including each of back
side power distribution structures BSPD2 of die D2 and BSPD3 of die
D3 bonded to power distribution structure CPD1 in the manner
discussed above with respect to FIG. 5D.
[0135] Bonding back side power distribution structures BSPD2 and
BSPD3 to power distribution structure CPD1 of IC package 100B
corresponds to operation 870 of method 800 illustrated in FIG.
8.
[0136] FIG. 6E depicts IC package 100B including dies D2 and D3
detached from respective carrier wafers C2 and C3 and further
including connecting bumps B, insulation layer DL, and via
structures V formed on power distribution structure CPD1.
[0137] Forming a connecting bump, e.g., a connecting bump B,
includes forming a volume including one or more conductive
materials as discussed above with respect to FIG. 1B. Forming the
volume includes forming the volume directly contacting the power
distribution structure, e.g., power distribution structure CPD1,
thereby electrically connecting the connecting bump to the power
distribution structure.
[0138] Forming an insulation layer, e.g., insulation layer DL,
includes performing one or more deposition processes whereby a
volume is caused to include one or more dielectric materials as
discussed above with respect to FIG. 1A.
[0139] Forming a via structure, e.g., a via structure V, includes
performing one or more etching processes and one or more deposition
processes whereby a volume within an insulation layer is caused to
include one or more conductive materials as discussed above with
respect to FIG. 1A.
[0140] In the embodiment depicted in FIG. 6E, via structures V are
formed directly contacting connecting bumps B, thereby electrically
connecting via structures V to power distribution structure CPD1.
In some embodiments, IC package 100B does not include connecting
bumps B directly contacting power distribution structure CPD1, and
via structures V are formed directly contacting power distribution
structure CPD1, thereby electrically connecting via structures V to
power distribution structure CPD1.
[0141] IC package 100B discussed above with respect to FIG. 1B
corresponds to the depiction of FIG. 6E after substrate INT1 has
been attached and electrically connected to dies D2 and D3 and via
structures V through additional connecting bumps B.
[0142] Detaching dies D2 and D3 from carrier wafers C2 and C3,
forming connecting bumps B, insulation layer DL, and via structures
V on power distribution structure CPD1, and attaching substrate
INT1 correspond to operation 880 of method 800 illustrated in FIG.
8.
[0143] FIG. 7A illustrates die D1 of IC package 100C mounted on
substrate INT2, and each of dies D2 and D3 mounted on carrier wafer
C5. Substrate INT2 is attached to die DA through connecting bumps
B, and in some embodiments substrate INT2 attached to die DA is
referred to as a carrier structure.
[0144] As depicted in FIG. 7A, the front side FS of die D1 has been
mounted on substrate INT2 by being attached to substrate INT2
through connecting bumps B, and each of dies D2 and D3 has been
mounted on carrier wafer C5 by bonding the corresponding signal
routing structure SR2 or SR3 to carrier wafer C5 in the manner
discussed above with respect to FIG. 5A.
[0145] Mounting dies D1-D3 of IC package 100C on substrate INT2 and
carrier wafer C5 corresponds to operation 810 of method 800
illustrated in FIG. 8.
[0146] FIG. 7B illustrates dies D1-D3 of IC package 100C further
including respective back side power distribution structures
BSPD1-BSPD3 constructed on the corresponding back sides BS of dies
D1-D3 in the manner discussed above with respect to FIG. 5B.
[0147] Constructing back side power distribution structures
BSPD1-BSPD3 on the back sides BS of dies D1-D3 of IC package 100C
corresponds to operation 820 of method 800 illustrated in FIG.
8.
[0148] FIG. 7C illustrates IC package 100C further including
connecting bumps B, insulation layer DL, and via structures V
formed on substrate INT2 in the manner discussed above with respect
to FIG. 6E.
[0149] Forming connecting bumps B, insulation layer DL, and via
structures V on substrate INT2 of IC package 100C corresponds to
operation 830 of method 800 illustrated in FIG. 8.
[0150] FIG. 7D illustrates IC package 100C with dies D1-D3 further
including respective power distribution structures CPD1-CPD3
constructed on corresponding back side power distribution
structures BSPD1-BSPD3 in the manner discussed above with respect
to FIG. 5C.
[0151] In the embodiment depicted in FIG. 7D, constructing power
distribution structure CPD1 on back side power distribution
structure BSPD1 includes constructing power distribution structure
CPD1 on insulation layer DL and via structures V, thereby
electrically connecting power distribution structure CPD1 to via
structures V. In some embodiments, IC package 100C does not include
insulation layer DL and via structures V, and constructing power
distribution structure CPD1 does not include constructing power
distribution structure CPD1 on insulation layer DL and via
structures V.
[0152] In some embodiments, IC package 100C does not include some
or all of power distribution structures CPD1-CPD3, and constructing
power distribution structures CPD1-CPD3 includes constructing a
subset or none of power distribution structures CPD1-CPD3.
[0153] Constructing power distribution structures CPD1-CPD3 of IC
package 100C on back side power distribution structures BSPD1-BSPD3
corresponds to operation 840 of method 800 illustrated in FIG.
8.
[0154] FIG. 7E illustrates IC package 100C further including
connecting bumps B, insulation layer DL, and via structures V
formed on substrate INT2 and carrier wafer C5 in the manner
discussed above with respect to FIG. 6E.
[0155] Forming connecting bumps B, insulation layer DL, and via
structures V on substrate INT2 and carrier wafer C5 of IC package
100C corresponds to operation 850 of method 800 illustrated in FIG.
8.
[0156] FIG. 7F illustrates IC package 100C further including power
distribution structure CPD4 constructed on power distribution
structures CPD2 and CPD3, insulation layer DL, and via structures
V, thereby electrically connecting power distribution structure
CPD4 to each of back side power distribution structures BSPD2 and
BSPD3. In some embodiments, IC package 100C does not include one or
both of power distribution structures CPD2 or CPD3, and power
distribution structure CPD4 is constructed on the corresponding one
or both of back side power distribution structures BSPD2 or BSPD3,
thereby electrically connecting power distribution structure CPD4
to each of back side power distribution structures BSPD2 and
BSPD3.
[0157] In the embodiment depicted in FIG. 7F, constructing power
distribution structure CPD4 includes constructing via structures VT
electrically connected to connecting bumps B and via structures V.
Constructing power distribution structure CPD4 including via
structures VT is performed in the sequential manner discussed above
with respect to FIG. 5C, in which forming each layer of conductive
segments and via structures further includes forming portions of
via structures VT. Because each operation in the sequence of
operations includes forming the portions of via structures VT,
performing the sequence of operations forms via structures VT as
continuous structures extending along the Z direction, as discussed
above with respect to FIGS. 2B and 3B.
[0158] In some embodiments, constructing power distribution
structure CPD4 includes constructing power distribution structure
CPD4 on power distribution structure CPD1 or back side power
distribution structure BSPD1 instead of on power distribution
structures CPD2 and CPD3, thereby electrically connecting power
distribution structure CPD4 to back side power distribution
structure BSPD1.
[0159] Constructing power distribution structure CPD4 of IC package
100C on power distribution structures CPD2 and CPD3, insulation
layer DL, and via structures V corresponds to operation 860 of
method 800 illustrated in FIG. 8.
[0160] In some embodiments, IC package 100C does not include power
distribution structures CPD1-CPD3, and constructing power
distribution structure CPD4 corresponds to operation 840 of method
800 illustrated in FIG. 8.
[0161] FIG. 7G illustrates IC package 100C including power
distribution structure CPD1, and thereby back side power
distribution structure BSPD1, bonded to power distribution
structure CPD4 in the manner discussed above with respect to FIG.
5D. In some embodiments, IC package 100C does not include power
distribution structure CPD1, and back side power distribution
structure BSPD1 is bonded directly to power distribution structure
CPD4 in the manner discussed above with respect to FIG. 5D.
[0162] In some embodiments, power distribution structure CPD4 is
formed on power distribution structure CPD1, and power distribution
structures CPD2 and CPD3, and thereby back side power distribution
structures BSPD2 and BSPD3, are bonded to power distribution
structure CPD4 in the manner discussed above with respect to FIG.
5D, or back side power distribution structures BSPD2 and BSPD3 are
directly bonded to power distribution structure CPD4 in the manner
discussed above with respect to FIG. 5D.
[0163] Bonding back side power distribution structures BSPD2 and
BSPD3 to power distribution structure CPD4 of IC package 100C
corresponds to operation 870 of method 800 illustrated in FIG.
8.
[0164] The embodiment of IC package 100C discussed above with
respect to FIG. 1Ca corresponds to the depiction of FIG. 7G after
carrier wafer C5 has been detached and substrate INT1 has been
attached and electrically connected to dies D2 and D3 and via
structures V through additional connecting bumps B. The embodiment
of IC package 100C discussed above with respect to FIG. 1Cb
corresponds to the depiction of FIG. 7G after substrate INT1 has
been attached and electrically connected to dies D2 and D3 and via
structures V through carrier wafer C5 and additional connecting
bumps B.
[0165] Detaching dies D2 and D3 from carrier wafer C5, forming
connecting bumps B, and attaching substrate INT1 correspond to
operation 880 of method 800 illustrated in FIG. 8.
[0166] In the embodiment depicted in FIG. 8, the sequence in which
the operations of method 800 are ordered is for illustration only;
the operations of method 800 are capable of being executed
simultaneously or in sequences that differ from that depicted in
FIG. 8. In some embodiments, operations in addition to those
depicted in FIG. 8 are performed before, between, during, and/or
after the operations depicted in FIG. 8.
[0167] In various embodiments, one or more operations of method 800
are executed using various fabrication tools, e.g., one or more of
a wafer stepper, a photoresist coater, a process chamber, e.g., a
CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a
wafer cleaning system, or other manufacturing equipment capable of
performing one or more suitable manufacturing processes as
discussed herein.
[0168] At operation 810, in some embodiments, first and second dies
are mounted on corresponding carrier structures. In various
embodiments, mounting the first and second dies on the
corresponding carrier structures includes mounting dies D1-D4 of IC
package 100A on carrier wafers C1-C4 as discussed above with
respect to FIG. 5A; mounting dies D1-D3 of IC package 100B on
carrier wafers C1-C3 as discussed above with respect to FIG. 6A; or
mounting die D1 on substrate INT2 and dies D2 and D3 on carrier
wafer C5 of IC package 100C as discussed above with respect to FIG.
7A.
[0169] At operation 820, in some embodiments, back side power
distribution structures are constructed on the first and second
dies. In various embodiments, constructing the back side power
distribution structures on the first and second dies includes
constructing back side power distribution structures BSPD1-BSPD4 on
dies D1-D4 of IC package 100A as discussed above with respect to
FIG. 5B; constructing back side power distribution structures
BSPD1-BSPD3 on dies D1-D3 of IC package 100B as discussed above
with respect to FIG. 6B; or constructing back side power
distribution structures BSPD1-BSPD3 on dies D1-D3 of IC package
100C as discussed above with respect to FIG. 7B.
[0170] In various embodiments, the first and second dies are
included in a plurality of dies, e.g., a wafer, and constructing
the back side power distribution structures on the first and second
dies includes constructing back side power distribution structures
on corresponding dies of the plurality of dies.
[0171] At operation 830, in some embodiments, a via structure is
formed adjacent to the first die. In some embodiments, forming the
via structure adjacent to the first die includes forming via
structures V adjacent to die D1 of IC package 100C as discussed
above with respect to FIG. 7C.
[0172] At operation 840, a common power distribution structure is
constructed on the back side power distribution structure of a die.
In various embodiments, constructing the common power distribution
structure on the back side power distribution structure of a die
includes constructing power distribution structures CPD1 and CPD2
on back side power distribution structures BSPD1 and BSPD3 of dies
D1 and D3 of IC package 100A as discussed above with respect to
FIG. 5C; constructing power distribution structure CPD1 on back
side power distribution structure BSPD1 of die D1 of IC package
100B as discussed above with respect to FIG. 6C; constructing one
or more of power distribution structures CPD1-CPD3 on back side
power distribution structures BSPD1-BSPD3 of dies D1-D3 of IC
package 100C as discussed above with respect to FIG. 7D; or
constructing power distribution structure CPD4 on one or more of
back side power distribution structures BSPD1-BSPD3 of dies D1-D3
of IC package 100C as discussed above with respect to FIG. 7F.
[0173] At operation 850, a via structure is formed adjacent to a
common power distribution structure. In some embodiments, forming
the via structure adjacent to the common power distribution
structure includes forming via structures V adjacent to one or more
of power distribution structures CPD1-CPD3 of IC package 100C as
discussed above with respect to FIG. 7E.
[0174] At operation 860, in some embodiments, a second common power
distribution structure is constructed on a first common power
distribution structure. In some embodiments, constructing the
second common power distribution structure on the first common
power distribution structure includes constructing power
distribution structure CPD4 on one or more of power distribution
structures CPD1-CPD3 of IC package 100C as discussed above with
respect to FIG. 7F.
[0175] At operation 870, the back side power distribution structure
of a die is bonded to a first or second common power distribution
structure of the IC package. Bonding the back side power
distribution structure of the die to the first or second common
power distribution structure of the IC package includes
electrically connecting the back side power distribution structure
of the die to the first or second common power distribution
structure.
[0176] In various embodiments, bonding the back side power
distribution structure of the die to the first or second common
power distribution structure includes bonding back side power
distribution structures BSPD2 and BSPD4 of dies D2 and D4 to power
distribution structures CPD1 and CPD2 of IC package 100A as
discussed above with respect to FIG. 5D; bonding back side power
distribution structures BSPD2 and BSPD3 of dies D2 and D3 to power
distribution structure CPD1 of IC package 100B as discussed above
with respect to FIG. 6D; or bonding one or more of back side power
distribution structures BSPD1-BSPD3 of dies D1-D3 to power
distribution structure CPD4 of IC package 100C as discussed above
with respect to FIG. 7G.
[0177] At operation 880, in some embodiments, one or more
additional manufacturing operations are performed on the first and
second dies of the IC package. In various embodiments, performing
the one or more additional manufacturing operations includes
constructing one or more IC package components in addition to those
discussed above with respect to operations 810-870, e.g., one or
more insulation layers DL, via structures V, and/or connective
bumps B as discussed above with respect to FIGS. 1A-1Cb and 5A-7G,
or the like.
[0178] In various embodiments, performing the one or more
additional manufacturing operations includes performing one or more
of a deposition operation, a removal operation, e.g., from a
carrier wafer, a soldering operation, a curing operation, an
encapsulation operation, or the like.
[0179] In various embodiments, performing the one or more
additional manufacturing operations includes forming a die stack by
detaching dies D1-D4 from carrier wafers C1-C4 and bonding dies D2
and D3 of IC package 100A to each other as discussed above with
respect to FIGS. 5E and 1A; detaching dies D2 and D3 from carrier
wafers C2 and C3, forming connecting bumps B, insulation layer DL,
and via structures V on common power distribution structure CPD1,
and attaching substrate INT1 to IC package 100B as discussed above
with respect to FIGS. 6E and 1B; or detaching dies D2 and D3 from
carrier wafer C5, forming connecting bumps B, and attaching
substrate INT1 to IC package 100C as discussed above with respect
to FIGS. 7G, 1Ca, and 1Cb.
[0180] By executing some or all of the operations of method 800, an
IC package, e.g., an IC package 100A-100C is formed including a
common power distribution structure electrically connected to back
side power distribution structures of each of at least two dies,
thereby obtaining the benefits discussed above with respect to IC
packages 100A-100C and IC structures depicted in FIGS. 2A-4D.
[0181] FIG. 9 is a flowchart of a method 900 of distributing power
in an IC package, in accordance with some embodiments. Method 900
is usable with an IC package, e.g., an IC package 100A-100C
discussed above with respect to FIGS. 1A-1Cb.
[0182] The sequence in which the operations of method 900 are
depicted in FIG. 9 is for illustration only; the operations of
method 900 are capable of being executed in sequences that differ
from that depicted in FIG. 9. In some embodiments, operations in
addition to those depicted in FIG. 9 are performed before, between,
during, and/or after the operations depicted in FIG. 9. In some
embodiments, the operations of method 900 are a subset of a method
of operating an IC, e.g., a processor, logic, memory, or signal
processing circuit, or the like.
[0183] At operation 910, a power supply voltage is received at a
first power distribution structure in the IC package. Receiving the
power supply voltage at the first power distribution structure
includes receiving the power supply voltage at a common power
distribution structure electrically connected to a second power
distribution structure positioned on a back side of a first die in
the IC package and to a third power distribution structure
positioned on a back side of a second die in the IC package.
[0184] In various embodiments, receiving the power supply voltage
at the first power distribution structure includes receiving the
power supply voltage at one or more of power distribution
structures CPD1-CPD4 discussed above with respect to FIGS.
1A-1Cb.
[0185] In some embodiments, receiving the power supply voltage at
the first power distribution structure includes receiving the power
supply voltage at an IC package component electrically connected to
the first power distribution structure. In some embodiments,
receiving the power supply voltage at the first power distribution
structure includes receiving the power supply voltage at a front
side of a die, e.g., a die D1-D3 discussed above with respect to
FIGS. 1A-1Cb. In some embodiments, receiving the power supply
voltage at the first power distribution structure includes
receiving the power supply voltage at a substrate, e.g., substrate
INT1 discussed above with respect to FIGS. 1B-1Cb or substrate INT2
discussed above with respect to FIGS. 1Ca and 1Cb.
[0186] In some embodiments, the power supply voltage is one power
supply voltage of a plurality of power supply voltages and
receiving the power supply voltage at the power distribution
structure includes receiving the plurality of power supply voltages
at the first power distribution structure. In some embodiments,
receiving the power supply voltage at the power distribution
structure includes receiving a reference voltage at the first power
distribution structure.
[0187] At operation 920, the power supply voltage is received from
the first power distribution structure at the second power
distribution structure, the second power distribution structure
being positioned on the back side of the first die in the IC
package. In some embodiments, receiving the power supply voltage
from the first power distribution structure at the second power
distribution structure includes receiving the power supply voltage
at a first one or more of back side power distribution structures
BSPD1-BSPD4 of dies D1-D4 discussed above with respect to FIGS.
1A-1Cb.
[0188] In some embodiments, the power supply voltage is one power
supply voltage of a plurality of power supply voltages and
receiving the power supply voltage from the first power
distribution structure at the second power distribution structure
includes receiving the plurality of power supply voltages from the
first power distribution structure at the second power distribution
structure. In some embodiments, receiving the power supply voltage
from the first power distribution structure at the second power
distribution structure includes receiving the reference voltage
from the first power distribution structure at the second power
distribution structure.
[0189] At operation 930, the power supply voltage is received from
the first power distribution structure at the third power
distribution structure, the third power distribution structure
being positioned on the back side of the second die in the IC
package.
[0190] In some embodiments, receiving the power supply voltage from
the first power distribution structure at the third power
distribution structure includes receiving the power supply voltage
at a second one or more of back side power distribution structures
BSPD1-BPD4 of dies D1-D4 discussed above with respect to FIGS.
1A-1Cb.
[0191] In some embodiments, receiving the power supply voltage from
the first power distribution structure at the third power
distribution structure includes receiving the power supply voltage
from the first power distribution structure at a fourth power
distribution structure, the fourth power distribution structure
being positioned on a back side of a third die in the IC package.
In some embodiments, receiving the power supply voltage from the
first power distribution structure at the fourth power distribution
structure includes receiving the power supply voltage at a third
one or more of back side power distribution structures BSPD1-BSPD4
of dies D1-D4 discussed above with respect to FIGS. 1A-1Cb.
[0192] In some embodiments, the power supply voltage is one power
supply voltage of a plurality of power supply voltages and
receiving the power supply voltage from the first power
distribution structure at the third power distribution structure
includes receiving the plurality of power supply voltages from the
first power distribution structure at the third power distribution
structure. In some embodiments, receiving the power supply voltage
from the first power distribution structure at the third power
distribution structure includes receiving the reference voltage
from the first power distribution structure at the third power
distribution structure.
[0193] By executing some or all of the operations of method 900,
one or more power supply voltage levels are distributed in an IC
package through a common power supply distribution structure
electrically connected to power distribution structures positioned
on back sides of each of a first and second die, thereby obtaining
the benefits discussed above with respect to IC packages 100A-100C
and IC structures depicted in FIGS. 2A-4D.
[0194] In some embodiments, an IC package includes a first die
including a front side and a back side, the front side including a
first signal routing structure, the back side including a first
power distribution structure, a second die including a front side
and a back side, the front side including a second signal routing
structure, the back side including a second power distribution
structure, and a third power distribution structure positioned
between the first and second power distribution structures and
electrically connected to each of the first and second power
distribution structures. In some embodiments, the IC package
includes a third die including a front side and a back side, the
front side including a third signal routing structure electrically
connected to the first signal routing structure, the back side
including a fourth power distribution structure, a fourth die
including a front side and a back side, the front side including a
fourth signal routing structure, the back side including a fifth
power distribution structure, and a sixth power distribution
structure positioned between the fourth and fifth power
distribution structures and electrically connected to each of the
fourth and fifth power distribution structures. In some
embodiments, the IC package includes a third die including a front
side and a back side, the front side including a third signal
routing structure and the back side including a fourth power
distribution structure electrically connected to the third power
distribution structure. In some embodiments, the IC package
includes a first substrate electrically connected to each of the
first signal routing structure and the third signal routing
structure. In some embodiments, the IC package includes a second
substrate electrically connected to the second signal routing
structure. In some embodiments, the IC package includes a plurality
of via structures electrically connected to each of the first and
second substrates, wherein the plurality of via structures extends
through the third power distribution structure and is electrically
isolated from the third power distribution structure. In some
embodiments, the IC package includes a fourth die electrically
connected to the second substrate, wherein the second substrate is
positioned between the second die and the fourth die. In some
embodiments, the IC package includes a via structure electrically
connected to the third power distribution structure and the second
substrate. In some embodiments, at least one of the back side of
the first die or the back side of the second die includes a power
rail. In some embodiments, each of the first, second, and third
power distribution structures includes a mesh structure.
[0195] In some embodiments, a method of forming an IC package
includes constructing a first power distribution structure on a
first die included in the IC package, thereby electrically
connecting the first power distribution structure to a second power
distribution structure positioned on a back side of the first die,
and bonding a third power distribution structure to the first power
distribution structure, the third power distribution structure
being positioned on a back side of a second die. In some
embodiments, constructing the first power distribution structure on
the first die includes forming a mesh structure on a mesh structure
of the second power distribution structure. In some embodiments,
the method includes forming a via structure extending through the
mesh structure of the first power distribution structure and
electrically isolated from the first power distribution structure.
In some embodiments, the third power distribution structure
includes topmost metal segments extending in a first direction and
having a first pitch, the first power distribution structure
includes topmost metal segments extending in a second direction and
having the first pitch, and bonding the third power distribution
structure to the first power distribution structure includes
aligning the first direction with the second direction, the topmost
metal segments of the third power distribution structure thereby
aligning with the topmost metal segments of the first power
distribution structure. In some embodiments, the third power
distribution structure includes topmost metal segments extending in
a first direction, the first power distribution structure comprises
topmost metal segments extending in a second direction, and bonding
the third power distribution structure to the first power
distribution structure includes aligning the first direction
perpendicular to the second direction, thereby aligning the topmost
metal segments of the third power distribution structure orthogonal
to the topmost metal segments of the first power distribution
structure. In some embodiments, bonding the third power
distribution structure to the first power distribution structure
includes performing a thermo-compression operation. In some
embodiments, the method includes constructing a fourth power
distribution structure electrically connected to a fifth power
distribution structure positioned on a back side of a third die,
bonding a sixth power distribution structure to the fourth power
distribution structure, the sixth power distribution structure
being positioned on a back side of a fourth die, and including the
third die and the fourth die in the IC package. In some
embodiments, the method includes bonding a fourth power
distribution structure to the first power distribution structure,
the fourth power distribution structure being positioned on a back
side of a third die.
[0196] In some embodiments, a method of distributing power in an IC
package includes receiving a power supply voltage at a first power
distribution structure in the IC package, receiving the power
supply voltage from the first power distribution structure at a
second power distribution structure, the second power distribution
structure being positioned on a back side of a first die in the IC
package, and receiving the power supply voltage from the first
power distribution structure at a third power distribution
structure, the third power distribution structure being positioned
on a back side of a second die in the IC package. In some
embodiments, the method includes receiving a reference voltage at
the first power distribution structure, receiving the reference
voltage from the first power distribution structure at the second
power distribution structure, and receiving the reference voltage
from the first power distribution structure at the third power
distribution structure.
[0197] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
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