U.S. patent application number 16/686393 was filed with the patent office on 2021-05-20 for static random-access memory cell design.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to RUQIANG BAO, Dechao Guo, Junli Wang, Heng Wu, Lan Yu.
Application Number | 20210151096 16/686393 |
Document ID | / |
Family ID | 1000004518961 |
Filed Date | 2021-05-20 |
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United States Patent
Application |
20210151096 |
Kind Code |
A1 |
Yu; Lan ; et al. |
May 20, 2021 |
STATIC RANDOM-ACCESS MEMORY CELL DESIGN
Abstract
6T-SRAM cell designs for larger SRAM arrays and methods of
manufacture generally include a single fin device for both nFET
(pass-gate (PG) and pull-down (PD)) and pFET (pull-up (PU). The
pFET can be configured with a smaller effective channel width
(Weff) than the nFET or with a smaller active fin height. An SRAM
big cell consumes the (111) 6t-SRAM design area while provide
different Weff ratios other than 1:1 for PU/PD or PU/PG as can be
desired for different SRAM designs.
Inventors: |
Yu; Lan; (Voorheesville,
NY) ; Wang; Junli; (Slingerlands, NY) ; Wu;
Heng; (Guilderland, NY) ; BAO; RUQIANG;
(Niskayuna, NY) ; Guo; Dechao; (Niskayuna,
NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
1000004518961 |
Appl. No.: |
16/686393 |
Filed: |
November 18, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/845 20130101;
H01L 27/1104 20130101; G11C 11/412 20130101; H01L 21/3212
20130101 |
International
Class: |
G11C 11/412 20060101
G11C011/412; H01L 27/11 20060101 H01L027/11; H01L 21/84 20060101
H01L021/84 |
Claims
1. A memory array comprising: at least one (111) six transistor
static random-access memory (6T-SRAM) comprising a single fin
pass-gate n-type doped field effect transistor, a single fin
pull-down n-type doped field effect transistor, and a single fin
pull-up p-type doped field effect transistor.
2. The memory array of claim 1, wherein the single fin pull-up
p-type doped field. effect transistor has an effective channel
width greater than the single fin pass-gate and pull-down n-type
doped field effect transistors.
3. The memory array of claim 1, wherein the single fin pull-up
p-type doped field effect transistor has an active fin height less
than the single fin pass-gate and pull-down n-type doped field
effect transistors.
4. The memory array of claim 1, wherein the single fin pull-up
p-type doped field effect transistor has an active area less than
the single fin pass-gate and pull-down n-type doped field effect
transistors.
5. The memory array of claim 1, wherein the (111) 6T-SRAM cell has
an effective channel width ratio for the pull-up and pull-down
transistors that is less than 1:1.
6. The memory array of claim 1, wherein the (111) 6T-SRAM cell has
an effective channel width ratio for the pull-up and pass-gate
transistors that is less than 1:1.
7. The memory array of claim 1. wherein the single fin pull-up
p-type doped field effect transistor has an effective channel width
less than each of the single fin pass-gate and pull-down n-type
doped field effect transistors, and wherein the single fin
pass-gate and pull-clown n-type doped field effect transistors have
equal effective channel widths.
8. The memory array of claim 1, wherein the at least one (111)
6T-SRAM cell comprises a silicon substrate.
9. A (111) six transistor static random-access memory (6T-SRAM)
cell comprising: a single fin pass-gate n-type doped field effect
transistor; a single fin pull-down n-type doped field effect
transistor; and a single fin pull-up p-type doped field effect
transistor.
10. The 6T-SRAM cell of claim 9, wherein the single fin pull-up
p-type doped field effect transistor has an effective channel width
greater than the single fin pass-gate and pull-down n-type doped
field effect transistors.
11. The 6T-SRAM cell of claim 9, wherein the single fin pull-up
p-type doped field. effect transistor has an active fin height less
than the single fin pass-gate and pull-down n-type doped field
effect transistors.
12. The 6T-SRAM cell of claim 9, wherein the single fin pull-up
p-type doped field effect transistor has an active area less than
the single fin pass-gate and pull-down n-type doped field effect
transistors.
13. The 6T-SRAM cell of claim 9, wherein the (111) 6T-SRAM cell has
an effective channel width ratio for the pull-up and pull-down
transistors that is less than 1:1.
14. The 6T-SRAM cell of claim 9, wherein the (111) 6T-SRAM cell has
an effective channel width ratio for the pull-up and pass-gate
transistors that is less than 1:1.
15. The 6T-SRAM cell of claim 9, wherein the single fin pull-up
p-type doped field effect transistor has an effective channel width
less than each of the single fin pass-gate and pull-down n-type
doped field effect transistors, and wherein the single fin
pass-gate and pull-down n-type doped field effect transistors have
equal effective channel widths.
16. A method for forming a (111) six transistor static
random-access memory (6T-SRAM) cell comprising: depositing a
nitride layer onto a silicon substrate; forming a trench feature in
the silicon substrate to form exposed portions of the silicon
substrate; epitaxially growing a silicon germanium layer onto the
exposed portions of the silicon substrate in the trench feature;
selectively removing the nitride layer; epitaxially growing silicon
the silicon substrate and an exposed upper surface of the silicon
germanium layer; directionally etching the silicon to form a
plurality of fins, wherein at least one of the fins comprises a
portion of the silicon germanium layer; and subjecting the silicon
substrate to p-type doping to define a pFET region corresponding to
the at least one fin comprising the portion of the silicon
germanium layer and n-type doping to define a nFET region
corresponding to the fins consisting of silicon.
17. The method of claim 16, wherein selectively removing the
nitride layer comprises a chemical planarization process.
18. The method of claim 16, wherein the trench feature has a depth
that controls an effective channel width of the fin comprising the
portion of the silicon germanium layer.
19. The method of claim 16 further comprising selectively removing
the silicon germanium layer to change a height of the fin in the
pFET region relative to a height of the fin in the nFET region,
wherein the height of the fin in the pFET region is less than the
height of the fin in the nFET region.
20. The method of claim 16, wherein the at least one fin comprising
the portion of the silicon germanium layer in the pFET region is in
a single fin pull-up transistor configuration and the fins
consisting of silicon in the nFET region are in single fin
pull-down and single fin pass-gate transistor configurations.
Description
BACKGROUND
[0001] The present invention is generally directed to a
semiconductor device including static random-access memory (SRAM)
cell designs, and more particularly, to fin field effect
transistors (finFETs) for six transistor SRAM cell designs for use
in advanced technology nodes.
[0002] Transistors have been continuously scaled down in size to
increase performance and reduce power consumption. This has led to
the advent of more efficient, scalable electronic devices and
increased user experiences. However, as transistors have decreased
in size, the complexity of manufacturing them for optimal
performance has increased. One area of challenge faced by
manufacturers of transistors is cell layout variability for static
random-access memory (SRAM) cell designs. As the cell size of SRAM
shrinks, variability in design layout becomes limited.
[0003] FinFET transistor structures have been developed as an
alternative to bulk-Si MOSFET structures for improved scalability.
FinFET transistors generally utilize a silicon fin (rather than a
planar Si surface as in MOSFETs) as the channel/body; the gate
electrode straddles the fin.
SUMMARY
[0004] Embodiments of the present invention are directed to
structures and methods of fabricating a semiconductor device. In
one or more embodiments of the invention, a memory array includes
at least one (111) six transistor static random-access memory
(6T-SRAM) cell. The (111) 6T-SRAM includes a single fin pass-gate
n-type doped field effect transistor, a single fin pull-down n-type
doped field effect transistor, and a single fin pull-up p-type
doped field effect transistor.
[0005] In one or more embodiments of the invention, a method for
forming a (111) 6T-SRAM cell includes depositing a nitride layer
onto a silicon substrate. A trench feature is formed in the silicon
substrate to form exposed portions of the silicon substrate. A
silicon germanium layer is epitaxially grown onto the exposed
portions of the silicon substrate and in the trench feature. The
nitride layer is selectively removed, and silicon is epitaxially
grown on the silicon substrate and an exposed upper surface of the
silicon germanium layer. A plurality of fins is formed by
directionally etching the silicon wherein at least one of the fins
includes a portion of the silicon germanium layer. The silicon
substrate is subjected to p-type doping to define a pFET region
corresponding to the at least one fin including the portion of the
silicon germanium layer, and n-type doping to define a nFET region
corresponding to the fins consisting of silicon.
[0006] Additional technical features and benefits are realized
through the techniques of the present invention. Embodiments and
aspects of the invention are described in detail herein and are
considered a part of the claimed subject matter. For a better
understanding, refer to the detailed description and to the
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The specifics of the exclusive rights described herein are
particularly pointed out and distinctly claimed in the claims at
the conclusion of the specification. The foregoing and other
features and advantages of the embodiments of the invention are
apparent from the following detailed description taken in
conjunction with the accompanying drawings in which:
[0008] FIG. 1 are top down views comparing a prior art (122)
6T-SRAM cell and an exemplary (111) 6T-SRAM cell according to
embodiments of the invention;
[0009] FIG. 2 is a sectional view depicting a silicon substrate
subsequent to deposition of a silicon nitride layer thereon
according to embodiments of the invention;
[0010] FIG. 3 is a sectional view of FIG. 2 subsequent to
patterning of a trench feature into the silicon substrate according
to embodiments of the invention;
[0011] FIG. 4 is a sectional view of FIG. 3 subsequent to epitaxial
growth of silicon germanium in the trench feature according to
embodiments of the invention;
[0012] FIG. 5 is a sectional view of FIG. 4 subsequent to a
planarization process to remove the silicon nitride layer according
to embodiments of the invention;
[0013] FIG. 6 is a sectional view of FIG. 5 subsequent to epitaxial
growth of silicon according to embodiments of the invention;
[0014] FIG. 7 is a sectional view of FIG. 6 subsequent to a
directional etch process to form fins according to embodiments of
the invention;
[0015] FIG. 8 is a sectional view of FIG. 7 subsequent to an oxide
deposition to reveal the fins according to embodiments of the
invention;
[0016] FIG. 9 depicts a top down view and sectional views taken
along lines X-X, Y-Y and Y'-Y' of the structure of FIG. 8
subsequent to post dummy PC directional etch according to
embodiments of the invention;
[0017] FIG. 10 depicts a top down view and sectional views taken
along lines X-X, Y-Y and Y'-Y' of the structure of FIG. 9
subsequent to selective silicon germanium release according to
embodiments of the invention;
[0018] FIG. 11 depicts a top down view and sectional views taken
along lines X-X, Y-Y and Y'-Y' of the structure of FIG. 10
subsequent to deposition of a conformal spacer layer according to
embodiments of the invention;
[0019] FIG. 12 depicts a top down view and sectional views taken
along lines X-X, Y-Y and Y'-Y' of the structure of FIG. 11
subsequent to spacer pull-down, fin recess and epitaxial growth
processing according to embodiments of the invention;
[0020] FIG. 13 depicts a top down view and sectional views taken
along lines X-X, Y-Y and Y'-Y' of the structure of FIG. 12
subsequent to deposition of a dielectric layer to form the (111)
6T-SRAM cell according to embodiments of the invention;
[0021] FIG. 14 depicts a sectional view of the structure of FIG. 5
subsequent to a directional etch process according to embodiments
of the invention;
[0022] FIG. 15 depicts a sectional view of the structure of FIG. 14
subsequent to fin reveal according to embodiments of the
invention;
[0023] FIG. 16 depicts a sectional view of the structure of FIG. 15
subsequent to selective removal of the silicon germanium layer
according to embodiments of the invention; and
[0024] FIG. 17 depicts a sectional view of the structure of FIG. 16
subsequent to forming the gate structure according to embodiments
of the invention.
[0025] The diagrams depicted herein are illustrative. There can be
many variations to the diagram or the operations described therein
without departing from the spirit of the invention. All of these
variations are considered a part of the specification.
[0026] In the accompanying figures and following detailed
description of the disclosed embodiments, the various elements
illustrated in the figures are provided with two or three digit
reference numbers. With minor exceptions, the leftmost digit(s) of
each reference number correspond to the figure in which its element
is first illustrated.
DETAILED DESCRIPTION
[0027] The present invention is generally directed to fin field
effect transistors for static random-access memory cell designs
(finFET SRAM) and processes of manufacturing the same. More
particularly, the present invention is generally directed to high
performance and high density 6 transistor (6T) finFET SRAM cell
designs. The high performance and high density 6T-SRAM cell designs
described herein provide flexible SRAM design without area penalty.
As will be described in greater detail below, in one or more
embodiments of the invention, the high performance and dense
6T-SRAM cell design are (111) 6T-SRAM cells including a single fin
for each nFET (e.g., the pull-down (PD) transistors and the
pass-gate (PG) transistors) and for each pFET (e.g., the pull-up
(PU) transistors). In these embodiments of the invention, the nFET
has a total 1-fin effective channel width (Weff) whereas the pFET
has a smaller Weff than the 1-fin. The smaller pFET Weff can be
provided by adjusting the active fin height such that the larger
SRAM array can consume the dense (111) SRAM cell design area while
providing different Weff ratios than 1:1 for PU/PD or PU/PG as can
be desired for different applications.
[0028] Prior high performance 6T-SRAM cell designs generally relied
on fabricating stronger nFETs than pFETs, which was realized by
utilizing more fins for the nFET than the pFET. FIG. 1 illustrates
a top down view of a typical prior (122) 6T-SRAM cell design 10,
which is compared to an exemplary (111) dense 6T-SRAM cell design
50 in accordance with the present invention, wherein the acronyms
WL indicates a word line, BL indicates a bit line, BLB indicates a
complementary bit line, VSS indicates voltage source supply, VDD
indicates voltage drain discharge. Q indicates storage node and QB
indicates another storage node. The illustrated (122) 6T-SRAM cell
design 10 utilizes two finFETs for each nFET (finFETs 12, 14 and
16, 18 for each PG/PD, respectively), and one finFET for each pFET
(single finFET 20 and 22 for each PU). In contrast, the (111)
6T-SRAM cell design 50 uses a single fin for both nFETs (single
finFETs 52, 54 for each PG/PD) and pFETs (single finFETs 56, 58 for
each PU), which will be described in greater detail below. As is
clearly shown, the use of two finFETs for each nFET in the (122)
6T-SRAM cell design results in an increased SRAM cell area due to
the presence of more finFETs per unit area relative to the
exemplary (111) 6T-SRAM cell design.
[0029] Various embodiments of the present invention are described
herein with reference to the related drawings. Alternative
embodiments can be devised without departing from the scope of this
invention. Although various connections and positional
relationships (e.g., over, below, adjacent, etc.) are set forth
between elements in the following description and in the drawings,
persons skilled in the art will recognize that many of the
positional relationships described herein are
orientation-independent when the described functionality is
maintained even though the orientation is changed. These
connections and/or positional relationships, unless specified
otherwise, can be direct or indirect, and the present invention is
not intended to be limiting in this respect. Accordingly, a
coupling of entities can refer to either a direct or an indirect
coupling, and a positional relationship between entities can be a
direct or indirect positional relationship. As an example of an
indirect positional relationship, references in the present
description to forming layer "A" over layer "B" include situations
in which one or more intermediate layers (e.g., layer "C") is
between layer "A" and layer "B" as long as the relevant
characteristics and functionalities of layer "A" and layer "B" are
not substantially changed by the intermediate layer(s).
[0030] The following definitions and abbreviations are to be used
for the interpretation of the claims and the specification. As used
herein, the terms "comprises," "comprising," "includes,"
"including," "has," "having," "contains" or "containing," or any
other variation thereof, are intended to cover a non-exclusive
inclusion. For example, a composition, a mixture, process, method,
article, or apparatus that comprises a list of elements is not
necessarily limited to only those elements but can include other
elements not expressly listed or inherent to such composition,
mixture, process, method, article, or apparatus.
[0031] Additionally, the term "exemplary" is used herein to mean
"serving as an example, instance or illustration." Any embodiment
or design described herein as "exemplary" is not necessarily to be
construed as preferred or advantageous over other embodiments or
designs. The terms "at least one" and "one or more" are understood
to include any integer number greater than or equal to one, i.e.
one, two, three, four, etc. The terms "a plurality" are understood
to include any integer number greater than or equal to two, i.e.
two, three, four, five, etc. The term "connection" can include an
indirect "connection" and a direct "connection."
[0032] References in the specification to "one embodiment," "an
embodiment," "an example embodiment," etc., indicate that the
embodiment described can include a particular feature, structure,
or characteristic, but every embodiment may or may not include the
particular feature, structure, or characteristic. Moreover, such
phrases are not necessarily referring to the same embodiment.
Further, when a particular feature, structure, or characteristic is
described in connection with an embodiment, it is submitted that it
is within the knowledge of one skilled in the art to affect such
feature, structure, or characteristic in connection with other
embodiments whether or not explicitly described.
[0033] For purposes of the description hereinafter, the terms
"upper," "lower," "right," "left," "vertical," "horizontal," "top,"
"bottom," and derivatives thereof shall relate to the described
structures and methods, as oriented in the drawing figures. The
terms "overlying," "atop," "on top," "positioned on" or "positioned
atop" mean that a first element, such as a first structure, is
present on a second element, such as a second structure, wherein
intervening elements such as an interface structure can be present
between the first element and the second element. The term "direct
contact" means that a first element, such as a first structure, and
a second element, such as a second structure, are connected without
any intermediary conducting, insulating or semiconductor layers at
the interface of the two elements.
[0034] The phrase "selective to," such as, for example, "a first
element selective to a second element," means that the first
element can be etched and the second element can act as an etch
stop.
[0035] The terms "about," "substantially," "approximately," and
variations thereof, are intended to include the degree of error
associated with measurement of the particular quantity based upon
the equipment available at the time of filing the application. For
example, "about" can include a range of .+-.8% or 5%, or 2% of a
given value.
[0036] As used herein, "p-type" refers to the addition of
impurities to an intrinsic semiconductor that creates deficiencies
of valence electrons. In a silicon-containing substrate, examples
of p-type dopants, i.e., impurities, include but are not limited
to: boron, aluminum, gallium and indium.
[0037] As used herein, "n-type" refers to the addition of
impurities that contributes free electrons to an intrinsic
semiconductor. In a silicon containing substrate examples of n-type
dopants, i.e., impurities, include but are not limited to antimony,
arsenic and phosphorous.
[0038] As previously noted herein, for the sake of brevity,
conventional techniques related to semiconductor device and
integrated circuit (IC) fabrication may or may not be described in
detail herein. By way of background, however, a more general
description of the semiconductor device fabrication processes that
can be utilized in implementing one or more embodiments of the
present invention will now be provided. Although specific
fabrication operations used in implementing one or more embodiments
of the present invention can be individually known, the described
combination of operations and/or resulting structures of the
present invention are unique. Thus, the unique combination of the
operations described in connection with the fabrication of a
semiconductor device according to the present invention utilize a
variety of individually known physical and chemical processes
performed on a semiconductor (e.g., silicon) substrate, some of
which are described in the immediately following paragraphs.
[0039] In general, the various processes used to form a micro-chip
that will be packaged into an IC fall into four general categories,
namely, film deposition, removal/etching, semiconductor doping and
patterning/lithography. Deposition is any process that grows,
coats, or otherwise transfers a material onto the wafer. Available
technologies include physical vapor deposition (PVD), chemical
vapor deposition (CVD), electrochemical deposition (ECD), molecular
beam epitaxy (MBE) and more recently, atomic layer deposition (ALD)
among others. Removal/etching is any process that removes material
from the wafer. Examples include etch processes (either wet or
dry), and chemical-mechanical planarization (CMP), and the like.
Semiconductor doping is the modification of electrical properties
by doping, for example, transistor sources and drains, generally by
diffusion and/or by ion implantation. These doping processes are
followed by furnace annealing or by rapid thermal annealing (RTA).
Annealing serves to activate the implanted dopants. Films of both
conductors (e.g., poly-silicon, aluminum, copper, etc.) and
insulators (e.g., various forms of silicon dioxide, silicon
nitride, etc.) are used to connect and isolate transistors and
their components. Selective doping of various regions of the
semiconductor substrate allows the conductivity of the substrate to
be changed with the application of voltage. By creating structures
of these various components, millions of transistors can be built
and wired together to form the complex circuitry of a modern
microelectronic device.
[0040] Semiconductor lithography is the formation of
three-dimensional relief images or patterns on the semiconductor
substrate for subsequent transfer of the pattern to the substrate.
In semiconductor lithography, the patterns are formed by a light
sensitive polymer called a photo-resist. To build the complex
structures that make up a transistor and the many wires that
connect the millions of transistors of a circuit, lithography and
etch pattern transfer steps are repeated multiple times. Each
pattern being printed on the wafer is aligned to the previously
formed patterns and slowly the conductors, insulators and
selectively doped regions are built up to form the final
device.
[0041] Turning now to a more detailed description of aspects of the
present invention, FIG. 2 depicts a sectional view a semiconductor
structure 100 including a silicon substrate 112 and a nitride layer
114 such as, for example, silicon nitride or boron nitride,
deposited thereon for fabricating fins in the nFET and pFET regions
such as those provided in the (111) 6T-SRAM cell design previously
shown in FIG. 1.
[0042] Although reference is made to a silicon substrate, the
substrate 112 can be any suitable substrate material, such as, for
example, any semiconductor material including, but not limited to,
Si, Ge, SiGe, SiC, SiGeC, II/IV, and III/V compound semiconductors
such as, for example, InAs, GaAs, and InP. Multilayers of these
semiconductor materials can also be used as substrate. In one or
more embodiments of the invention, and when substrate 112 is a
remaining semiconductor material portion of a bulk semiconductor
substrate, the substrate 112 can be of a single crystalline
semiconductor material, such as, for example, single crystalline
silicon. In some embodiments of the invention, the crystal
orientation of the remaining semiconductor portion of the bulk
semiconductor substrate can be {100}, {110}, {111} or any other of
the well-known crystallographic orientations. In some embodiments
of the invention, and when substrate 112 is a remaining
semiconductor material portion of a bulk semiconductor substrate.
As will be described in greater detail below, each semiconductor
fin can include the same semiconductor material, or a different
semiconductor material, from substrate 112.
[0043] In another embodiment, substrate 112 includes at least an
insulator layer of a semiconductor-on-insulator (SOI) substrate
(not specifically shown). Although not specifically shown, one
skilled in the art understands that an SOI substrate includes a
handle substrate, an insulator layer located on an upper surface of
the handle substrate, and a semiconductor layer located on an
uppermost surface of the insulator layer. The handle substrate
provides mechanical support for the insulator layer and the
semiconductor layer. The semiconductor layer of such an SOI
substrate can be processed into semiconductor fins.
[0044] The handle substrate and the semiconductor layer of the SOI
substrate can include the same, or different, semiconductor
material. The term "semiconductor" as used herein in connection
with the semiconductor material of the handle substrate and the
semiconductor layer denotes any semiconductor material including,
for example, Si, Ge, SiGe, SiC, SiGeC, II/VI, and III/V compound
semiconductors such as, for example, InAs, GaAs, or InP.
Multilayers of these semiconductor materials can also be used as
the semiconductor material of the handle substrate and the
semiconductor layer. In one or more embodiments of the invention,
the handle substrate and the semiconductor layer are both formed of
silicon. In some embodiments of the invention, the handle substrate
is a non-semiconductor material including, for example, a
dielectric material and/or a conductive material. In yet other
embodiments of the invention, the handle substrate can be omitted
and the substrate 104 includes only an insulator layer.
[0045] In one or more embodiments of the invention, the handle
substrate and the semiconductor layer can have the same or
different crystal orientation. For example, the crystal orientation
of the handle substrate and/or the semiconductor layer can be
{100}, {110}, or {111}. Other crystallographic orientations besides
those specifically mentioned can also be used in the present
application. The handle substrate and/or the semiconductor layer of
the SOI substrate can be a single crystalline semiconductor
material, a polycrystalline material, or an amorphous material.
Typically, at least the semiconductor layer is a single crystalline
semiconductor material.
[0046] In FIG. 3, a trench feature 116 is formed and generally
corresponds to where the pFET fin will be formed. As will be
discussed in greater detail, the depth of the trench feature can be
used to control the final Weff of the pFET for SRAM. The trench
feature 166 can be formed by selectively patterning the nitride
layer to form an opening therein followed by an anisiotropic etch.
The etching apparatus used in carrying out the anisotropic etch can
include any commercially available reactive ion etching (RIE)
apparatus, or magnetically enhanced reactive ion etching (MERIE)
apparatus, capable of supporting a wafer of the size desired to be
etched in which gases of the type used herein can be introduced at
the flow rates to be discussed and a plasma maintained at the power
levels required for the process. Such apparatus will be generally
referred to herein as RIE apparatus, whether magnetically enhanced
or not. Examples of such commercially available apparatus include
the Precision 5000 magnetically enhanced reactive ion etcher
available from Applied Materials, Inc.; the Rainbow reactive ion
etcher by Lam; the reactive ion apparatus by Tegal Company; the
Quad reactive ion etcher by Drytek, and reactive ion exchange tools
available from Tokyo Electron Limited.
[0047] By way of example, the trench feature 116 can formed by
optical lithography and etching. The lithographic step can include
forming a photoresist (organic, inorganic or hybrid) atop the
nitride layer on the substrate. The photoresist can be formed using
conventional deposition techniques such chemical vapor deposition,
plasma vapor deposition, sputtering, dip coating, spin-on coating,
brushing, spraying and other like deposition techniques can be
employed. Following formation of the photoresist, the photoresist
is exposed to a desired pattern of radiation such as X-ray
radiation, extreme ultraviolet (EUV) radiation, electron beam
radiation or the like. Next, the exposed photoresist is developed
utilizing a conventional resist development process.
[0048] After the development step, the etching step can be
performed to transfer the pattern from the patterned photoresist
into the interlayer dielectric. The etching step used in forming
the at least one opening can include a dry etching process
(including, for example, reactive ion etching, ion beam etching,
plasma etching or laser ablation), a wet chemical etching process
or any combination thereof.
[0049] FIG. 4 depicts a sectional view of the structure 100 of FIG.
3 subsequent to epitaxial growth of a silicon-germanium (SiGe)
layer 118 on the exposed surfaces of the silicon substrate, i.e.,
epitaxial growth of the SiGe layer within the trench feature 116 as
shown. Epitaxial growth is selective and does not form on the
non-crystalline silicon nitride surface.
[0050] The SiGe layer can be epitaxiall formed, for example, by a
selective epitaxial process using a combination of
silicon-containing gas, a germanium-containing gas, a carrier gas,
and optionally, an etchant gas. The silicon containing gas can be a
gas such as silane (SiH.sub.4), dichlorosilane (SiH.sub.2Cl.sub.2),
disilane (Si.sub.2H.sub.6), trisilane (Si.sub.3H.sub.8) or
tetrasilane (Si.sub.4H.sub.10). The germanium containing gas can be
a gas such as germane (GeH.sub.4) or digermane (Ge.sub.2H.sub.6).
The carrier gas can be a gas such as nitrogen, hydrogen, or argon.
The optional etchant gas can be a gas such as hydrogen chloride
(HCl) or chlorine (Cl.sub.2). The formation can occur at a
temperature ranging from about 450.degree. C. to about 900.degree.
C. The SiGe layer can have a Ge concentration of about 15% to about
100% in one or more embodiments of the invention, a Ge
concentration from about 20% to about 60% in other embodiments of
the invention, and a Ge concentration from about 20% to about 40%
in still other embodiments of the invention.
[0051] FIG. 5 depicts a sectional view of the structure 100 of FIG.
4 subsequent to planarization to the silicon germanium layer 118
effectively removing the nitride layer 114 from the substrate 112.
The planarization process can include, for example, a chemical
mechanical polishing (CMP) process, which planarizes the surface of
the interconnect structure by a combination of chemical and
mechanical forces generally known in the art. By way of example,
CMP can remove material through the physical grinding of a slurry
containing abrasive particles such as silica, as well as through
chemical action as a result of oxidizing agents such as hydrogen
peroxide contained in the slurry.
[0052] FIG. 6 depicts a sectional view of the structure 100 of FIG.
5 subsequent to epitaxial growth of a crystalline silicon layer 120
onto the substrate 112, which embeds the silicon germanium layer
118.
[0053] FIG. 7 depicts a sectional view of the structure 100 of FIG.
6 subsequent to a directional etch process using RIE, for example,
to further define fins 122, 124. Fin 122 will be utilized in the
pFET region and fin 124 will be utilized in the nFET. The fins 122,
124 formed in this manner can be used for forming the fins used in
the (111) 6T-SRAMc ell design such as that previously shown in FIG.
1.
[0054] FIG. 8 depicts a sectional view of the structure 100 of FIG.
6 subsequent to deposition of an isolation layer 126 such as an
oxide. The isolation layer can be etched back exposing at least a
portion of the fins 122, 124 stopping at silicon 112 underlying the
silicon germanium portion 118 in fin 122. Any etch with good
uniformity and etch rate control can be employed. By way of
example, the oxide layer can be recessed with are etchant including
a fluorine ion, such as HF. In some embodiments of the invention,
isolation layer 126 is recessed using a commonly known anisotropic
etch, such as a plasma or reactive ion etch (RIE) process using an
etchant gas such as, but not limited to, hexafluorethane
(C.sub.2F.sub.6). In a further embodiment, an anisotropic etch can
be followed by an isotropic etch, such as a commonly known dry
process using a gas such as nitrogen trifluoride (NF.sub.3), or a
wet chemical etch such as hydrofluoric acid (HF), to completely
remove isolation from at least a portion of the fin sidewalls.
Alternatively, only a portion of the unprotected isolation layer is
removed during the recess etch.
[0055] FIG. 9 provides a top down view and sectional views taken
along lines X-X, Y-Y (pFET) and Y'-Y' (nFET) of the structure of
FIG. 8 subsequent to a dummy PC RIE process for forming gate stack
128. Any known composition and manner of forming the gate stack 128
can be utilized. For example, the gate stack can be formed by
blanket depositing a gate electrode material over the substrate and
then patterning the gate electrode material. The gate electrodes
can include metals such as, but not limited to, tungsten, tantalum
nitride, titanium nitride or titanium silicide, nickel silicide, or
cobalt silicide. In still other embodiments of the invention, the
gate electrode includes silicides. In other embodiments of the
present invention, the gate electrode can be formed using
"replacement gate" methods. In such embodiments of the invention,
the gate electrode utilizes a fill and polish technique similar to
those commonly employed in damascene metallization technology.
[0056] The gate stack 128 can include a deposited dielectric or a
grown dielectric and a gate electrode. In an embodiment of the
present invention, the gate dielectric layer is a silicon dioxide
dielectric film grown with a dry/wet oxidation process. In an
embodiment of the present invention, the gate dielectric is a
deposited high dielectric constant (high-K) metal oxide dielectric,
such as, but not limited to, tantalum pentaoxide, titanium oxide,
hafnium oxide, zirconium oxide, aluminum oxide, or another high-K
dielectric, such as barium strontium titanate, (BST). The high-K
dielectric film can be formed by well-known techniques, such as
chemical vapor deposition (CVD) and atomic layer deposition (ALD).
A hardmask 130 can be used to pattern the gate stacks 128.
[0057] FIG. 10 provides a top down view and sectional views taken
along lines X-X, Y-Y(pFET) and Y'-Y' (nFET) of the structure of
FIG. 9 subsequent to selective release of the silicon-germanium in
fin 122 to form a space 132. Selective release of the silicon 118
can include a dry or wet etch process. By way of example, the
silicon germanium layer can be removed by exposure to gaseous
hydrochloric acid.
[0058] FIG. 11 provides a top down view and sectional views taken
along lines X-X, Y-Y (pFET) and Y'-Y' (nFET) of the structure of
FIG. 10 subsequent to atomic layer deposition of a spacer material
into the space 132 and about the gate stack 128 to form a conformal
spacer layer 134.
[0059] FIG. 12 provides a top down view and sectional views taken
along lines X-X, Y-Y (pFET) and Y'-Y' (nFET) of the structure of
FIG. 11 subsequent to spacer pull-down, fin recess and epitaxial
growth. The spacer pull-down and fin recess formation include
anisotropically etching the spacer layer 134 to the silicon 120
between fins 122, 124 to remove the spacer layer followed by
further etching to silicon 112. A RIE process can be used for the
spacer pull-down and fin recess formation 134.
[0060] A single-crystalline silicon layer is then epitaxially grown
on the exposed silicon 112, which is subsequently doped to form
source and drain regions 140, 142 adjacent the channel region. For
the pFET transistor provided in the sectional view Y-Y, the silicon
140 is doped to p-type conductivity and to a concentration of
1.times.10.sup.19-1.times.10.sup.21 atoms/cm.sup.3. For the nFET
transistor provided in the sectional view Y'-Y', the silicon is
doped with n-type conductivity ions to a concentration of
1.times.10.sup.19-1.times.10.sup.21 atoms/cm.sup.3. It should be
apparent that in the case of a pFET S/D epi, the semiconductor
material can be heavily doped with p-type dopants, such as B
whereas for nFET S/D epi, the semiconductor material can be heavily
doped with n-type dopants, such as P, As, and the like.
[0061] FIG. 13 provides a top down view and sectional views taken
along lines X-X, Y-Y and Y'-Y' of the structure of FIG. 12
subsequent to deposition of an interlayer dielectric 150 and metal
gate 152 to form the final structure, which is suitable of use for
integration into a (111) 6T-SRAM cell. In this embodiment, the pFET
Weff is adjusted by active fin height, which as described above can
be easily adjusted for different applications by changing the depth
of the trench opening provided in FIG. 3.
[0062] In one or more other embodiments of the invention, the pFET
Weff can be adjusted by changing the physical height of the fin
relative to nFET fins in the (111) 6T-SRAM. FIG. 14 provides a
sectional view of the structure of FIG. 5 subsequent to deposition
and patterning a hardmask layer 202 to form fins 210, 220 for the
pFET and nFET regions. Using the patterned hardmask layer 202, a
RIE etch process can be used to directional etch the silicon 112
(and the silicon germanium layer, where indicated) to form the
fins.
[0063] FIG. 15 provides a sectional view of the structure of FIG.
14 subsequent to oxide deposition and fin reveal after etching the
oxide layer 126. The hardmask layer 202 is also removed during the
etching process.
[0064] FIG. 16 provides a sectional view of the structure of FIG.
16 subsequent to wet or dry etching to selectively remove the
silicon germanium layer 118. For example, the structure 200 can be
exposed to gaseous hydrochloric acid for a period of time effective
to remove the silicon germanium 118. By removing the silicon
germanium layer, the height of the fin 210 is less than the height
of fin 220, i.e., fin 210 has a smaller Weff than fin 220. The
etching process generally depends on temperature, pressure, time,
ratio of HCl to germane, and the like. Modification of these
parameters is well within the ordinary skill of those in the
art.
[0065] FIG. 17 provides a sectional view of the structure of FIG.
16 subsequent to completing formation of the transistors in the
pFET and nFET regions 212, 214, respectively. The transistors
further include a high k dielectric 216, metal gate 217, and
interlayer dielectric 218 using known processes. As noted above,
the pFET region 212 has a smaller Weff than the 1-fin in the nFET
region 214.
[0066] Advantageously, the 6T-SRAM cell design in accordance with
the present invention as is generally described above provides a
single fin for both nFET (PG/PD) and pFET (PU), e.g., a (111)
6T-SRAM cell design, wherein the Weff can be adjusted as can be
desired for different applications. For example, the pFET can be
provided with a smaller Weff than 1-fin and/or can be adjusted by
active fin height. Consequently, the SRAM big cell consumes (111)
design area but provides different Weff ratios than 1:1 for PU/PD
or PU/PG. The flexible SRAM Weff design provides high performance
and is without area penalty
[0067] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration but are
not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments described
herein.
* * * * *