U.S. patent application number 16/909649 was filed with the patent office on 2020-10-08 for multilayers of nickel alloys as diffusion barrier layers.
The applicant listed for this patent is TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Nazila DADVAND, Christopher Daniel MANACK, Salvatore Frank PAVONE.
Application Number | 20200321299 16/909649 |
Document ID | / |
Family ID | 1000004915465 |
Filed Date | 2020-10-08 |
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United States Patent
Application |
20200321299 |
Kind Code |
A1 |
DADVAND; Nazila ; et
al. |
October 8, 2020 |
MULTILAYERS OF NICKEL ALLOYS AS DIFFUSION BARRIER LAYERS
Abstract
A structure for a semiconductor device includes a copper (Cu)
layer and a first nickel (Ni) alloy layer with a Ni grain size
a.sub.1. The structure also includes a second Ni alloy layer with a
Ni grain size a.sub.2, wherein a.sub.1<a.sub.2. The first Ni
alloy layer is between the Cu layer and the second Ni alloy layer.
The structure further includes a tin (Sn) layer. The second Ni
alloy layer is between the first Ni alloy layer and the Sn
layer.
Inventors: |
DADVAND; Nazila;
(Richardson, TX) ; MANACK; Christopher Daniel;
(Flower Mound, TX) ; PAVONE; Salvatore Frank;
(Murphy, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TEXAS INSTRUMENTS INCORPORATED |
Dallas |
TX |
US |
|
|
Family ID: |
1000004915465 |
Appl. No.: |
16/909649 |
Filed: |
June 23, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
16038598 |
Jul 18, 2018 |
10692830 |
|
|
16909649 |
|
|
|
|
62568429 |
Oct 5, 2017 |
|
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62611432 |
Dec 28, 2017 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/13084
20130101; H01L 2224/1318 20130101; H01L 2224/13082 20130101; H01L
24/13 20130101; H01L 2924/01057 20130101; H01L 24/11 20130101; H01L
2224/13111 20130101; H01L 2224/13155 20130101; H01L 2924/01058
20130101; H01L 2224/13007 20130101; H01L 2224/13083 20130101; H01L
2224/1308 20130101; H01L 2224/13021 20130101; H01L 2224/13184
20130101; H01L 2224/11462 20130101; H01L 2224/13147 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00 |
Claims
1. An integrated circuit package comprising: a die; and a bump
electrically connected to the die, the bump comprising: a copper
(Cu) layer; a nickel alloy layer over the copper layer, the nickel
alloy layer including an element from a lanthanoid group; and a tin
(Sn) layer formed over the nickel alloy layer.
2. The integrated circuit package of claim 1, wherein the copper
layer is over a pad of the die.
3. The integrated circuit package of claim 1, wherein the nickel
alloy layer includes one of NiCe, NiMoW, and NiWCe.
4. The integrated circuit package of claim 1, wherein the nickel
alloy layer includes a first nickel alloy layer and a second nickel
alloy layer adjacent to each other.
5. The integrated circuit package of claim 4, wherein the first
nickel alloy layer includes a nickel grain size a.sub.1, and the
second nickel alloy layer with a nickel grain size a.sub.2, wherein
a.sub.1<a.sub.2.
6. The integrated circuit package of claim 5, wherein some of the
alloy in the first nickel alloy layer, and the second nickel alloy
layer is solubilized in nickel, while the remainder of the alloy is
at boundaries of the nickel grains in each of the nickel alloy
layers.
7. The integrated circuit package of claim 1, wherein the nickel
alloy layer includes a first nickel alloy layer, a second nickel
alloy layer, and a third nickel alloy layer adjacent to each
other.
8. The integrated circuit package of claim 7, wherein the first
nickel alloy layer includes a nickel grain size a.sub.1, the second
nickel alloy layer with a nickel grain size a.sub.2, and the third
nickel alloy layer with a Ni grain size a.sub.3, wherein
a.sub.1<a.sub.2<a.sub.3.
9. The integrated circuit package of claim 8, wherein some of the
alloy in the first nickel alloy layer, the second nickel alloy
layer, and the third nickel alloy layer is solubilized in nickel,
while the remainder of the alloy is at boundaries of the nickel
grains in each of the nickel alloy layers.
10. The integrated circuit package of claim 1, wherein the nickel
barrier layer functions as a barrier layer to contain formation of
intermetallic compounds between the copper layer and the tin
layer.
11. An integrated circuit package comprising: a die; and a bump
electrically connected to the die, the bump comprising: a copper
(Cu) layer; a nickel alloy layer over the copper layer, the nickel
alloy layer including an element from one of molybdenum,
lanthanoid, and cerium; and a tin (Sn) layer formed over the nickel
alloy layer.
12. The integrated circuit package of claim 11, wherein the copper
layer is over an aluminum pad of the die.
13. The integrated circuit package of claim 11, wherein the nickel
alloy layer includes a first nickel alloy layer and a second nickel
alloy layer adjacent to each other.
14. The integrated circuit package of claim 13, wherein the first
nickel alloy layer includes a nickel grain size a.sub.1, and the
second nickel alloy layer with a nickel grain size a.sub.2, wherein
a.sub.1<a.sub.2.
15. The integrated circuit package of claim 14, wherein some of the
alloy in the first nickel alloy layer, and the second nickel alloy
layer is solubilized in nickel, while the remainder of the alloy is
at boundaries of the nickel grains in each of the nickel alloy
layers.
16. The integrated circuit package of claim 11, wherein the nickel
alloy layer includes a first nickel alloy layer, a second nickel
alloy layer, and a third nickel alloy layer adjacent to each
other.
17. The integrated circuit package of claim 16, wherein the first
nickel alloy layer includes a nickel grain size a.sub.1, the second
nickel alloy layer with a nickel grain size a.sub.2, and the third
nickel alloy layer with a Ni grain size a.sub.3, wherein
a.sub.1<a.sub.2<a.sub.3.
18. The integrated circuit package of claim 17, wherein some of the
alloy in the first nickel alloy layer, the second nickel alloy
layer, and the third nickel alloy layer is solubilized in nickel,
while the remainder of the alloy is at boundaries of the nickel
grains in each of the nickel alloy layers.
19. The integrated circuit package of claim 11 further comprising
an under bump metallization layer between the pad and the copper
layer of the bump.
20. An integrated circuit package comprising: a die; a pad
electrically connected to the die; a metallization layer on the
pad; and a bump electrically connected to the metallization layer,
the bump comprising: a copper (Cu) layer; a nickel alloy layer over
the copper layer, the nickel alloy layer including an element from
a lanthanoid group; and a tin (Sn) layer formed over the nickel
alloy layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application is a continuation of U.S. patent
application Ser. No. 16/038,598, filed Jul. 18, 2018, which claims
priority to U.S. Provisional Application No. 62/611,432, filed Dec.
28, 2017, and U.S. Provisional Application No. 62/568,429, filed
Oct. 5, 2017, which are hereby incorporated by reference.
BACKGROUND
[0002] Wafer bumping is a requirement for board level semiconductor
packaging whereby bumps or balls made of solder are formed on the
wafers in a whole wafer prior to dicing of wafer into individual
chips. The electromigration failure mode of bumps resulting from
interdiffusion of copper (Cu) and tin (Sn) is a significant problem
in semiconductor devices.
SUMMARY
[0003] In order to solve the above problem, it is desirable to
provide a semiconductor device formed by electrodeposition of
multilayers of nickel (Ni) alloys on Cu that is able to overcome
the above disadvantage. Advantages of the present invention will
become more fully apparent from the detailed description of the
invention hereinbelow.
[0004] In one aspect of the disclosure, a structure for a
semiconductor device includes a Cu layer and a first Ni alloy layer
with a Ni grain size a.sub.1. The structure also includes a second
Ni alloy layer with a Ni grain size a.sub.2, wherein
a.sub.1<a.sub.2. The first Ni alloy layer is between the Cu
layer and the second Ni alloy layer. The structure further includes
a Sn layer or a Sn alloy such as Sn--Ag, Sn--Cu--Ag, Sn--Bi, etc.
The second Ni alloy layer is between the first Ni alloy layer and
the Sn layer.
[0005] In another aspect of the disclosure, an integrated circuit
(IC) package includes a die and a bump electrically connected to
the die. The bump includes a Cu layer and a first nickel tungsten
(NiW) layer, with a Ni grain size a.sub.1, formed over the Cu
layer. The bump also includes a second NiW layer, with a Ni grain
size a.sub.2, formed over the first NiW layer. The bump further
includes a third NiW layer, with a Ni grain size a.sub.3, formed
over the second NiW layer, wherein a.sub.1<a.sub.2<a.sub.3. A
Sn layer is formed over the third NiW layer.
[0006] In yet another aspect of the disclosure, a method of forming
an integrated circuit package includes forming a die and forming a
bump on the die such that the bump is electrically connected to the
die. The forming of the bump includes forming a first Ni alloy
layer, with a Ni grain size a.sub.1, over a Cu layer. The forming
of the bump also includes forming a second Ni alloy layer, with a
Ni grain size a.sub.2, over the first Ni alloy layer, wherein
a1<a2. The forming of the bump further includes forming a Sn
layer over the second Ni alloy layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] For a detailed description of various examples, reference
will now be made to the accompanying drawings in which:
[0008] FIG. 1 is a side view of an IC package;
[0009] FIG. 2 is a side view of a multilayered structure of a bump,
in accordance with this disclosure;
[0010] FIG. 3 is a side view of another multilayered structure of a
bump, in accordance with this disclosure;
[0011] FIG. 4 is a side view of yet another multilayered structure
of a bump, in accordance with this disclosure;
[0012] FIG. 5 is a side view of an IC package including a
multilayered bump structure, in accordance with this
disclosure;
[0013] FIG. 6 is a plot depicting an example of a reversed pulse
waveform that may be applied to form Ni alloy layers of a structure
for a semiconductor device, in accordance with this disclosure;
[0014] FIG. 7 is a flowchart illustrating an exemplary method for
forming an integrated circuit package, in accordance with this
disclosure;
[0015] FIG. 8 is a side view of yet another multilayered structure
of a bump, in accordance with this disclosure; and
[0016] FIG. 9 is a flowchart illustrating an exemplary method for
forming another integrated circuit package, in accordance with this
disclosure.
DETAILED DESCRIPTION
[0017] Certain terms have been used throughout this description and
claims to refer to particular system components. As one skilled in
the art will appreciate, different parties may refer to a component
by different names. This document does not intend to distinguish
between components that differ in name but not function. In this
disclosure and claims, the terms "including" and "comprising" are
used in an open-ended fashion, and thus should be interpreted to
mean "including, but not limited to . . . ." Also, the term
"couple" or "couples" is intended to mean either an indirect or
direct wired or wireless connection. Thus, if a first device
couples to a second device, that connection may be through a direct
connection or through an indirect connection via other devices and
connections. The recitation "based on" is intended to mean "based
at least in part on." Therefore, if X is based on Y, X may be a
function of Y and any number of other factors.
[0018] The increasing demand for miniaturization of semiconductor
packages (or IC packages) necessitates the increased current
density (amount of current per surface area) per bump. FIG. 1
displays a schematic diagram of an IC package with the bumps.
Therefore, the electromigration failure mode of bumps is critical
to determine the bump current carrying capability. Electromigration
is the transport of material as a result of gradual movement of the
ions in a conductor due to the momentum transfer between conducting
electrons and diffusing metal atoms. Electromigration degrades the
reliability of chips resulting in eventual loss of connections or
failure of a circuit. The electromigration effect becomes more
important with the reduction in the structure size in electronics
such as ICs. Electromigration failure in Cu pillar bumps and also
in solder bumps is attributed to the depletion of intermetallic
compounds at the interface of Cu and Sn.
[0019] Both the growth of intermetallic compounds (IMCs) between Cu
and Sn and void formation affect the solder joint reliability,
which can degrade the mechanical and electrical properties of the
joints. The mechanism of void formation in the Cu/Sn system is
basically caused by unbalanced diffusion rates of Cu and Sn in
which the diffusion rate of copper is higher than that of tin in
the Cu.sub.3Sn phase (the Kirkendall effect). The Kirkendall effect
is the motion of the interface between two metals that occurs as a
result of the difference in diffusion rates of the metal atoms. The
Kirkendall effect has important practical consequences. One of
these is the prevention or suppression of voids formed at the
boundary interface in various kinds of alloy-to-metal bonding.
These are referred to as Kirkendall voids.
[0020] Voiding and micro-cracks elimination and/or reduction at the
Cu--Sn interface can be achieved through insertion of multilayered
(or multilayers of) NiW with controlled grain size. The Cu--Sn
intermetallic layer is dominated by formation of Cu.sub.6Sn.sub.5
(.eta.) phase and a limited amount of Cu.sub.3Sn (.epsilon.) is
formed as a non-continuous layer at the Cu surface. In general, the
.eta.-phase shows extensive scalloping with a pattern similar to
the .epsilon.-islands. The Kirkendall voids are usually present in
the Cu.sub.3Sn-phase mainly in the adjacent of the Cu--Cu.sub.3Sn
interface and on the interface itself and the Cu.sub.3Sn layer
grows at the expense of Cu.sub.6Sn.sub.5 as long as there is a
sufficient source of Cu. Therefore, insertion of an intermediate
diffusion barrier layer at the Cu--Sn interface can decrease and/or
eliminate the inter-diffusion of Cu and Sn. When Ni alone has been
used as a diffusion barrier layer, formation of brittle
intermetallic compounds of Ni.sub.3Sn.sub.4 at the Sn and Ni
interface occurs which imposes reliability issues. The presence of
dissolved Cu into the Ni.sub.3Sn.sub.4 slows down the intermetallic
growth. However, the amount of the Cu needs to be small enough to
form (Cu,Ni)3Sn4. Presence of too much Cu results in formation of a
Cu/Ni-intermetallic with the Cu.sub.6Sn.sub.5-stoichiometry
resulting in extensive scalloping.
[0021] Pulsed Electrodeposition of multiple NiW layers with
Controlled Grain Structure as a Diffusion Barrier Layer is the
solution to these problems. Interfacing of NiW at the Cu and Sn
interface through reversed pulse electrodeposition in which the Ni
grain size of the electrodeposited NiW may be precisely controlled
by using a particular plating chemistry together with a reversed
pulse waveform is disclosed. Using this reversed pulse plating,
anodic and cathodic pulses or waveforms are mixed where cathodic
pulses are followed by anodic pulses.
[0022] Application of multiple layers of NiW through
electrodeposition in which the first layer 301 (see FIG. 4) has a
grain size of a.sub.1, a second layer 402 has a grain size of
a.sub.2, and, if employed, a third layer 403 has a grain size of
a.sub.3, where a.sub.1<a.sub.2<a.sub.3. Some amount of the
codeposited W is solubilized in crystal structure of Ni grain and
the rest is segregated at the grain boundary of Ni. The content (%
by weight) of the codeposited W (i.e., with respect to the entire
NiW layer) is inversely related to the size of the grains.
Therefore, through precise controlling of codeposited W, it is
possible to control the grain size of Ni precisely. The amount of
codeposited tungsten (W) depends on the type of the applied
reversed pulse waveform; meaning that the cathodic and anodic
current densities as well as their pulse duration influence the
amount of codeposited tungsten. The content of codeposited tungsten
influences the size of nickel (Ni) grains. Therefore, by precise
controlling of the anodic and cathodic current densities and their
pulse duration, it is possible to precisely control the grain size
of nickel (Ni). The segregation of W at the grain boundary of Ni
blocks the diffusion of the Cu through the grain boundary path.
Also, Ni within the higher layer (as oriented in FIG. 4) having
larger grain size would have a tendency to diffuse towards the
layer with smaller grain size. Therefore, the Ni in the layer 403
will have tendency to diffuse towards layer 402 and the Ni in layer
402 would have a tendency to diffuse towards layer 401. This is
expected to slow down or eliminate the Ni diffusion from layer 403
to the Sn layer due to its tendency for diffusion towards its under
layer. On the other hand, it is expected that the segregated W at
the Ni grain boundary would slow down or eliminate the formation of
a brittle Ni.sub.3Sn.sub.4 intermetallic compound.
[0023] Insertion of multilayered NiW at the Cu--Sn interface solves
the above problems. A multilayered deposition process is performed
in which the NiW layers are deposited with gradually increasing Ni
grain size starting from the Cu layer. This results in, inter alia,
segregation of W at grain boundaries of Ni, thereby improving
electromigration performance.
[0024] Reversed pulse electrodeposition slows down or eliminates
the formation of a brittle Ni.sub.3Sn.sub.4 intermetallic layer
that would otherwise be formed at the interface of Sn and Ni.
[0025] The segregation of W in the Ni grain boundary slows down or
eliminates the diffusion of Cu through grain boundary paths
resulting in a more efficient diffusion barrier compared to Ni
alone.
[0026] The deposition of multilayered NiW with precise control of
grain size allows enforcement of the direction of Ni diffusion to
be towards the underlayer NiW layer having smaller grain size
(i.e., in a direction toward the Cu layer). This results in slowing
down or elimination of Ni diffusion towards the Sn layer, hence
reducing the thickness of any possible-formed Ni.sub.3Sn.sub.4
intermetallic compound which is brittle in nature. On the other
hand, the solid solubility of Ni in Cu would provide good adhesion
at the first NiW layer 401 and the Cu layer 410 interface (FIG.
4).
[0027] Reversed pulse electrodeposition allows for adjustment of
the Ni grain size hence enforcing the Ni diffusion more towards the
underlayer NiW layer as compared to toward the Sn layer.
[0028] Reversed pulse electrodeposition allows precise control of
the grain growth of Ni and the precise amount of segregated W.
Reversed pulse electrodeposition also allows for electrodeposition
of multiple layers of NiW with gradually increasing grain size of
nickel during the plating resulting in enforcement of Ni diffusion
towards its underlayer of NiW (e.g., towards the lower Ni alloy
layers in FIGS. 2 and 3, or the lower NiW layers in FIG. 4) that
has smaller Ni grain size.
[0029] FIGS. 2-4 show, inter alia, a particular grain size
arrangement within a multilayered structure of a bump.
[0030] With reference to FIG. 2, in one aspect of the disclosure, a
structure 200 for a semiconductor device includes a Cu layer 210
and a first Ni alloy layer 201 with a Ni grain size a.sub.1. The
structure 200 also includes a second Ni alloy layer 202 with a Ni
grain size a.sub.2, wherein a.sub.1<a.sub.2. The first Ni alloy
layer 201 is between the Cu layer 210 and the second Ni alloy layer
202. The structure 200 further includes a Sn layer 220. Sn layer
220 may optionally be comprised of a Sn alloy such as Sn--Ag,
Sn--Cu--Ag, Sn--Bi, etc. The second Ni alloy layer 202 is between
the first Ni alloy layer 201 and the Sn layer 220.
[0031] In an example, the first Ni alloy layer 201 and the second
Ni alloy layer 202 each comprises at least one element selected
from the group consisting of tungsten (W), molybdenum (Mo), an
element from a lanthanoid group, and combinations thereof.
[0032] In an example, a % by weight (x.sub.1) of the at least one
element within the first Ni alloy layer 201 is present, a % by
weight (x.sub.2) of the at least one element within the second Ni
alloy layer 202 is present, and wherein x.sub.1>x.sub.2.
[0033] In an example, the first Ni alloy layer 201 may be formed
over the Cu layer 210, and the Sn layer 220 may be formed over the
second Ni alloy layer 202.
[0034] In an example, some of the at least one element in the first
Ni alloy layer 201 and some of the at least one element in the
second Ni alloy layer 202 are solubilized in the Ni grains, while a
remainder of the at least one element in the first Ni alloy layer
201 and a remainder of the at least one element in the second Ni
alloy layer 202 are segregated at boundaries of the Ni grains.
[0035] In an example, the first Ni alloy layer 201 comprises
NiW.
[0036] In an example, the second Ni alloy layer 202 comprises
NiW.
[0037] In an example, the first Ni alloy layer 201 comprises NiCe,
NiLa, NiMo, NiMoW, or NiWCe.
[0038] In an example, the second Ni alloy layer 202 comprises NiCe,
NiLa, NiMo, NiMoW, or NiWCe.
[0039] With reference to FIG. 3, in another aspect of the
disclosure, a structure 300 for a semiconductor device includes a
Cu layer 310 and a first Ni alloy layer 301 with a Ni grain size
a.sub.1. The structure 300 also includes a second Ni alloy layer
302 with a Ni grain size a.sub.2, wherein a.sub.1<a.sub.2. The
first Ni alloy layer 301 is between the Cu layer 310 and the second
Ni alloy layer 302. The structure 300 further includes a third Ni
alloy layer 303 with a Ni grain size a.sub.3, formed over the
second Ni alloy layer 302, and a Sn layer 320 is formed over the
third Ni alloy layer 303, wherein
a.sub.1<a.sub.2<a.sub.3.
[0040] In an example, the first Ni alloy layer 301, the second Ni
alloy layer 302, and the third Ni alloy layer 303 each comprises at
least one element selected from the group consisting of tungsten
(W), molybdenum (Mo), an element from a lanthanoid group, and
combinations thereof. A % by weight (x.sub.1) of the at least one
element within the first Ni alloy layer 301 is present, a % by
weight (x.sub.2) of the at least one element within the second Ni
alloy layer 302 is present, a % by weight (x.sub.3) of the at least
one element within the third Ni alloy layer 303 is present, and
wherein x.sub.1>x.sub.2>x.sub.3.
[0041] With reference to FIG. 4, in another aspect of the
disclosure, a structure 400 for a semiconductor device includes a
Cu layer 410 and a first nickel tungsten (NiW) layer 401, with a Ni
grain size a.sub.1, formed over the Cu layer 410. The structure 400
also includes a second NiW layer 402, with a Ni grain size a.sub.2,
formed over the first NiW layer 401. The structure 400 further
includes a third NiW layer 403, with a Ni grain size a.sub.3,
formed over the second NiW layer 402, wherein
a.sub.1<a.sub.2<a.sub.3. A Sn layer 420 is formed over the
third NiW layer 403.
[0042] With reference to FIG. 5, in another aspect of the
disclosure, an IC package/die includes a multilayered bump (also
shown in FIG. 4). With specific reference back to FIG. 4, the
multilayered bump 400 includes a Cu layer 410 and a first nickel
tungsten (NiW) layer 401, with a Ni grain size a.sub.1, formed over
the Cu layer 410. The bump 400 also includes a second NiW layer
402, with a Ni grain size a.sub.2, formed over the first NiW layer
401. The bump 400 further includes a third NiW layer 403, with a Ni
grain size a.sub.3, formed over the second NiW layer 402, wherein
a.sub.1<a.sub.2<a.sub.3. A Sn layer 420 is formed over the
third NiW layer 403.
[0043] In an example, a % by weight (x.sub.1) of the W within the
first NiW layer 401 is present, a % by weight (x.sub.2) of the W
within the second NiW layer 402 is present, and a % by weight
(x.sub.3) of the W within the third NiW layer 403 is present, and
wherein x.sub.1>x.sub.2>x.sub.3.
[0044] In an example, the first NiW layer 401 and/or the second NiW
layer 402 comprise an element from a lanthanoid group.
[0045] In an example, some W in the first NiW layer 401, second NiW
layer 402, and third NiW layer 403 is solubilized in the Ni grains,
while the remainder of the W in the first NiW layer 401, second NiW
layer 402, and third NiW layer 403 is segregated at boundaries of
the Ni grains.
[0046] With reference to FIG. 7, In yet another aspect of the
disclosure, a method 700 of forming an integrated circuit package
includes forming a die (block 702) and forming a bump on the die
such that the bump is electrically connected to the die (block
704). The forming of the bump includes forming a first Ni alloy
layer, with a Ni grain size a.sub.1, over a Cu layer. The forming
of the bump also includes forming a second Ni alloy layer, with a
Ni grain size a.sub.2, over the first Ni alloy layer, wherein
a1<a2. The forming of the bump further includes forming a Sn
layer over the second Ni alloy layer.
[0047] In an example of the method, the first Ni alloy layer and
the second Ni alloy layer each comprises at least one element
selected from the group consisting of tungsten (W), molybdenum
(Mo), an element from a lanthanoid group, and combinations
thereof.
[0048] In an example of the method, a % by weight (x.sub.1) of the
at least one element within the first Ni alloy layer is present, a
% by weight (x.sub.2) of the at least one element within the second
Ni alloy layer is present, and wherein x.sub.1>x.sub.2.
[0049] In an example of the method, the forming of the first Ni
alloy layer and the second Ni alloy layer are performed via a
reversed pulse electrodeposition process.
[0050] In an optional process step (and with reference to FIGS. 8
and 9), once the multiple Ni alloy layers are formed, and before
the Sn layer is formed thereon, the structure may be heated to a
temperature between about 100-200.degree. C. for a period of about
4-5 hours. This optional process step would melt or fuse the
multiple Ni alloy layers together, thereby forming a single Ni
alloy layer. This single Ni alloy layer, as a whole, would
effectively have substantially similar properties (e.g., the
location and distribution of the Ni grain sizes and W content % by
weight) as those of the multiple Ni alloy layers. The resultant
structure is shown in FIG. 8.
[0051] With reference to FIG. 8, in another aspect of the
disclosure, a structure 800 for a semiconductor device includes a
Cu layer 810 and a Ni alloy layer 801 with Ni grain sizes a.sub.1
and a.sub.2, wherein a.sub.1<a.sub.2. The structure 800 further
includes a Sn layer 820. Sn layer 820 may optionally be comprised
of a Sn alloy such as Sn--Ag, Sn--Cu--Ag, Sn--Bi, etc. The Ni alloy
layer 801 is between the Cu layer 810 and the Sn layer 820.
[0052] In an example, the Ni grains of size a.sub.1 within the Ni
alloy layer is substantially closer to the Cu layer than the Sn
layer, and the Ni grains of size a.sub.2 within the Ni alloy layer
is substantially closer to the Sn layer than the Cu layer.
[0053] In an example, the Ni grain size a.sub.1 is between 1 nm and
100 nm in diameter, and the Ni grain size a.sub.2 is between 2 nm
and 100 nm in diameter.
[0054] In an example, the Ni alloy layer comprises at least one
element selected from the group consisting of tungsten (W),
molybdenum (Mo), an element from a lanthanoid group, and
combinations thereof.
[0055] In an example, a % by weight (x.sub.1) of the at least one
element within the Ni alloy layer is present, a % by weight
(x.sub.2) of the at least one element within the Ni alloy layer is
present, and wherein x.sub.1>x.sub.2.
[0056] In an example, the at least one element at x.sub.1 within
the Ni alloy layer is substantially closer to the Sn layer than the
Cu layer, and the at least one element at x.sub.2 within the Ni
alloy layer is substantially closer to the Cu layer than the Sn
layer.
[0057] In an example, some of the at least one element at x.sub.1
within the Ni alloy layer and some of the at least one element at
x.sub.2 within the Ni alloy layer are solubilized in the Ni grains,
while a remainder of the at least one element at x.sub.1 within the
Ni alloy layer and a remainder of the at least one element at
x.sub.2 within the Ni alloy layer are segregated at boundaries of
the Ni grains.
[0058] In an example, the Ni alloy layer comprises NiW.
[0059] In an example, the Ni alloy layer comprises NiCe, NiLa,
NiMo, NiMoW, or NiWCe.
[0060] With reference to FIG. 9, In yet another aspect of the
disclosure, a method 900 of forming an integrated circuit package
includes forming a die (block 902) and forming a bump on the die
such that the bump is electrically connected to the die (block
904). The forming of the bump includes forming a copper (Cu) layer.
The forming of the bump also includes forming a nickel (Ni) alloy
layer with Ni grain sizes a.sub.1 and a.sub.2, wherein
a.sub.1<a.sub.2. The forming of the bump further includes
forming a tin (Sn) layer, wherein the Ni alloy layer is between the
Cu layer and the Sn layer.
[0061] In an example of the method, the Ni grains of size a.sub.1
within the Ni alloy layer is substantially closer to the Cu layer
than the Sn layer, and the Ni grains of size a.sub.2 within the Ni
alloy layer is substantially closer to the Sn layer than the Cu
layer.
[0062] In an example of the method, the Ni alloy layer comprises at
least one element selected from the group consisting of tungsten
(W), molybdenum (Mo), an element from a lanthanoid group, and
combinations thereof.
[0063] In an example of the method, a % by weight (x.sub.1) of the
at least one element within the Ni alloy layer is present, a % by
weight (x.sub.2) of the at least one element within the Ni alloy
layer is present, and wherein x.sub.1>x.sub.2.
[0064] In an example of the method, the at least one element at
x.sub.1 within the Ni alloy layer is substantially closer to the Sn
layer than the Cu layer, and the at least one element at x.sub.2
within the Ni alloy layer is substantially closer to the Cu layer
than the Sn layer.
[0065] In an example of the method, the forming of the Ni alloy
layer comprises heating and melting together of multiple pre-heated
Ni alloy layers, prior to the forming of the Sn layer.
[0066] Reversed Pulse Plating
[0067] Examples below describe reverse pulse electrodeposition
processes including, inter alia, current density and pulse duration
characteristics. In pulse reverse plating (PRP), the potential
voltage and/or current is alternated between cathodic and anodic
pulses. Cathodic and anodic pulses are characterized by their
amplitude (peak voltage and/or peak current density) and pulse
duration. Each pulse may consist of an OFF time (T.sub.OFF) during
which the applied current is zero. FIG. 6 is a plot 600 depicting
an example of a reversed pulse waveform that may be applied to form
Ni alloy layers between Cu and Sn layers in any of the aspects of
the disclosure. The combination of the Cu and Sn layers and the
intermediary Ni alloy layers form a structure for a semiconductor
device. As it can be seen in FIG. 6, each cathodic pulse consists
of an ON-time pulse duration (T.sub.ON,cathodic) during which
negative potential and/or negative current is applied, and an
OFF-time (T.sub.OFF,cathodic) during which zero current is applied.
Each anodic pulse consists of an ON-time pulse duration
(T.sub.ON,anodic) during which positive potential and/or positive
current is applied, and an OFF-time (T.sub.OFF,anodic) during which
zero current is applied.
[0068] The deposited film composition (e.g., the content (% by
weight) of co-deposited W in electrodeposition of NiW alloys) may
be controlled in an atomic order by regulating the pulse amplitude
and width, which fosters the initiation of grain nuclei and greatly
increases the number of grains per unit area resulting in
finer-grained deposit with better properties as compared to direct
current (DC) plated coatings.
[0069] High current density areas in the bath (i.e., plating
solution) become more depleted of ions than low current density
areas. During T.sub.OFF, ions migrate to the depleted areas in the
bath. Therefore, during the T.sub.ON, more evenly distributed ions
would be available for electrodeposition.
[0070] Table 1 and Table 2 below show an example of the waveform
than can be used for depositing of first and second layers of NiW,
respectively. The average current density (I.sub.Average) is
calculated using Equation 1.
I.sub.Average=(I.sub.Cathodic,ON.times.T.sub.Cathodic,ON-I.sub.anodic,ON-
.times.T.sub.Anodic,ON)/(T.sub.Cathodic,ON+T.sub.Cathodic,OFF+T.sub.Anodic-
,ON+T.sub.Anodic,OFF) (Equation 1)
TABLE-US-00001 TABLE 1 Pulse waveform characteristics for
depositing of the first layer of NiW. Pulse characterization Symbol
Value Cathodic pulse amplitude (current density) I.sub.Cathodic, ON
0.5 A/cm.sup.2 Cathodic pulse duration during ON time
T.sub.Cathodic, ON 20 ms Cathodic OFF time t.sub.Cathodic, OFF 0
Anodic pulse amplitude (current density) I.sub.Anodic, ON 0.3
A/cm.sup.2 Anodic pulse duration during ON time T.sub.Anodic, ON 13
ms Anodic OFF time T.sub.Anodic, OFF 0 Average current density
I.sub.Average 0.185 A/cm.sup.2
TABLE-US-00002 TABLE 2 Pulse waveform characteristics for
depositing of the second layer of NiW. Pulse characterization
Symbol Value Cathodic pulse amplitude (current density)
I.sub.Cathodic, ON 0.5 A/cm.sup.2 Cathodic pulse duration during ON
time T.sub.Cathodic, ON 20 ms Cathodic OFF time t.sub.Cathodic, OFF
0 Anodic pulse amplitude (current density) I.sub.Anodic, ON 0.4
A/cm.sup.2 Anodic pulse duration during ON time T.sub.Anodic, ON 15
ms Anodic OFF time T.sub.Anodic, OFF 0 Average current density
I.sub.Average 0.114 A/cm.sup.2
[0071] Table 3 and Table 4 below show another example of the
waveform than can be used for depositing of first and second layers
of NiW, respectively. The average current density (I.sub.Average)
is calculated using Equation 1.
TABLE-US-00003 TABLE 3 Pulse waveform characteristics for
depositing of the first layer of NiW. Pulse characterization Symbol
Value Cathodic pulse amplitude (current density) I.sub.Cathodic, ON
0.6 A/cm.sup.2 Cathodic pulse duration during ON time
T.sub.Cathodic, ON 20 ms Cathodic OFF time t.sub.Cathodic, OFF 1
Anodic pulse amplitude (current density) I.sub.Anodic, ON 0.4
A/cm.sup.2 Anodic pulse duration during ON time T.sub.Anodic, ON 13
ms Anodic OFF time T.sub.Anodic, OFF 0.2 Average current density
I.sub.Average 0.199 A/cm.sup.2
TABLE-US-00004 TABLE 4 Pulse waveform characteristics for
depositing of the second layer of NiW. Pulse characterization
Symbol Value Cathodic pulse amplitude (current density)
I.sub.Cathodic, ON 0.6 A/cm.sup.2 Cathodic pulse duration during ON
time T.sub.Cathodic, ON 20 ms Cathodic OFF time t.sub.Cathodic, OFF
1 Anodic pulse amplitude (current density) I.sub.Anodic, ON 0.5
A/cm.sup.2 Anodic pulse duration during ON time T.sub.Anodic, ON 13
ms Anodic OFF time T.sub.Anodic, OFF 0.5 Average current density
I.sub.Average 0.159 A/cm.sup.2
[0072] Advantages of aspects of the disclosure are, for example,
better corrosion resistance, better diffusion barrier, precise
control of grain size of deposit, better control of the amount of
the segregation of alloying element (e.g., W), reasonable cost,
and/or easy scale-up from lab scale to production.
[0073] Although examples are described above with reference to W as
the alloying element within the NiW layers, other alloying
elements/compositions such as Ce, La, Mo, MoW, or WCe may
alternatively be employed in any of the examples above. Such
alternatives are considered to be within the spirit and scope of
the disclosure, and may therefore utilize the advantages of the
configurations and examples described above.
[0074] Also, although examples are described above with reference
to structures with two or three Ni alloy layers, structures with
more than three Ni alloy layers between the Cu and Sn layers may
alternatively be employed in any of the examples above. Such
alternatives are considered to be within the spirit and scope of
the disclosure, and may therefore utilize the advantages of the
configurations and examples described above.
[0075] The method steps in any of the embodiments described herein
are not restricted to being performed in any particular order.
Also, structures mentioned in any of the method embodiments may
utilize structures mentioned in any of the device embodiments. Such
structures may be described in detail with respect to the device
embodiments only but are applicable to any of the method
embodiments.
[0076] Features in any of the embodiments described in this
disclosure may be employed in combination with features in other
embodiments described herein, such combinations are considered to
be within the spirit and scope of the present invention.
[0077] The above discussion is meant to be illustrative of the
principles and various example implementations according to this
disclosure. Numerous variations and modifications will become
apparent to those skilled in the art once the above disclosure is
fully appreciated. It is intended that the following claims be
interpreted to embrace all such variations and modifications.
* * * * *