U.S. patent application number 16/371390 was filed with the patent office on 2019-07-25 for activation of memory core circuits in an integrated circuit.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz.
Application Number | 20190228811 16/371390 |
Document ID | / |
Family ID | 64999824 |
Filed Date | 2019-07-25 |
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United States Patent
Application |
20190228811 |
Kind Code |
A1 |
Kalla; Thomas ; et
al. |
July 25, 2019 |
ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
Abstract
In an approach to activating at least one memory core circuit of
a plurality of memory core circuits in an integrated circuit, one
or more computer processors activate a clock signal of a currently
selected memory core circuit. The one or more computer processors
activate the clock signal of a previously selected memory core
circuit to allow the previously selected memory core circuit to be
set to a deselected operating mode. The one or more computer
processors forward an output bit generated by a memory core circuit
selected from a plurality of memory core circuits to a multiplexed
bit line.
Inventors: |
Kalla; Thomas; (Boeblingen,
DE) ; Noack; Jens; (Eglfing, DE) ; Pille;
Juergen; (Stuttgart, DE) ; Salz; Philipp;
(Altdorf, DE) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
64999824 |
Appl. No.: |
16/371390 |
Filed: |
April 1, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15831436 |
Dec 5, 2017 |
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16371390 |
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15647410 |
Jul 12, 2017 |
10210923 |
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15831436 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 11/4093 20130101;
G11C 7/1006 20130101; G11C 8/12 20130101; G11C 11/4076 20130101;
G11C 29/83 20130101; G11C 7/225 20130101; G11C 11/4096 20130101;
G11C 7/1045 20130101; G11C 7/222 20130101; G11C 11/4072 20130101;
G11C 11/408 20130101; G11C 11/406 20130101 |
International
Class: |
G11C 11/4072 20060101
G11C011/4072; G11C 7/10 20060101 G11C007/10; G11C 7/22 20060101
G11C007/22; G11C 11/4093 20060101 G11C011/4093; G11C 11/4076
20060101 G11C011/4076; G11C 11/406 20060101 G11C011/406; G11C
11/4096 20060101 G11C011/4096; G11C 11/408 20060101
G11C011/408 |
Claims
1. A method for activating at least one memory core circuit of a
plurality of memory core circuits in an integrated circuit, the
method comprising: storing, by one or more computer processors, in
a storage element, information regarding whether a specific memory
core circuit was previously selected; activating, by the one or
more computer processors, a clock signal of a currently selected
memory core circuit; activating, by the one or more computer
processors, the clock signal of a previously selected memory core
circuit to allow the previously selected memory core circuit to be
set to a deselected operating mode; combining, by the one or more
computer processors, an output bit generated by the currently
selected memory core circuit with an output bit generated by the
previously selected memory core circuit; forwarding, by the one or
more computer processors, the combined output bit to a multiplexed
bit line; and maintaining, by the one or more computer processors,
an activated state of the clock signal of the specific memory core
circuit based on the information stored in the storage element
indicating that the specific memory core was previously activated.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates generally to the field of data
processing systems, and in particular, to integrated circuits
comprising memory core circuits.
[0002] An integrated circuit is a set of electronic circuits on one
small flat piece of semiconductor material which can be made of
materials like silicon. Integrating large numbers of tiny
transistors into a small chip results in circuits that are orders
of magnitude smaller, cheaper, and faster than those constructed on
discrete electronic components. The reliability of integrated
circuits and building block approach to circuit designs cement
integrated circuits as the standard in place of designs using
discrete transistors. Integrated circuits are used in virtually all
electronic equipment and are now inextricable parts of the
structure of modern societies.
SUMMARY
[0003] Embodiments of the present invention disclose an apparatus,
a method, and a computer program product for activating at least
one memory core circuit of a plurality of memory core circuits in
an integrated circuit. The one or more computer processors activate
a clock signal of a currently selected memory core circuit. The one
or more computer processors activate the clock signal of a
previously selected memory core circuit to allow the previously
selected memory core circuit to be set to a deselected operating
mode. The one or more computer processors forward an output bit
generated by a memory core circuit selected from a plurality of
memory core circuits to a multiplexed bit line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 depicts a data flow of an integrated circuit
comprising two memory core circuits and a logic circuitry for
activating at least one of the memory core circuits according to an
embodiment of the invention.
[0005] FIG. 2 depicts a state machine for activating at least one
of the memory core circuits according to an embodiment of the
invention.
[0006] FIG. 3 depicts a state machine for activating at least one
of the memory core circuits according to an embodiment of the
invention.
[0007] FIG. 4 depicts an exemplary embodiment of a data processing
system comprising at least one integrated circuit for executing a
method according to the invention.
DETAILED DESCRIPTION
[0008] Present day integrated circuits utilize synchronized dynamic
random access memory. Synchronized dynamic random access memory
(SDRAM) devices are utilized in various computing devices and are
accessed by various types of processors. An SDRAM controller
generates signals for controlling read and write operations in
response to commands and addresses from a master, for example a
master processor. When a memory cell of an SDRAM is accessed, a row
(or a word line) on which the memory cell is placed activates. One
function of the SDRAM controller is to determine whether a row to
be accessed is presently activated. If the row is not activated,
the SDRAM controller activates the row prior to a read or write
access involving the row. The other function of the SDRAM
controller is to inactivate a previously activated row when the
SDRAM controller grants access to a new row.
[0009] The SDRAM performs a precharge operation following
read/write operations in order to maintain the status of stored
data. When the precharge operation is performed, a formerly
activated row inactivates and columns (or bit lines) set to a
precharge voltage (e.g., VCC/2). This precharge operation typically
requires several clock cycles to complete, such as two or three
clock cycles. When rows in the same bank of the SDRAM are
continuously accessed, the precharge operation is performed even
though it is not required.
[0010] Static random access memory (SRAM) is a type of volatile
digital memory that retains data written to it as long as power is
applied to the SRAM. One type of SRAM commonly used in high
performance computational circuits is referred to as a "ripple
domino" SRAM.
[0011] At present, the cells are arranged into groups of cells of
typically in the order of 16 to 64 cells per group in domino SRAM
designs. Each cell in a group connects to a local bit line pair and
the local bit line pair for each group of cells couples to a global
bit line pair. Rather than using a sense amplifier to detect a
differential voltage when reading a cell, the local bit lines are
discharged by the cell in a read operation in a ripple domino read
SRAM scheme. The state of the cell may then be determined when the
domino read SRAM scheme detects a charge. The dynamic data is
usually captured in a dynamic to static conversion circuit such as
a set-reset-latch. Before such a read operation the set-reset-latch
has to be reset and the bit lines have to be in a precharge
state.
[0012] As used herein, memory core circuits are parts of memory
array structures, particularly two-dimensional array structures,
more particularly monolithic array circuits comprising caches,
status register, and the like. A memory core may comprise a part of
an address space and thus part of SRAM cells, e.g., memory cores
interconnected via local and global bit lines.
[0013] Memory core circuits in integrated circuits may comprise a
plurality of memory banks with independent global bit lines and
global bit line latches. For example, memory core circuits may use
exclusive NAND gates (XNANDs) as set/reset latches. Address space,
such as decoded most significant bits (MSBs), may be used to select
the requested active memory core circuit. Data from the addressed
bit line may be selectively propagated to the array data out. A
significant part of the power consumption of a read operation of
the memory core circuits is required to reset/restore global bit
lines and the global bit line latches.
[0014] Advantageously, the present invention avoids slowing down
the data path and distributing global, timing critical signals.
Further, the present invention saves power to reset/restore all bit
lines during a read operation. As a result, the present invention
lowers the load on clock signals involved in memory core circuit
selection while fulfilling timing requirements. Additionally, the
present invention addresses power consumption and wire routability
tradeoffs.
[0015] The present invention details a state machine associated
with a history function which is evaluated to control bit line
capture latches. The state machine keeps track of the usage of the
memory core circuits. Depending on the evaluation of the history
function, a subset of the capture latches (e.g. XNANDs) may be
precharged or reset. The state machine does not use any additional
signals, such as clock signals, for control. Unlike a multiplexer,
the state machine avoids data bus slow down. Further, the state
machine reduces the wiring on the integrated circuit. Compared to a
solution using a discrete or distributed multiplexer at the output
to connect the desired memory core circuit to the output, the
present invention avoids the distribution of timing critical select
signals and additional logic in the data path.
[0016] Compared to solutions involving simple OR-logic connecting
the global bit line latch outputs as the data outputs while
deactivating the clocking and resetting/fencing the capture latch
of the memory core circuit, the present invention reduces power
consumption by avoiding using the OR logic in order to ensure the
proper function of the OR (or AND) gate the unaddressed memory
cores to propagate a logical zero (or logical one) state. In the
current state of the art, all memory core/bank global bit lines are
always restored to the precharge level which consumes additional
power to speed up the critical path though. The present invention
avoids the aforementioned situation.
[0017] The present invention evaluates a state machine associated
with a schematic featuring a history function to control the local
or global bit line capture latch reset and/or the local or global
bit line restore. The integrated circuit proposed by the present
invention comprises additional latches to store the global bit line
address of the last active read cycle. The integrated circuit only
resets the memory core circuit read in the current cycle and the
memory core circuit read in the last cycle. The integrated circuit
does not clock memory core circuits that do not need to be clocked
which allows the memory core circuits that do not need to be locked
to remain on the reset level. The integrated circuit may foresee
additional logic to reset all global bit line latches at the power
on phase or during an exception state removal, such as an array
initialization by a built-in self-test component, at least once.
The integrated circuit does not control using any additional
signals, such as clock signals. The integrated circuit may be used
for static memory arrays as well as for dynamic memory arrays.
[0018] FIG. 1 depicts a data flow of an integrated circuit 10
comprising two memory core circuits 12, 14 and a logic circuitry 40
for activating at least one of the memory core circuits 12, 14
according to an embodiment of the invention.
[0019] Integrated circuit 10 comprises memory core circuit 12 and
memory core circuit 14, with outputs 24 and 26 which output at
least one output bit each. Memory core circuit 12 and memory core
circuit 14 are in a deselected operating mode, wherein the at least
one output bit on outputs 24 and 26 are held on an inactive level,
respectively. Integrated circuit 10 further comprises a logic
circuitry 40 that forwards the output bit generated by memory core
circuit 12 and memory core circuit 14 selected from memory core
circuit 12 and memory core circuit 14 to multiplexed bit line 42.
Logic circuitry 40 comprises a clock gating circuit being
configured for activating clock signals 54 and 56 of one or a
selected memory core circuit 12 and memory core circuit 14 and for
activating clock signals 54 and 56 of a previously selected memory
core circuit 12 and memory core circuit 14, via controlling a
gating of clock 44 and clock 46, in order to allow the previously
selected memory core circuit 12 and memory core circuit 14 to be
set to the deselected operating mode if memory core circuit 12 and
memory core circuit 14 are currently selected for reading and
memory core circuit 12 and memory core circuit 14 were previously
selected.
[0020] The logic circuitry 40 may reside on different components
and may comprise a storage element 22 configured for storing
information regarding whether or not a specific memory core circuit
12 and memory core circuit 14 were previously selected. Further, a
clock gating circuit may keep clock signal 54 and clock signal 56
of memory core circuit 12 and memory core circuit 14 activated if
the information stored in storage element 22 indicates that memory
core circuit 12 and memory core circuit 14 activated previously. A
clock gating circuit may drive clock gates 32 and clock gate 34,
which may be implemented as a logic gate, such as an AND gate
driving the clock signal 54 and clock signal 56 and/or implementing
a precharge clock and/or XNAND/set/reset latch clock. The polarity
of the driving signal depends on the type of clock gate 32 and
clock gate 34.
[0021] The inactive level of the output bit in the embodiment shown
corresponds to a logical value of zero ("logical zero"). Logic
levels, such as logical zero and logical one, corresponding to the
finite number of states that a digital signal can inhabit.
Therefore, logic circuitry 40 comprises OR gate 28 for combining
the output bits of memory core circuits 12 and memory core circuit
14 to a signal on the multiplexed bit line 42 for propagating a
logical zero if inactive output bits exist. Thus, OR gate 28 may
switch multiplexed bit line 42.
[0022] In an alternative embodiment, if the inactive level also
corresponds to a logical zero, the logic circuitry 40 may comprise
a NOR gate for propagating a logical value of one in the case of
inactive output bits.
[0023] In a further alternative embodiment, if the inactive level
corresponds to a logical value of one ("logical one"), the logic
circuitry 40 may comprise an AND gate for combining the output bits
of the plurality of memory core circuit 12 and memory core circuit
14 to a signal on multiplexed bit line 42 for propagating a logical
one in the case of the output bits being inactive.
[0024] In yet another alternative embodiment, if the inactive level
also corresponds to a logical one, the logic circuitry 40 may
comprise a NAND gate for propagating a logical zero in the case of
inactive output bits.
[0025] At least one of memory core circuit 12 and memory core
circuit 14 may comprise a memory bank and logic circuitry 40 may
select a memory bank based on at least one address bit 48.
[0026] The logic circuitry may be configured to precharge or reset
output 24 and output 26 of the plurality of memory core circuit 12
and memory core circuit 14 upon a power-on phase or an exception
state removal or an initialization of one of memory core circuit 12
and memory core circuit 14. Further, the memory core circuit 12 and
memory core circuit 14 may precharge or reset output line 24 and
output line 26 when performing a built-in self-test. In the
embodiment shown in FIG. 1, force clock enable (FCE) signal 68
executes the built-in self-test.
[0027] The storage element 22 may be a latch. First latch 20
delivers the input for storage element 22 which receives most
significant bit (MSB) 48 of a memory core cell address and an input
and a first address latch signal L1 74 to an AND gate 39 and a
second address latch signal L2 66 to storage element 22 as an
output.
[0028] In an embodiment of the invention, integrated circuit 10
further comprises programmable local clock buffers (PLCB) 16 and
PLCB 18 for propagating clock signal 44 and clock signal 46,
enabled by enable (ENA) signal 62 and ENA signal 64 and force clock
enable (FCE) signal 58 and FCE signal 60.
[0029] Integrated circuit 10 further comprises OR gate 36 and OR
gate 38 that deliver additional inputs for clock gate 32 and clock
gate 34. Force clock enable L1 signal 68 provide OR gate 36 and OR
gate 38. Storage element 22 outputs signal 70 to NAND gate 39 and
to OR gate 38.
[0030] Integrated circuit 10 depicted in FIG. 1 implements a method
for activating at least one memory core circuit 12 and memory core
circuit 14 in integrated circuit 10. In the present invention,
clock signal 44 of a currently selected configuration of memory
core circuit 12 activates. Clock signal 46 of the previously
selected memory core circuit 14 activates in order to allow a
previously selected configuration of memory core circuit 14 to set
to a deselected operating mode. Finally, logic circuitry 40
forwards the output bit generated by the memory core circuit 12 and
memory core circuit 14 to the multiplexed bit line 42.
[0031] Storage element 22 stores information about whether or not
memory core circuit 12 and/or memory core circuit 12 were
previously selected. Clock signal 54 and clock signal 56 of memory
core circuit 14 remains activated if the information stored in the
storage element 22 indicates that memory core circuit 14 and memory
core circuit 12 were previously activated. For this purpose, logic
circuitry 40 performs the function of determining the state of one
or more memory core circuits.
[0032] Addresses of memory core cells selected for a read process
input to first address latch 20 via MSB 48. Output 66 and output 74
of address latch 20 control the signal flow through second address
latch 22 as the storage element, NAND gate 39, and OR gate 36 and
OR gate 38 in order to enable a clock gating process of AND gate 32
and AND gate 34 for activating one of memory core circuit 12 and
memory core circuit 14. Via the signal 68, a force clock enable may
disable all related clock gates, such as clock gate 32 and clock
gate 34, so that memory core circuit 12 and memory core circuit 14
clock independent of the content of latch 20 and latch 22.
[0033] FCE signal 68 and FCE signal 60 may switch from logical zero
to logical one for one or more cycles during a power-on phase or a
reset phase so that the PLCB 16 and PCLB 18 may generate a clock
pulse as clock signal 44 and clock signal 46 which transfers to
clock signal 54 and clock signal 56 as FCE signal 68 disables clock
gating via clock gate 32 and clock gate 24.
[0034] Memory core circuit 12 and memory core circuit 14 are reset
by precharge clock 54 and precharge clock 56 so that data output 24
and data output 26 is a value of zero.
[0035] After this phase, enable (ENA) signal 62 ENA signal 64 may
switch from zero to one in a read operation. The most significant
bit (MSB) 48 is logical zero indicating that the read is performed
on memory core 12. Other signals such as decoded least significant
bit (LSB)/address latches are not shown in FIG. 1 for
simplification but may be present in any embodiment of the present
invention. As indicated by MSB 48, a read operation executes in the
address space of the memory core circuit 12. If a logical one was
read from the memory core 12 the output signal 24 remains a logical
one until the memory core 12 is reset. The logical one propagates
to data out (DOUT) output 42.
[0036] In a next cycle, ENA signal 62 may remain high and the MSB
48 may switch to one so that memory core circuit 14 performs a read
operation.
[0037] MSB 48 of logical one is stored in the latch 20 while the
latch 22 stores MSB 48 of logical zero from the preceding cycle.
Memory core circuit 12 and memory core circuit 14 then clock and
reset. Assuming that logical zero is read the memory core output 26
stays at logical zero and the memory core 12 is again reset to zero
driving a zero to memory core output 24. The DOUT 42 also switches
to logical zero.
[0038] In a next cycle, if ENA signal 62 stays high, then another
read operation executes. MSB 48 may remain at logical one so that
both latch 20 and latch 22 store a logical one. In this cycle only
memory core 14 is clocked as precharge clock 54 for memory core
circuit 12 is gated by the logical one driven from NAND gate 39 and
OR gate 36.
[0039] The following table 1 show the possible input combinations
and switching of memory core clock 54 and memory core clock 56.
Both memory core circuit 12 and memory core circuit 14 are clocked
in the case of a transition or reset associated with MSB 48.
Typically, MSB 48 of subsequent read operations does not change
every cycle. In the case that MSB 48 of subsequent read operation
does not change every cycle, only memory core circuit 12 or memory
core circuit 14 is clocked. This an exemplary embodiment and
embodiments of the present inventions may be extended to any number
of memory cores. For example, the present invention may be extended
to four memory cores by including two MSB 48 to logic circuitry
40.
TABLE-US-00001 TABLE 1 Possible input combinations and switching of
the memory core clocks 54, 56 MSB last FCE ENA MSB latch cycle
latch Precharge Precharge 58, 60 62, 64 20 22 clock 54 56 1 X X X
Clocked Clocked 0 1 0 0 Clocked Gated 0 1 1 0 Clocked Clocked 0 1 0
1 Clocked Clocked 0 1 1 1 Gated Clocked
[0040] FIG. 2 depicts a state machine 100 for activating at least
one memory core circuit according to an embodiment of the
invention. A read address of address latches on a global bit line
(GBL) selected in a cycle N of state S100, is stored when a
Read_Enable signal equals to logical one in state S106 as
previously selected in a state S102. When the Read_Enable signal
equal logical one, GBL addresses restore in state S110 when in a
state S104 for the currently selected cycle N as well as the
previously selected cycle N-X. The state S102 of the additional
latches are not updated as long as the Read_Enable signal equal
logical zero in state S108.
[0041] FIG. 3 depicts a state machine 110 for activating at least
one of the memory core circuits according to a further embodiment
of the invention. The state machine 110 shown in FIG. 3 resembles
the state machine 100 shown in FIG. 2 with the exception that
optional transition S114 for a Power-On_Reset which delivers a
force clock enable (FCE) leads to a restore of global bit lines
S112.
[0042] FIG. 4 depicts a block diagram of components of server
computer 108 within distributed data processing environment 100 of
FIG. 1, in accordance with an embodiment of the present invention.
It should be appreciated that FIG. 4 provides only an illustration
of one implementation and does not imply any limitations with
regard to the environments in which different embodiments can be
implemented. Many modifications to the depicted environment can be
made.
[0043] Server computer 108 can include processor(s) 404, cache 414,
memory 406, persistent storage 408, communications unit 410,
input/output (I/O) interface(s) 412 and communications fabric 402.
Communications fabric 402 provides communications between cache
414, memory 406, persistent storage 408, communications unit 410,
and input/output (I/O) interface(s) 412. Communications fabric 402
can be implemented with any architecture designed for passing data
and/or control information between processors (such as
microprocessors, communications and network processors, etc.),
system memory, peripheral devices, and any other hardware
components within a system. For example, communications fabric 402
can be implemented with one or more buses.
[0044] Memory 406 and persistent storage 408 are computer readable
storage media. In this embodiment, memory 406 includes random
access memory (RAM). In general, memory 406 can include any
suitable volatile or non-volatile computer readable storage media.
Cache 414 is a fast memory that enhances the performance of
processor(s) 404 by holding recently accessed data, and data near
recently accessed data, from memory 406.
[0045] Program instructions and data used to practice embodiments
of the present invention, e.g., program module 110 and database
112, are stored in persistent storage 408 for execution and/or
access by one or more of the respective processor(s) 404 of server
computer 108 via cache 414. In this embodiment, persistent storage
408 includes a magnetic hard disk drive. Alternatively, or in
addition to a magnetic hard disk drive, persistent storage 408 can
include a solid-state hard drive, a semiconductor storage device, a
read-only memory (ROM), an erasable programmable read-only memory
(EPROM), a flash memory, or any other computer readable storage
media that is capable of storing program instructions or digital
information.
[0046] The media used by persistent storage 408 may also be
removable. For example, a removable hard drive may be used for
persistent storage 408. Other examples include optical and magnetic
disks, thumb drives, and smart cards that are inserted into a drive
for transfer onto another computer readable storage medium that is
also part of persistent storage 508.
[0047] Communications unit 410, in these examples, provides for
communications with other data processing systems or devices,
including resources of computing device 104. In these examples,
communications unit 410 includes one or more network interface
cards. Communications unit 410 may provide communications through
the use of either or both physical and wireless communications
links. Program module 110, database 112, and other programs and
data used for implementation of the present invention, may be
downloaded to persistent storage 408 of server computer 108 through
communications unit 410.
[0048] I/O interface(s) 412 allows for input and output of data
with other devices that may be connected to server computer 108.
For example, I/O interface(s) 412 may provide a connection to
external device(s) 416 such as a keyboard, a keypad, a touch
screen, a microphone, a digital camera, and/or some other suitable
input device. External device(s) 416 can also include portable
computer readable storage media such as, for example, thumb drives,
portable optical or magnetic disks, and memory cards. Software and
data used to practice embodiments of the present invention, e.g.,
program module 110 and database 112 on server computer 108, can be
stored on such portable computer readable storage media and can be
loaded onto persistent storage 408 via I/O interface(s) 412. I/O
interface(s) 412 also connect to a display 418.
[0049] Display 418 provides a mechanism to display data to a user
and may be, for example, a computer monitor. Display 518 can also
function as a touchscreen, such as a display of a tablet
computer.
[0050] The programs described herein are identified based upon the
application for which they are implemented in a specific embodiment
of the invention. However, it should be appreciated that any
particular program nomenclature herein is used merely for
convenience, and thus the invention should not be limited to use
solely in any specific application identified and/or implied by
such nomenclature.
* * * * *