Salz; Philipp

Patent Applications and Registrations

Patent applications and USPTO patent grants for Salz; Philipp.The latest application filed is for "build synthesized soft arrays".

Company Profile

5.9.10

Salz; Philipp - Boeblingen DE
Salz; Philipp - Altdorf DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Build synthesized soft arrays Grant 10,586,006 - Frisch , et al.	2020-03-10
Activation of memory core circuits in an integrated circuit Grant 10,388,357 - Kalla , et al. A	2019-08-20
Build Synthesized Soft Arrays App 20190251221 - Frisch; Albert ; et al.	2019-08-15
Activation Of Memory Core Circuits In An Integrated Circuit App 20190228811 - Kalla; Thomas ; et al.	2019-07-25
Build synthesized soft arrays Grant 10,318,688 - Frisch , et al.	2019-06-11
Activation of memory core circuits in an integrated circuit Grant 10,210,923 - Kalla , et al. Feb	2019-02-19
Activation of memory core circuits in an integrated circuit Grant 10,204,674 - Kalla , et al. Feb	2019-02-12
Activation Of Memory Core Circuits In An Integrated Circuit App 20190019548 - Kalla; Thomas ; et al.	2019-01-17
Activation Of Memory Core Circuits In An Integrated Circuit App 20190019549 - Kalla; Thomas ; et al.	2019-01-17
Activation Of Memory Core Circuits In An Integrated Circuit App 20190019547 - Kalla; Thomas ; et al.	2019-01-17
Build Synthesized Soft Arrays App 20180068043 - Frisch; Albert ; et al.	2018-03-08
Enhanced power savings for memory arrays Grant 8,659,963 - Dengler , et al. February 25, 2	2014-02-25
Enhanced Power Savings for Memory Arrays App 20130176795 - Dengler; Osama ; et al.	2013-07-11
Method for circuit design Grant 8,001,501 - Dorsch , et al. August 16, 2	2011-08-16
Computer readable medium, system and associated method for designing integrated circuits with loop insertions Grant 7,996,808 - Arp , et al. August 9, 2	2011-08-09
Circuit Design Processes App 20090288046 - Dorsch; Rainer ; et al.	2009-11-19
Computer Readable Medium, System and Associated Method For Designing Integrated Circuits With Loop Insertions App 20090031274 - Arp; Andreas ; et al.	2009-01-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.