U.S. patent application number 15/857296 was filed with the patent office on 2019-07-04 for memory array with individually trimmable sense amplifiers.
The applicant listed for this patent is SPIN TRANSFER TECHNOLOGIES, INC.. Invention is credited to Neal BERGER, Mourad EL BARAJI, Susmita KARMAKAR, Benjamin LOUIE.
Application Number | 20190206467 15/857296 |
Document ID | / |
Family ID | 67058431 |
Filed Date | 2019-07-04 |
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United States Patent
Application |
20190206467 |
Kind Code |
A1 |
KARMAKAR; Susmita ; et
al. |
July 4, 2019 |
MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS
Abstract
A device includes an array of memory cells, input/output lines
coupled to the memory cells, and sense amplifiers coupled to the
input/output lines. Each sense amplifier is associated with a
respective input/output line. The device also includes trim
circuits. Each trim circuit is associated with and coupled to a
respective sense amplifier. Each sense amplifier receives a
respective reference voltage that allows the sense amplifier to
sense a bit value of an addressed memory cell. Each trim circuit is
operable for compensating for variations in the reference voltage
used by the respective sense amplifier.
Inventors: |
KARMAKAR; Susmita; (Fremont,
CA) ; BERGER; Neal; (Cupertino, CA) ; EL
BARAJI; Mourad; (Fremont, CA) ; LOUIE; Benjamin;
(Fremont, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SPIN TRANSFER TECHNOLOGIES, INC. |
Fremont |
CA |
US |
|
|
Family ID: |
67058431 |
Appl. No.: |
15/857296 |
Filed: |
December 28, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 29/028 20130101;
G11C 11/1655 20130101; G11C 7/08 20130101; G11C 29/026 20130101;
G11C 2207/002 20130101; G11C 7/062 20130101; G11C 11/1693 20130101;
G11C 11/1673 20130101 |
International
Class: |
G11C 11/16 20060101
G11C011/16; G11C 7/08 20060101 G11C007/08 |
Claims
1. A device, comprising: an array of memory cells that are
individually addressable; a plurality of input/output lines coupled
to the memory cells; a plurality of sense amplifiers coupled to the
input/output lines, wherein each sense amplifier of the plurality
of sense amplifiers is associated with and coupled to a respective
input/output line of the plurality of input/output lines; and a
plurality of trim circuits, wherein each trim circuit of the
plurality of trim circuits is associated with and coupled to a
respective sense amplifier of the plurality of sense amplifiers,
and wherein said each trim circuit is further coupled to receive a
respective reference voltage that allows said each sense amplifier
to sense a bit value of an addressed memory cell of the array of
memory cells, wherein further each trim circuit of the plurality of
trim circuits is operable for compensating for variations in the
respective reference voltage, and wherein said each trim circuit
comprises a plurality of transistors, wherein the plurality of
transistors comprises transistors having sizes that differ from
each other by a factor of two.
2. The device of claim 1, wherein each transistor of the a
plurality of transistors is coupled to a ground and wherein said
each trim circuit is selectively coupled to a line coupled to the
respective sense amplifier.
3. The device of claim 2, further comprising a selection circuit
coupled to the plurality of transistors and operable for
selectively coupling one or more of the transistors to the line and
for selectively decoupling one or more of the transistors from the
line.
4. (canceled)
5. The device of claim 2, wherein the line comprises a reference
bit line coupled to the respective sense amplifier through a bit
line bias transistor.
6. The device of claim 2, wherein the line comprises: a bit line
bias line; a bit line bias transistor coupled to the bit line bias
line; and a reference bit line coupled to the bit line bias
transistor and to the respective sense amplifier.
7. (canceled)
8. The device of claim 1, wherein the memory cells comprise
magnetoresistive random access memory (MRAM) cells, wherein the
MRAM cells comprise magnetic tunnel junctions (MTJs).
9. A device, comprising: an array of magnetoresistive random access
memory (MRAM) cells, wherein the MRAM cells comprise magnetic
tunnel junctions (MTJs); a plurality of input/output lines coupled
to the MRAM cells; a plurality of sense amplifiers coupled to the
input/output lines, wherein each sense amplifier of the plurality
of sense amplifiers is associated with and coupled to a respective
input/output line of the plurality of input/output lines to receive
a voltage from the respective input/output line, the voltage having
a first level if a bit value of an addressed memory cell of the
MRAM cells has a first binary value and having a second level if
the bit value of the addressed memory cell has a second binary
value, said each sense amplifier further coupled to receive a
respective reference voltage operable for allowing the sense
amplifier to sense the bit value of the addressed memory cell; and
a plurality of trim circuits coupled to the sense amplifiers,
wherein the plurality of trim circuits are operable to individually
correct variations in reference voltages respectively supplied to
the sense amplifiers, wherein each trim circuit of the plurality of
trim circuits is operable to maintain a reference voltage at the
respective sense amplifier between the first level and the second
level; wherein each trim circuit of the plurality of trim circuits
is associated with a respective sense amplifier of the plurality of
sense amplifiers, and wherein said each trim circuit comprises a
plurality of transistors coupled to a ground and selectively
coupled to a line coupled to the respective sense amplifier.
10-11. (canceled)
12. The device of claim 9, further comprising a selection circuit
coupled to the plurality of transistors and operable for
selectively coupling one or more of the transistors to the line and
for selectively decoupling one or more of the transistors from the
line.
13. The device of claim 9, wherein the plurality of transistors
comprises transistors having sizes that differ from each other by a
factor of two.
14. The device of claim 9, wherein the line comprises a reference
bit line coupled to the respective sense amplifier through a bit
line bias transistor.
15. The device of claim 9, wherein the line is coupled to a bit
line bias transistor coupled to a reference bit line coupled to the
respective sense amplifier.
16. (canceled)
17. A method, comprising: for each sense amplifier of a plurality
of sense amplifiers coupled to a memory array, wherein said each
sense amplifier is associated with i) a respective input/output
line of a plurality of input/output lines and ii) a respective
reference bit line voltage of a plurality of reference bit line
voltages, and wherein said each sense amplifier is coupled to a
respective programmable trim circuit of a plurality of programmable
trim circuits: detecting a variation of an associated reference bit
line voltage that places the associated reference bit line voltage
outside a range of voltage values; determining a respective program
value to configure the respective programmable trim circuit to
compensate for the variation; and storing the respective program
value, wherein the respective program value when applied to
configure the respective programmable trim circuit causes the
associated reference bit line voltage to be within the range of
voltage values.
18. The method of claim 17, wherein the respective programmable
trim circuit comprises a plurality of transistors coupled to a
ground and selectively coupled to a line coupled to the respective
sense amplifier, wherein the method further comprises applying the
respective program value to select a number of the transistors to
be coupled to the line, wherein the line is selected from the group
consisting of: a reference bit line coupled to the respective sense
amplifier through a bit line bias transistor, and a bit line bias
line coupled to a bit line bias transistor coupled between a
reference bit line and the respective sense amplifier.
19. The method of claim 17, wherein the respective programmable
trim circuit comprises a variable resistor coupled to a supply
voltage and coupled to a line coupled to the respective sense
amplifier, wherein the method further comprises applying the
respective program value to select an amount of resistance to be
applied to the line, wherein the line is a reference bit line
coupled to the respective sense amplifier.
20. The method of claim 17, wherein the memory array comprises
magnetoresistive random access memory (MRAM) cells, wherein the
MRAM cells comprise magnetic tunnel junctions (MTJs).
Description
BACKGROUND
[0001] Magnetoresistive random access memory (MRAM) is a
non-volatile memory technology that stores data through magnetic
storage elements. The elements are two ferromagnetic plates or
electrodes that can hold a magnetic field and are separated by a
non-magnetic material, such as a non-magnetic metal or insulator.
This structure is known as a magnetic tunnel junction (MTJ). MRAM
devices are considered to be a next generation structure for a wide
range of memory applications.
[0002] FIG. 1 illustrates an example of an MRAM cell 110 including
an MTJ 120. In general, one of the plates (a reference layer or
fixed layer 130) has its magnetization pinned, meaning that this
layer has a higher coercivity than the other layer and requires a
larger magnetic field or spin-polarized current to change the
orientation of its magnetization. The second plate is typically
referred to as the free layer 140 and its magnetization direction
can be changed by a smaller magnetic field or spin-polarized
current relative to that of the reference layer 130. The two plates
can be sub-micron in lateral size, and the magnetization direction
can still be stable with respect to thermal fluctuations.
[0003] MRAM devices can store information by changing the
orientation of the magnetization of the free layer 140. In
particular, based on whether the free layer 140 is in a parallel or
anti-parallel alignment relative to the reference layer 130, either
a binary value of "1" or a binary value of "0" can be stored in the
MRAM cell 110 as represented in FIG. 1.
[0004] MRAM products based on spin transfer torque switching, or
spin transfer switching, are already making their way into larger
data storage devices. Spin transfer torque MRAM (STT-MRAM) devices,
such as the one illustrated in FIG. 1, use spin-aligned (polarized)
electrons to change the magnetization orientation of the free layer
in the magnetic tunnel junction. In general, electrons possess a
quantized number of angular momentum intrinsic to the electron
referred to as spin. An electrical current is generally
unpolarized; that is, it consists of 50% spin-up and 50% spin-down
electrons. By passing a current though a magnetic layer, electrons
are polarized with a spin orientation corresponding to the
magnetization direction of the magnetic layer (e.g., polarizer),
thereby producing a spin-polarized current. If the spin-polarized
current is passed to the magnetic region of the free layer 140 in
the MTJ device, the electrons will transfer a portion of their
spin-angular momentum to the magnetization layer to produce a
torque on the magnetization of the free layer. This spin transfer
torque can switch the magnetization of the free layer 140, which in
effect writes either a "1" or a "0" based on whether the free layer
is in the parallel or anti-parallel state relative to the reference
layer 130.
[0005] Due to the spin-polarized electron tunneling effect, the
electrical resistance of the cell changes due to the orientation of
the magnetic fields of the two layers 130 and 140. The electrical
resistance is typically referred to as tunnel magnetoresistance
(TMR), which is a magnetoresistance effect that occurs in an MTJ.
The cell's resistance will be different for the parallel and
anti-parallel states, and thus the cell's resistance can be used to
distinguish between a "1" and a "0."
[0006] Generally speaking, to read a memory cell, a current is
applied to the bit line that includes that cell (the "main bit
line") to detect the value of the cell's resistance by monitoring
the voltage across the cell. A sense amplifier is used to sense the
voltage level on the main bit line and compare it to a reference
bit line voltage. The reference bit line voltage is established at
a level that is between the main bit line voltage that corresponds
to a bit value of 1 and the main bit line voltage that corresponds
to a bit value of 0. If the main bit line voltage is greater than
the reference bit line voltage, then a "1" is stored in the cell;
and if the main bit line voltage is less than the reference bit
line voltage, then a "0" is stored in the cell.
[0007] There is a sense amplifier for each bit line. Thus, for
example, for a 32-bit read, 32 sense amplifiers are used. Ideally,
the sense amplifiers would be identical, but often there is a
mismatch between them due to variations in circuit parameters
deriving from manufacturing process, layout, position in the memory
array, and location of the ground. These mismatches can result in
erroneous reads.
[0008] This problem is illustrated by the example of FIGS. 2A and
2B. A reference bit line bias transistor 211 is connected to the
reference bit line 201, and a main bit line bias transistor 212 is
connected to the main bit line 202 of a memory cell being read. As
illustrated in FIG. 2B, during the clock period of the sense
amplifier 220, the reference bit line voltage supplied to the sense
amplifier (Vs) is less than both the voltage (V1) that corresponds
to a bit value of 1 and the voltage (V0) that corresponds to a bit
value of 0 due to circuit parameter mismatch between the main bit
line and the reference bit line. Thus, regardless of the actual bit
value (0 or 1) stored by the memory cell that is being read, the
sense amplifier 220 will sense a bit value of 1. That is, even if
the actual stored bit value is 0, the sense amplifier 220 may
erroneously sense a bit value of 1.
[0009] In an MTJ device, the difference between the main bit line
voltage corresponding to a "1" and that corresponding to a "0" (the
sensing margin) is small because the bit line resistance in series
reduces the resistance ratio of the MTJs as seen by the sense
amplifier. Also, a bias across an MTJ reduces the MTJ's resistance,
especially the resistance of the anti-parallel state, and so TMR is
reduced relative to the case of zero bias. Reduced TMR further
decreases the sensing margin, which increases the possibility of an
erroneous read. Thus, because of the relatively small sensing
margin in MTJ devices, the problem of mismatches due to variations
in circuit parameters and reference bit line voltage is
particularly acute.
SUMMARY
[0010] Embodiments according to the present invention include a
memory device that includes an array of memory cells, input/output
lines (e.g., bit lines) coupled to the memory cells, and sense
amplifiers coupled to the input/output lines. Each sense amplifier
is associated with a respective input/output line. The device also
includes trim circuits. Each trim circuit is associated with and
coupled to a respective sense amplifier. Each sense amplifier
receives a respective reference voltage that allows the sense
amplifier to sense a bit value of an addressed memory cell. Each
trim circuit is operable for independently compensating for
variations in the reference voltage used by the respective sense
amplifier.
[0011] In an embodiment, the memory cells include magnetoresistive
random access memory (MRAM) cells, and the MRAM cells include
magnetic tunnel junction (MTJ) memory cells.
[0012] In some embodiments, each trim circuit includes a number of
transistors coupled to a ground and selectively coupled to a line
that is coupled to a respective sense amplifier. In an embodiment,
the trim circuit is coupled to a reference bit line that is coupled
to the sense amplifier through a respective bit line bias
transistor. In another embodiment, the trim circuit is coupled to a
bit line bias line that is coupled to a respective bit line bias
transistor that is coupled to a respective reference bit line that
is coupled to the sense amplifier. In some of these embodiments,
each trim circuit also includes a selection circuit that is coupled
to the transistors and that is operable for selectively coupling
one or more of the transistors to the line and for selectively
decoupling one or more of the transistors from the line. In an
embodiment, the transistors in the trim circuits have sizes that
differ from each other by a factor of two.
[0013] In other embodiments, each trim circuit includes a variable
resistor that is coupled to a supply voltage and that is also
coupled to a reference bit line that is coupled to a respective
sense amplifier.
[0014] Embodiments according to the present invention also include
a method for configuring a trim circuit in a memory array. For each
sense amplifier coupled to the memory array, a variation in an
associated reference bit line voltage that places the associated
reference bit line voltage outside a range of voltage values is
detected; a respective program value to configure the respective
programmable trim circuit to compensate for the variation is
determined; and the respective program value is stored. When the
program value is applied to configure a respective trim circuit,
the associated reference bit line voltage is compensated so that it
is within the range of voltage values. For example, the program
value can be used to select (enable or disable) a number of
transistors in a trim circuit or to select an amount of resistance
in a trim circuit coupled to the sense amplifier.
[0015] In summary, embodiments according to the present invention
use a trim circuit per sense amplifier to compensate for variations
in the respective reference bit line voltage supplied to the sense
amplifier. As a result, the reference bit line voltage supplied to
each sense amplifier is maintained between the voltage associated
with a bit value of 1 and the voltage associated with a bit value
of 0. Mismatches between sense amplifiers are thereby compensated
for or precluded. Consequently, the accuracy and reliability of
read operations are increased. Specifically, erroneous reads due to
mismatches in circuit parameters and variations in the reference
bit line voltages are reduced in number if not completely
eliminated, even when the sensing margin is small as it is for MTJ
devices in MRAM arrays.
[0016] These and other objects and advantages of the various
embodiments of the present invention will be recognized by those of
ordinary skill in the art after reading the following detailed
description of the embodiments that are illustrated in the various
drawing figures.
BRIEF DESCRIPTION OF DRAWINGS
[0017] The accompanying drawings, which are incorporated in and
form a part of this specification and in which like numerals depict
like elements, illustrate embodiments of the present disclosure
and, together with the detailed description, serve to explain the
principles of the disclosure.
[0018] FIG. 1 illustrates an example of a conventional
magnetoresistive random access memory cell.
[0019] FIG. 2A illustrates an example of a conventional memory
device including a sense amplifier coupled to a reference bit line
and to a main bit line.
[0020] FIG. 2B illustrates an example of voltages versus time for
an erroneous read operation in a conventional memory device.
[0021] FIG. 3A illustrates a memory array in a memory device in
embodiments according to the present invention.
[0022] FIG. 3B illustrates an example of voltages versus time for a
read operation in embodiments according to the present
invention.
[0023] FIG. 4 illustrates an embodiment of a trim circuit according
to the present invention.
[0024] FIG. 5 illustrates a trim circuit coupled to a reference bit
line in embodiments according to the present invention.
[0025] FIG. 6 illustrates a trim circuit coupled to a bit line bias
line in embodiments according to the present invention.
[0026] FIG. 7 illustrates another embodiment of a trim circuit
according to the present invention.
[0027] FIG. 8 is a flowchart of examples of operations in a method
for configuring a trim circuit in embodiments according to the
present invention.
[0028] FIG. 9 is an example of a computing system upon which
embodiments according to the present invention can be
implemented.
DETAILED DESCRIPTION
[0029] Reference will now be made in detail to the various
embodiments of the present disclosure, examples of which are
illustrated in the accompanying drawings. While described in
conjunction with these embodiments, it will be understood that they
are not intended to limit the disclosure to these embodiments. On
the contrary, the disclosure is intended to cover alternatives,
modifications and equivalents, which may be included within the
spirit and scope of the disclosure as defined by the appended
claims. Furthermore, in the following detailed description of the
present disclosure, numerous specific details are set forth in
order to provide a thorough understanding of the present
disclosure. However, it will be understood that the present
disclosure may be practiced without these specific details. In
other instances, well-known methods, procedures, components, and
circuits have not been described in detail so as not to
unnecessarily obscure aspects of the present disclosure.
[0030] Some portions of the detailed descriptions that follow are
presented in terms of procedures, logic blocks, processing, and
other symbolic representations of operations on data bits within a
computer memory. These descriptions and representations are the
means used by those skilled in the data processing arts to most
effectively convey the substance of their work to others skilled in
the art. In the present application, a procedure, logic block,
process, or the like, is conceived to be a self-consistent sequence
of steps or instructions leading to a desired result. The steps are
those utilizing physical manipulations of physical quantities.
Usually, although not necessarily, these quantities take the form
of electrical or magnetic signals capable of being stored,
transferred, combined, compared, and otherwise manipulated in a
computing system. It has proven convenient at times, principally
for reasons of common usage, to refer to these signals as
transactions, bits, values, elements, symbols, characters, samples,
pixels, or the like.
[0031] It should be borne in mind, however, that all of these and
similar terms are to be associated with the appropriate physical
quantities and are merely convenient labels applied to these
quantities. Unless specifically stated otherwise as apparent from
the following discussions, it is appreciated that throughout the
present disclosure, discussions utilizing terms such as "reading,"
"programming," "detecting," "determining," "storing," "applying,"
or the like, refer to actions and processes (e.g., the flowchart
800 of FIG. 8) of a computing system or similar electronic
computing device or hardware processor (e.g., the system 900 of
FIG. 9). The computing system or similar electronic computing
device manipulates and transforms data represented as physical
(electronic) quantities within the computing system memories,
registers or other such information storage, transmission or
display devices.
[0032] Memory Array with Individually Trimmable Sense
Amplifiers
[0033] FIG. 3A illustrates a memory array 301 in a memory device
300 in embodiments according to the present invention. In
embodiments, the memory device 300 is a magnetoresistive random
access memory (MRAM) device. In an embodiment, the memory device
300 is a spin transfer torque (STT-MRAM) device.
[0034] The memory array 301 includes a number of memory cells or
storage elements exemplified by the memory cell 302. As just noted,
the memory cell 302 may be an MRAM cell. In embodiments, an MRAM
cell includes a magnetic tunnel junction (MTJ).
[0035] The memory device 300 includes a number of word lines
exemplified by the word lines WL(0), WL(1), . . . , WL(n), a number
of bit lines exemplified by BL(0), BL(1), . . . , BL(m), and a
number of source lines exemplified by SL(0), SL1(1), . . . , SL(m).
Not all memory cells, word lines, bit lines, and source lines are
shown in the figure. The bit lines may also be referred to herein
as input/output lines.
[0036] The memory cell 302 is at the intersection of a particular
word line, bit line, and source line. The memory cell 302 is
individually addressable using a row address, which specifies the
particular word line, and a column address, which specifies the
particular bit line. The memory device 300 includes an x-decoder
block 304 that decodes a row address signal and supplies a signal
to the corresponding word line. The memory device 300 also includes
a number of y-multiplexers (y-muxes) exemplified by the y-mux 306.
The y-muxes provide column select logic for selecting a bit line
and source line corresponding to a column address signal. A number
of memory cells are typically addressed together to form a data
word.
[0037] The memory device 300 also includes a number of sense
amplifiers 310-0, 310-1, . . . , 310-N, collectively referred to
herein as the sense amplifiers 310. Each of the sense amplifiers
310 is coupled to a respective set of the input/output lines (set
of bit lines) through a respective y-mux as shown in FIG. 3A. Each
sense amplifier can receive a voltage from a respective
input/output line (bit line), specifically an input/output line
(bit line) corresponding to the memory cell being read (the
addressed memory cell). The voltage has a first level if a bit
value of the addressed memory cell has a first binary value, and
has a second level if the bit value of the addressed memory cell
has a second binary value. Each sense amplifier also can receive a
respective reference bit line voltage that allows the sense
amplifier to sense the bit value of the addressed memory cell. Each
sense amplifier 0, 1, N outputs a respective output (I/O) value
(bit value) I/O 0, I/O 1, . . . , I/O N.
[0038] Significantly, in embodiments according to the present
invention, the memory device 300 also includes a number of circuits
320-0, 320-1, . . . , 320-N collectively referred to herein as trim
circuits 320. Each of the trim circuits 320 is associated with and
coupled to a respective one of the sense amplifier 310. That is,
there is a different trim circuit for each sense amplifier.
[0039] As described further below, each of the trim circuits 320
compensates for variations in the respective bit line reference
voltage received by the corresponding one of the sense amplifiers
310. That is, the trim circuits 320 are operable to individually
correct variations in the reference bit line voltages respectively
supplied to the sense amplifiers 310, and each trim circuit is
operable to maintain the respective reference bit line voltage
between a first voltage level (the voltage level associated with a
bit value of 1) and a second voltage level (the voltage level
associated with a bit value of 0), as shown in FIG. 3B.
[0040] FIG. 3B illustrates an example of voltages versus time for a
read operation in embodiments according to the present invention.
For example, the trim circuit 320-N compensates for variations in
the reference voltage received by the sense amplifier 310-N. As a
result, during the clock period of the sense amplifier 310-N, there
is no mismatch between the main and reference bit line voltages and
the reference bit line voltage supplied to the sense amplifier (Vs)
is between the voltage (V1) that corresponds to a bit value of 1
and the voltage (V0) that corresponds to a bit value of 0. Thus,
the sense amplifier 310-N will sense the proper bit value.
[0041] Co-pending U.S. patent application Ser. No. ______, entitled
"Multi-Port Random Access Memory," by Mourad El Baraji et al.,
Attorney Docket No. SPIN-0012-01.01US, is hereby incorporated by
reference in its entirety. That application describes a multi-port
memory device that can access two or more memory cells at the same
time. Embodiments according to the present disclosure can be
utilized with and/or in a multi-port memory device as disclosed in
the referenced application.
[0042] FIG. 4 illustrates a trim circuit 400 in embodiments
according to the present invention. In some embodiments, each of
the trim circuits 320 of FIG. 3A is implemented using the trim
circuit 400. In other embodiments, each of the trim circuits 320 is
implemented using the trim circuit 700 of FIG. 7, described further
below.
[0043] The transistor tree 404 of FIG. 4 includes a number of
transistors 401-0, 401-1, . . . , 401-k, collectively referred to
herein as the transistors 401. In an embodiment, the sizes of the
transistors differ from each other by a factor of two. Thus, for
example, the transistor 401-1 is twice the size of the transistor
401-0, the transistor 401-2 (not shown) is twice the size of the
transistor 401-1, and so on.
[0044] The transistors 401 receive a reference voltage from a
voltage bias generator 405. The transistors 401 are coupled to a
selection circuit 402. In general, as described further in
conjunction with FIGS. 5 and 6 below, the selection circuit 402 is
operable for selectively coupling and decoupling one or more of the
transistors 401 to and from a respective reference bit line.
[0045] In an embodiment, the selection circuit 402 of FIG. 4
includes a number of switches 403-0, 403-1, . . . , 403-k,
collectively referred to herein as the switches 403. The switches
403 can be implemented as transistors. Each of the transistors 401
is coupled to a respective one of the switches 403. Each of the
switches 403 is controlled by a respective program value or
configuration bit. If the configuration bit has a first binary
value, then the switch is closed (enabled), and the switch is
opened (disabled) if the configuration bit has a second binary
value. Each of the transistors 401 is also coupled to a respective
ground.
[0046] When a transistor in the transistor tree 404 is coupled to a
respective reference bit line or respective bit line bias line (see
FIGS. 5 and 6) by closing the associated one of the switches 403, a
corresponding amount of current is trimmed (drained) from that line
through the transistor to ground. As noted above, one or more of
the transistors may be coupled to the line at a time. As described
above, in an embodiment, the transistors 401 have different sizes.
Thus, the amount of the trimmed current can be finely controlled by
selecting a single one of the transistors (a single desired size)
or any combination of the transistors (any desired combination of
sizes).
[0047] In general, the program values used to configure the trim
circuit 400 (FIG. 4) are determined by measuring the reference bit
line voltage respectively supplied to each of the sense amplifiers
320 (FIG. 3A) and then determining the program values that will
cause each respective reference bit line voltage to be in the range
between the voltage for a binary value of 1 and the voltage for a
binary value of 0. Ideally, each reference bit line voltage
supplied to a sense amplifier is at about the midpoint of that
range.
[0048] The program values used to control the switches 403 (FIG. 4)
can be determined, for example, when the memory device 300 (FIG.
3A) is manufactured, and/or when the memory device is installed in
a computing system, and/or each time the memory device is powered
up. Alternatively, after installation, testing of the memory device
300 can be periodically performed and the program values can be
determined accordingly.
[0049] Because a respective trim circuit is coupled to each sense
amplifier, each trim circuit can be individually tuned. That is,
the program values can be different for each of the trim circuits
400 of FIG. 4. Thus, the reference bit line voltage for each of the
sense amplifiers 320 (FIG. 3A) can be individually trimmed, as
opposed to global trimming of all sense amplifiers.
[0050] FIG. 5 illustrates a trim circuit 400 coupled to a reference
bit line 502 in an embodiment according to the present invention.
The sense amplifier 310-N is coupled to receive a reference bit
line voltage from the reference bit line 502, which is connected to
the sense amplifier through a reference bit line bias transistor
506. A reference bit line bias line 504 is connected to the gate of
the reference bit line bias transistor 506. As described above, the
trim circuit 400 is configured to trim a selected amount of current
on the reference bit line 502 to compensate for variations in the
reference bit line, so that a trimmed reference bit line voltage is
supplied to the sense amplifier 310-N.
[0051] The sense amplifier 310-N is also coupled to receive a main
bit line voltage from the main bit line 508, which is connected to
the sense amplifier through a main bit line bias transistor 510. A
main bit line bias line 512 is connected to the gate of the main
bit line bias transistor 510. The main bit line voltage is the
voltage on the bit line of the memory cell being read (the
addressed memory cell). The sense amplifier 310-N can compare the
main bit line voltage and the trimmed reference bit line voltage to
determine the bit value of the memory cell being read.
[0052] FIG. 6 illustrates a trim circuit 400 coupled to a bit line
bias line 604 in an embodiment according to the present invention.
A reference bit line bias line 604 is connected to the gate of the
reference bit line bias transistor 606 that is coupled to the
reference bit line 602, which is coupled to the sense amplifier
310-N. As described above, the trim circuit 400 is configured to
trim a selected amount of the current on the reference bit line
bias line 604 to compensate for variations in the reference bit
line 602, so that a trimmed reference bit line voltage is supplied
to the sense amplifier 310-N. More specifically, the float on the
reference bit line bias transistor 606 is adjusted to provide a
different bias for the reference bit line 602 and trim the
reference bit line voltage supplied to the sense amplifier
310-N.
[0053] The sense amplifier 310-N is also coupled to receive a main
bit line voltage from the main bit line 608, which is connected to
the sense amplifier through a main bit line bias transistor 610. A
main bit line bias line 612 is connected to the gate of the main
bit line bias transistor 610. The main bit line voltage is the
voltage on the bit line of the memory cell being read (the
addressed memory cell). The sense amplifier 310-N can compare the
main bit line voltage and the trimmed reference bit line voltage to
determine the bit value of the memory cell being read.
[0054] FIG. 7 illustrates a trim circuit 700 in another embodiment
according to the present invention. As mentioned above, in some
embodiments, each of the trim circuits 320 of FIG. 3A is
implemented using the trim circuit 700. The trim circuit 700
includes a variable resistor 702 coupled to the reference bit line
704 and to supply voltage Vdd. The trim circuit 700 also includes a
resistor 703 coupled between the supply voltage Vdd and the main
bit line 710. The current on the reference bit line 702 can be
trimmed using the trim circuit 700, by varying the resistances of
the variable resistor 702, so that a trimmed reference bit line
voltage is supplied to the sense amplifier 310-N.
[0055] The reference bit line 704 is coupled to the trim circuit
700 and to the sense amplifier 310-N through a reference bit line
bias transistor 706. A reference bit line bias line 708 is
connected to the gate of the reference bit line bias transistor
706.
[0056] The variable resistor 702 can be implemented using a digital
potentiometer, or digitally controlled variable resistor, that is
controlled by program values or configuration bits in a manner
similar to that described above for the trim circuit 400. The
program values used to control the variable resistor 702 can be
determined, for example, when the memory device 300 (FIG. 3A) is
manufactured, and/or when the memory device is installed in a
computing system, and/or each time the memory device is powered up.
Alternatively, after installation, testing of the memory device 300
can be periodically performed and the program values can be
determined accordingly.
[0057] The sense amplifier 310-N is also coupled to receive a main
bit line voltage from the main bit line 710, which is connected to
the sense amplifier through a main bit line bias transistor 712. A
main bit line bias line 714 is connected to the gate of the main
bit line bias transistor 712. The main bit line 710 is also coupled
to the trim circuit 700. The main bit line voltage is the voltage
on the bit line of the memory cell being read (the addressed memory
cell). The sense amplifier 310-N can compare the main bit line
voltage and the trimmed reference bit line voltage to determine the
bit value of the memory cell being read.
[0058] FIG. 8 is a flowchart 800 of examples of operations in a
method for configuring a trim circuit in embodiments according to
the present invention. The operations can be performed in and by
the computing system 900 of FIG. 9. The computing system 900 can
include the memory device 300 of FIG. 3A or can be coupled to the
memory device. The operations in the flowchart 800 can be
performed, for example, by a tester system when the memory device
300 is manufactured, and/or when the memory device is installed,
and/or each time the memory device is powered up, and/or each time
the memory device is tested. The operations in the flowchart 800
can be performed for each of the sense amplifiers 310 of FIG.
3A.
[0059] In block 802 of FIG. 8, a variation of a reference bit line
voltage associated with a sense amplifier, that places the
associated reference bit line voltage outside a range of voltage
values, is detected.
[0060] In block 804, a respective program value or configuration
bit to configure a respective programmable trim circuit (e.g., the
trim circuit 400 or the trim circuit 700 of FIGS. 4 and 7,
respectively) to compensate for the variation is determined.
[0061] In block 806, the respective program value is non-volatilely
stored. The respective program value, when applied to configure the
respective programmable trim circuit, causes the associated
reference bit line voltage to be within the range of voltage
values.
[0062] For implementations using the trim circuit 400 of FIG. 4
implemented as shown in FIG. 5, the respective program value is
applied to select a number of transistors to be coupled to a
reference bit line coupled to the respective sense amplifier
through a respective bit line bias transistor. For implementations
using the trim circuit 400 of FIG. 4 implemented as shown in FIG.
6, the respective program value is applied to select a number of
transistors to be coupled to a bit line bias line coupled to a
respective bit line bias transistor coupled to a respective
reference bit line that is coupled to the respective sense
amplifier.
[0063] For implementations using the trim circuit 700 of FIG. 7,
the respective program value is applied to select an amount of
resistance to be applied to a reference bit line coupled to the
respective sense amplifier.
[0064] FIG. 9 is an example of a computing system 900 upon which
embodiments according to the present invention can be implemented.
In its most basic configuration, the system 900 includes at least
one processing unit 902 and memory 904. This most basic
configuration is illustrated in FIG. 9 by dashed line 906. The
system 900 may also have additional features and/or functionality.
For example, the system 900 may also include additional storage
(removable and/or non-removable) including, but not limited to,
magnetic or optical disks or tape. Such additional storage is
illustrated in FIG. 9 by removable storage 908 and non-removable
storage 920. The system 900 may also contain communications
connection(s) 922 that allow the device to communicate with other
devices, e.g., in a networked environment using logical connections
to one or more remote computers.
[0065] The system 900 can also include input device(s) 924 such as
keyboard, mouse, pen, voice input device, touch input device, etc.
Output device(s) 926 such as a display device, speakers, printer,
etc., are also included.
[0066] In the example of FIG. 9, the memory 904 includes
computer-readable instructions, data structures, program modules,
and the like associated with an application for executing a method
for configuring a trim circuit in embodiments according to the
present invention (e.g., the method of FIG. 8). For example, in an
embodiment, the system 900 can include a tester system that can be
connected to a memory device that includes a trim circuit (e.g.,
the memory device 300 of FIG. 3).
[0067] Thus, in embodiments according to the present invention, a
trim circuit per sense amplifier is used to compensate for
variations in the respective reference bit line voltage supplied to
the sense amplifier. As a result, the reference bit line voltage
supplied to each sense amplifier is maintained between the voltage
associated with a bit value of 1 and the voltage associated with a
bit value of 0. Mismatches between sense amplifiers are thereby
compensated for or precluded. Consequently, the accuracy and
reliability of read operations are increased. Specifically,
erroneous reads due to mismatches in circuit parameters and
variations in the reference bit line voltages are reduced in number
if not completely eliminated, even when the sensing margin is small
as it is for MTJ devices in MRAM arrays.
[0068] While the foregoing disclosure sets forth various
embodiments using specific block diagrams, flowcharts, and
examples, each block diagram component, flowchart step, operation,
and/or component described and/or illustrated herein may be
implemented, individually and/or collectively, using a wide range
of hardware, software, or firmware (or any combination thereof)
configurations. In addition, any disclosure of components contained
within other components should be considered as examples because
many other architectures can be implemented to achieve the same
functionality.
[0069] The process parameters and sequence of steps described
and/or illustrated herein are given by way of example only and can
be varied as desired. For example, while the steps illustrated
and/or described herein may be shown or discussed in a particular
order, these steps do not necessarily need to be performed in the
order illustrated or discussed. The example methods described
and/or illustrated herein may also omit one or more of the steps
described or illustrated herein or include additional steps in
addition to those disclosed.
[0070] Although the subject matter has been described in language
specific to structural features and/or methodological acts, it is
to be understood that the subject matter defined in the disclosure
is not necessarily limited to the specific features or acts
described above. Rather, the specific features and acts described
above are disclosed as example forms of implementing the
disclosure.
[0071] Embodiments described herein may be discussed in the general
context of computer-executable instructions residing on some form
of computer-readable storage medium, such as program modules,
executed by one or more computers or other devices. By way of
example, and not limitation, computer-readable storage media may
comprise non-transitory computer-readable storage media and
communication media; non-transitory computer-readable media include
all computer-readable media except for a transitory, propagating
signal. Generally, program modules include routines, programs,
objects, components, data structures, etc., that perform particular
tasks or implement particular abstract data types. The
functionality of the program modules may be combined or distributed
as desired in various embodiments.
[0072] Computer storage media includes volatile and nonvolatile,
removable and non-removable media implemented in any method or
technology for storage of information such as computer-readable
instructions, data structures, program modules or other data.
Computer storage media includes, but is not limited to, random
access memory (RAM), magnetoresistive random access memory (MRAM),
read only memory (ROM), electrically erasable programmable ROM
(EEPROM), flash memory or other memory technology, compact disk ROM
(CD-ROM), digital versatile disks (DVDs) or other optical storage,
magnetic cassettes, magnetic tape, magnetic disk storage or other
magnetic storage devices, or any other medium that can be used to
store the desired information and that can be accessed to retrieve
that information.
[0073] Communication media can embody computer-executable
instructions, data structures, and program modules, and includes
any information delivery media. By way of example, and not
limitation, communication media includes wired media such as a
wired network or direct-wired connection, and wireless media such
as acoustic, radio frequency (RF), infrared, and other wireless
media. Combinations of any of the above can also be included within
the scope of computer-readable media.
[0074] Embodiments according to the present invention are thus
described. While the present invention has been described in
particular embodiments, it should be appreciated that the present
invention should not be construed as limited by such embodiments,
but rather construed according to the following claims.
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