Karmakar; Susmita

Patent Applications and Registrations

Patent applications and USPTO patent grants for Karmakar; Susmita.The latest application filed is for "heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments".

Company Profile

14.9.12

Karmakar; Susmita - Fremont CA
KARMAKAR; Susmita - Milpitas CA
Karmakar; Susmita - Bangalore IN
Karmakar; Susmita - Malvern PA
Karmakar, Susmita - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Word line decoder memory architecture Grant 11,423,965 - Berger , et al. August 23, 2	2022-08-23
Heuristics For Selecting Subsegments For Entry In And Entry Out Operations In An Error Cache System With Coarse And Fine Grain Segments App 20220107888 - BERGER; Neal ; et al.	2022-04-07
Error Cache System With Coarse And Fine Segments For Power Optimization App 20220107900 - BERGER; Neal ; et al.	2022-04-07
Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Grant 11,119,910 - Berger , et al. September 14, 2	2021-09-14
Error cache system with coarse and fine segments for power optimization Grant 11,119,936 - Berger , et al. September 14, 2	2021-09-14
Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow Grant 11,048,633 - Karmakar , et al. June 29, 2	2021-06-29
Memory array with individually trimmable sense amplifiers Grant 10,930,332 - Karmakar , et al. February 23, 2	2021-02-23
Master slave level shift latch for word line decoder memory architecture Grant 10,803,949 - Berger , et al. October 13, 2	2020-10-13
Master Slave Level Shift Latch for Word Line Decoder Memory Architecture App 20200286561 - BERGER; Neal ; et al.	2020-09-10
Word Line Decoder Memory Architecture App 20200227102 - BERGER; Neal ; et al.	2020-07-16
Word line decoder memory architecture Grant 10,699,761 - Berger , et al.	2020-06-30
Error Cache System With Coarse And Fine Segments For Power Optimization App 20200117610 - BERGER; Neal ; et al.	2020-04-16
Heuristics For Selecting Subsegments For Entry In And Entry Out Operations In An Error Cache System With Coarse And Fine Grain S App 20200117592 - BERGER; Neal ; et al.	2020-04-16
Word Line Decoder Memory Architecture App 20200090721 - BERGER; Neal ; et al.	2020-03-19
Determining An Inactive Memory Bank During An Idle Memory Cycle To Prevent Error Cache Overflow App 20200042451 - KARMAKAR; Susmita ; et al.	2020-02-06
Memory Array With Individually Trimmable Sense Amplifiers App 20190348097 - KARMAKAR; Susmita ; et al.	2019-11-14
Memory array with individually trimmable sense amplifiers Grant 10,360,962 - Karmakar , et al.	2019-07-23
Memory Array With Individually Trimmable Sense Amplifiers App 20190206467 - KARMAKAR; Susmita ; et al.	2019-07-04
Power-on reset signal generation circuit and method App 20070216453 - Vispute; Hemant ; et al.	2007-09-20
High voltage shunt regulator for flash memory Grant 7,116,088 - Tran , et al. October 3, 2	2006-10-03
High voltage shunt regulator for flash memory App 20040245975 - Tran, Hieu Van ; et al.	2004-12-09

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