U.S. patent application number 16/220470 was filed with the patent office on 2019-06-27 for methods for thermal management in amplifiers.
The applicant listed for this patent is Skyworks Solutions, Inc.. Invention is credited to Bharatjeet Singh Gill, Michael Joseph McPartlin.
Application Number | 20190199294 16/220470 |
Document ID | / |
Family ID | 58559026 |
Filed Date | 2019-06-27 |
![](/patent/app/20190199294/US20190199294A1-20190627-D00000.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00001.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00002.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00003.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00004.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00005.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00006.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00007.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00008.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00009.png)
![](/patent/app/20190199294/US20190199294A1-20190627-D00010.png)
View All Diagrams
United States Patent
Application |
20190199294 |
Kind Code |
A1 |
McPartlin; Michael Joseph ;
et al. |
June 27, 2019 |
METHODS FOR THERMAL MANAGEMENT IN AMPLIFIERS
Abstract
Methods of managing heat generated by amplifiers are disclosed.
A metal pillar, a plurality of resistors, and a transistor array
are formed over a silicon substrate. The plurality of resistors
provide emitter-ballasting for the amplifier. A footprint defined
by a periphery of the metal pillar is adjacent to a footprint
defined by a periphery of the transistor array and overlaps a
footprint defined by a periphery of the plurality of resistors so
that heat generated during operation of the amplifier is
transferred through the silicon substrate to the metal pillar.
Inventors: |
McPartlin; Michael Joseph;
(North Andover, MA) ; Gill; Bharatjeet Singh;
(Ottawa, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Skyworks Solutions, Inc. |
Woburn |
MA |
US |
|
|
Family ID: |
58559026 |
Appl. No.: |
16/220470 |
Filed: |
December 14, 2018 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
15299760 |
Oct 21, 2016 |
10193504 |
|
|
16220470 |
|
|
|
|
62245183 |
Oct 22, 2015 |
|
|
|
62245168 |
Oct 22, 2015 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/73204
20130101; H03F 1/56 20130101; H01L 29/41708 20130101; H01L 21/4882
20130101; H01L 23/49816 20130101; H01L 2224/16235 20130101; H01L
2224/32225 20130101; H01L 2924/1305 20130101; H01L 29/7325
20130101; H03F 3/213 20130101; H04B 1/0475 20130101; H01L 23/49844
20130101; H01L 2224/13647 20130101; H01L 2924/10271 20130101; H01L
21/4853 20130101; H01L 23/3738 20130101; H01L 29/1004 20130101;
H01L 29/161 20130101; H01L 2223/6655 20130101; H01L 2224/1302
20130101; H01L 23/53214 20130101; H01L 28/40 20130101; H03F 3/195
20130101; H04B 1/48 20130101; H01L 24/05 20130101; H01L 2224/13147
20130101; H01L 2224/16227 20130101; H03F 2200/451 20130101; H04W
88/02 20130101; H01L 23/3142 20130101; H03F 2200/387 20130101; H03F
2200/447 20130101; H04B 1/44 20130101; H01L 23/5286 20130101; H01L
2224/05647 20130101; H01L 23/3157 20130101; H01L 23/3675 20130101;
H03F 3/24 20130101; H01L 23/3114 20130101; H01L 23/528 20130101;
H01L 23/66 20130101; H01L 2924/1207 20130101; H01L 25/50 20130101;
H01L 27/0658 20130101; H01L 2224/0401 20130101; H01L 2224/81447
20130101; H03F 3/211 20130101; H01L 24/11 20130101; H01L 29/732
20130101; H01L 23/367 20130101; H01L 23/5223 20130101; H01L 27/0647
20130101; H01L 28/20 20130101; H01L 29/16 20130101; H03F 3/245
20130101; H01L 23/53228 20130101; H01L 23/3736 20130101; H01L
2924/10253 20130101; H03F 1/302 20130101; H01L 21/8222 20130101;
H01L 2224/131 20130101; H01L 2224/16145 20130101; H04B 2001/0408
20130101; H01L 23/36 20130101; H01L 24/13 20130101; H01L 2224/13147
20130101; H01L 2924/00014 20130101; H01L 2224/131 20130101; H01L
2924/014 20130101; H01L 2224/81447 20130101; H01L 2924/00014
20130101; H01L 2224/1302 20130101; H01L 2924/00012 20130101; H01L
2224/73204 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2924/00 20130101 |
International
Class: |
H03F 1/30 20060101
H03F001/30; H01L 23/498 20060101 H01L023/498; H01L 21/48 20060101
H01L021/48; H04B 1/48 20060101 H04B001/48; H04B 1/04 20060101
H04B001/04; H03F 3/213 20060101 H03F003/213; H03F 1/56 20060101
H03F001/56; H01L 49/02 20060101 H01L049/02; H01L 23/66 20060101
H01L023/66; H01L 23/528 20060101 H01L023/528; H01L 23/31 20060101
H01L023/31; H01L 23/532 20060101 H01L023/532; H01L 23/522 20060101
H01L023/522; H03F 3/21 20060101 H03F003/21; H03F 3/24 20060101
H03F003/24; H01L 23/36 20060101 H01L023/36; H01L 29/161 20060101
H01L029/161; H01L 27/06 20060101 H01L027/06; H01L 23/367 20060101
H01L023/367; H01L 29/16 20060101 H01L029/16; H01L 23/373 20060101
H01L023/373; H04B 1/44 20060101 H04B001/44; H03F 3/195 20060101
H03F003/195; H01L 23/00 20060101 H01L023/00; H01L 25/00 20060101
H01L025/00; H01L 29/732 20060101 H01L029/732; H01L 29/417 20060101
H01L029/417; H01L 29/10 20060101 H01L029/10; H01L 21/8222 20060101
H01L021/8222 |
Claims
1. A method for thermal management of an amplifier, the method
comprising: forming a transistor array over a silicon substrate;
and forming a metal pillar over the silicon substrate such that a
footprint defined by a periphery of the metal pillar is adjacent to
a footprint defined by a periphery of the transistor array, heat
generated during operation of the transistor array being
transferred through the silicon substrate to the metal pillar.
2. The method of claim 1 wherein the footprint defined by the
periphery of the metal pillar further overlaps a footprint defined
by a periphery of a plurality of first resistors formed over the
silicon substrate.
3. The method of claim 2 wherein a first end of a resistor of the
plurality of first resistors is in communication with an emitter of
a transistor of the transistor array.
4. The method of claim 3 wherein the resistor of the plurality of
first resistors provides emitter-ballasting for the amplifier.
5. The method of claim 3 wherein a second end of the resistor of
the plurality of first resistors in communication with the metal
pillar.
6. The method of claim 1 wherein the metal pillar is configured to
provide a flip chip interconnection for the amplifier.
7. The method of claim 1 wherein the metal pillar is configured to
provide a ground connection.
8. The method of claim 1 further comprising forming one or more
inter-level metal layers between the silicon substrate and the
metal pillar.
9. The method of claim 8 wherein the heat is transferred through
the one or more inter-level metal layers before reaching the metal
pillar.
10. The method of claim 1 wherein the transistor array includes an
NPN bipolar transistor.
11. The method of claim 1 wherein the transistor array includes at
least a portion of a silicon germanium power amplifier.
12. A method for thermal management of a flip chip implementation
of an amplifier, the method comprising: forming a transistor array
and a plurality of first resistors over a silicon substrate, a
first end of a resistor of the plurality of first resistors in
communication with an emitter of a transistor of the transistor
array; and forming a metal pillar over the silicon substrate such
that a footprint defined by a periphery of the metal pillar is
adjacent to a footprint defined by a periphery of the transistor
array and overlaps a footprint defined by a periphery of the
plurality of first resistors, a second end of the resistor of the
plurality of first resistors in communication with the metal
pillar, heat generated during operation of the transistor of the
transistor array being transferred through the silicon substrate to
the metal pillar.
13. The method of claim 12 wherein the metal pillar is configured
to provide a flip chip interconnection for the amplifier.
14. The method of claim 12 wherein the metal pillar is configured
to provide a ground connection.
15. The method of claim 12 wherein the resistor of the plurality of
first resistors providing emitter-ballasting for the amplifier.
16. The method of claim 12 further comprising forming a second
plurality of resistors, a resistor of the second plurality of
resistors in communication with a base of the transistor.
17. The method of claim 16 wherein the resistor of the second
plurality of resistors providing base-ballasting for the
amplifier.
18. The method of claim 12 further comprising forming one or more
inter-level metal layers between the silicon substrate and the
metal pillar.
19. The method of claim 12 wherein the transistor array includes an
NPN bipolar transistor.
20. The method of claim 12 wherein the transistor array includes at
least a portion of a silicon germanium power amplifier.
Description
INCORPORATION BY REFERENCE TO ANY PRIORITY APPLICATIONS
[0001] Any and all applications for which a foreign or domestic
priority claim is identified in the Application Data Sheet as filed
with the present application are hereby incorporated by reference
under 37 CFR 1.57.
BACKGROUND
[0002] Embodiments relate to power-amplifier design, and in
particular to managing electrothermal performance in flip-chip
power-amplifier design.
SUMMARY
[0003] In an embodiment, an alternative bumping method for linear
flip-chip SiGe-power-amplifier IC design implements emitter
ballasting and achieves equivalent or lower thermal resistance to
that obtained with direct emitter bumping and base ballasting.
[0004] In another embodiment, the metal bump or pillars are placed
adjacent to the NPN transistor arrays that are used in the power
amplifier for RF power generation. By placing the metal in intimate
contact with the silicon substrate, the heat generated by the NPN
arrays flows down into the silicon substrate and then out the metal
bump/pillar. Advantageously, the metal bump/pillar also forms an
electrical ground connection in close proximity to the NPN array
and, consequently, the emitter ballast resistors can be connected
to the grounding point.
[0005] In yet another embodiment, a method to provide equivalent or
lower thermal resistance for a SiGe NPN array of a power amplifier
relative to the emitter bumping method is disclosed. In an
embodiment, the Cu pillar connects directly to the bulk silicon
substrate adjacent to the NPN transistor array. The metal area and
contact-via area is maximized to the extent of the bump pad to
provide less thermal resistance without increasing the die area.
The heat generated in each emitter stripe of the transistor array
is more efficiently transferred to the bulk silicon rather than to
the polysilicon-emitter-contact via because of the physical
differences in the top side versus the backside contact surface
area of the integrated circuit (IC) or chip. Since the bulk silicon
has relatively high thermal conductivity, the heat generated in the
NPN transistor array spreads quickly and is efficiently transferred
to a large silicon contact pad and Cu pillar.
[0006] In a further embodiment, the Cu pillar bump electrically and
thermally connects to the bulk silicon and not to the emitter
contact. A ballast resistor can be electrically connected and
physically placed between each emitter of the NPN transistor array
and the bump pad, which in an embodiment, optimizes the
electrothermal configuration or layout for a linear SiGe power
amplifier.
[0007] According to a number of embodiments, the disclosure relates
to a method to implement an emitter-ballasted amplifier in a flip
chip configuration. The method comprises forming a power amplifier
over a silicon substrate, the power amplifier including at least
one transistor, forming a metal pillar including a top portion
providing a flip chip interconnection for the power amplifier,
where the metal pillar is in thermal communication with the at
least one transistor, and forming a first resistor in electrical
communication with an emitter of the at least one transistor so as
to provide emitter-ballasting to the power amplifier.
[0008] In an embodiment, the metal pillar is in thermal
communication with the at least one transistor via a thermal path
including the silicon substrate and one or more metal layers
disposed between the metal pillar and the silicon substrate. In
another embodiment, the metal pillar is configured to provide at
least a portion of a thermal path for heat generated by the at
least one transistor. In a further embodiment, the metal pillar is
not formed over a substantial portion of the at least one
transistor. In a yet further embodiment, the first resistor is in
electrical communication with the metal pillar.
[0009] In an embodiment, the metal pillar is configured to provide
a ground connection. In another embodiment, the method further
comprises forming a second resistor in communication with a base of
the at least one transistor so as to provide base-ballasting to the
power amplifier. In a further embodiment, the method further
comprises forming inter-level metals and contacts under the metal
pillar and not over the at least one transistor. In a yet further
embodiment, the metal pillar includes copper.
[0010] In an embodiment, the metal pillar forms a solder bump of a
flip chip. In another embodiment, the at least one transistor
includes an NPN bipolar junction transistor. In a further
embodiment, the power amplifier is a SiGe power amplifier.
[0011] Certain embodiments relate to an emitter-ballasted power
amplifier comprising at least one transistor formed over a silicon
substrate, a first resistor formed over the silicon substrate and
in electrical communication with an emitter of the at least one
transistor to form at least one emitter-ballasted transistor, and a
metal pillar in thermal communication with the at least one
emitter-ballasted transistor and including a top portion that
provides a flip chip interconnection for the at least one
emitter-ballasted transistor.
[0012] In an embodiment, when looking down onto the metal pillar
and the at least one emitter-ballasted transistor from above the
substrate, a footprint defined by a periphery of the metal pillar
does not significantly overlap a footprint defined by a periphery
of the at least one emitter-ballasted transistor. In another
embodiment, the metal pillar is in thermal communication with the
at least one emitter-ballasted transistor via a thermal path
including the silicon substrate and one or more metal layers
disposed between the metal pillar and the silicon substrate. In a
further embodiment, the metal pillar is configured to provide a
ground connection. In a yet further embodiment, the
emitter-ballasted amplifier further comprises a second resistor in
communication with a base of the at least one emitter-ballasted
transistor so as to provide base-ballasting. In an embodiment, the
metal pillar forms a solder bump of a flip chip.
[0013] According to further embodiments, the disclosure relates to
a wireless mobile device comprising an antenna configured to
receive and transmit radio frequency signals, a transmit/receive
switch configured to pass an amplified radio frequency signal to
the antenna for transmission, and a multi-chip module including a
flip chip amplifier die that includes at least one
emitter-ballasted amplifier configured to amplify a radio frequency
input signal and to generate the amplified radio frequency signal,
where the at least one emitter-ballasted amplifier includes at
least one transistor formed over a silicon substrate, a first
resistor in communication with an emitter of the at least one
transistor to form at least one emitter-ballasted transistor, and a
metal pillar formed adjacent to the at least one emitter-ballasted
transistor, and an output matching network die including an output
matching network circuit configured to match an impedance of a
fundamental frequency of the amplified radio frequency signal. In
an embodiment, wherein the at least one emitter-ballasted amplifier
further includes a second resistor in communication with a base of
the at least one emitter-ballasted transistor to provide base
resistance.
[0014] According to a number of embodiments, the disclosure relates
to an amplifier die comprising an emitter-ballasted amplifier
including at least one transistor formed over a silicon substrate,
a resistor in communication with an emitter of the at least one
transistor to form at least one emitter-ballasted transistor, and a
metal pillar formed adjacent to the at least one emitter-ballasted
transistor. The amplifier die further comprises an input pad
electrically connected to a first terminal of the emitter-ballasted
amplifier, an output pad electrically connected to a second
terminal of the emitter-ballasted amplifier, and a plurality of
interconnections configured to electrically connect at least the
resistor to the metal pillar. In an embodiment, a portable
transceiver comprising the amplifier die.
[0015] Certain embodiments relate to a multi-chip module comprising
a flip chip amplifier die including at least one emitter-ballasted
amplifier configured to amplify an input signal and to generate an
amplified output signal, where the at least one emitter-ballasted
amplifier includes at least one transistor formed over a silicon
substrate, a resistor in communication with an emitter of the at
least one transistor to form at least one emitter-ballasted
transistor, and a metal pillar formed adjacent to the at least one
emitter-ballasted transistor. The multi-chip module further
comprises an output matching network die including an output
matching network circuit configured to match an impedance of a
fundamental frequency of the amplified output signal. In an
embodiment, the emitter-ballasted amplifier includes a SiGe power
amplifier.
[0016] According to a number of embodiments, the disclosure relates
to an amplifier comprising at least one transistor formed over a
silicon substrate, and a metal pillar formed over the silicon
substrate such that, as viewed from above and looking down onto the
metal pillar, the silicon substrate, and the at least one
transistor, a footprint defined by a periphery of the metal pillar
does not substantially overlap with a footprint defined by a
periphery of the at least one transistor, where the silicon
substrate, the metal pillar, and the at least one transistor are
arranged with respect to each other such that heat generated during
operation of the at least one transistor is transferred through the
silicon substrate to the metal pillar.
[0017] In an embodiment, the metal pillar is configured to provide
a flip chip interconnection for the amplifier. In another
embodiment, the metal pillar is configured to provide a thermal
path for heat generated by the at least one transistor when the
amplifier is operating. In a further embodiment, the heat is
transferred through one or more layers disposed between the silicon
substrate and the metal pillar before reaching the metal
pillar.
[0018] In an embodiment, the amplifier further comprises a first
resistor in communication with an emitter of the at least one
transistor and the metal pillar, the resistor providing
emitter-ballasting to the amplifier. In another embodiment, the
amplifier further comprises a second resistor in communication with
a base of the at least one transistor, where the second resistor
provides base-ballasting to the amplifier. In a further embodiment,
the metal pillar is further configured to provide a ground
connection. In a yet further embodiment, the amplifier further
comprises inter-level metals and contacts formed under the metal
pillar.
[0019] In an embodiment, the metal pillar includes copper. In
another embodiment, the metal pillar forms one or more solder bumps
of a flip chip. In a further embodiment, the at least one
transistor includes an NPN bipolar junction transistor. In a yet
further embodiment, the at least one transistor includes at least a
portion of a SiGe power amplifier.
[0020] Certain embodiments relate to a method for thermal
management of a flip chip implementation of an amplifier. The
method comprises forming at least one transistor over a silicon
substrate, and forming a metal pillar in relation to the at least
one transistor such that heat generated during operation of the at
least one transistor travels through the silicon substrate before
being transferred to the metal pillar.
[0021] In an embodiment, the metal pillar is formed over the
silicon substrate offset from and not over the at least one
transistor. In another embodiment, the metal pillar is configured
to provide a flip chip interconnection for the amplifier. In a
further embodiment, the metal pillar is configured to provide a
ground connection. In a yet further embodiment, the method further
comprises forming a first resistor in communication with an emitter
of the at least one transistor and the metal pillar, the resistor
providing emitter-ballasting to the amplifier. In an embodiment,
the method t further comprises forming a second resistor in
communication with a base of the at least one transistor, the
second resistor providing base-ballasting to the amplifier.
[0022] According to further embodiments, the disclosure relates to
a wireless mobile device comprising an antenna configured to
receive and transmit radio frequency signals, a transmit/receive
switch configured to pass an amplified radio frequency signal to
the antenna for transmission, and a multi-chip module including a
flip chip amplifier die. The flip chip amplifier die includes at
least one amplifier configured to amplify a radio frequency input
signal and to generate the amplified radio frequency signal, where
the at least one amplifier includes at least one transistor formed
over a silicon substrate, and a metal pillar formed with respect to
the silicon substrate and the at least one transistor such that
heat generated during operation of the at least one transistor is
transferred through the silicon substrate to the metal pillar. The
wireless mobile device further comprises an output matching network
die including an output matching network circuit configured to
match an impedance of a fundamental frequency of the amplified
radio frequency signal. In an embodiment, the at least one
amplifier further includes a first resistor and a second resistor,
where the first resistor is in communication with an emitter of the
at least one transistor to provide emitter-ballasting and the
second resistor is in communication with a base of the at least one
transistor to provide base resistance.
[0023] Certain embodiments relate to an amplifier die comprising an
amplifier including at least one transistor formed over a silicon
substrate, and a metal pillar formed in relation to the at least
one transistor such that heat generated during operation of the at
least one transistor is transferred through the silicon substrate
to the metal pillar, an input pad electrically connected to a first
terminal of the amplifier, an output pad electrically connected to
a second terminal of the amplifier, and a plurality of
interconnections configured to provide electrical communication
between the at least one transistor and the metal pillar. In an
embodiment, a portable transceiver comprises the amplifier die.
[0024] According to a number of embodiments, the disclosure relates
to a multi-chip module comprising a flip chip amplifier die
including at least one amplifier configured to amplify an input
signal and to generate an amplified output signal, where the at
least one amplifier includes at least one transistor formed over a
silicon substrate, and a metal pillar formed with respect to the
silicon substrate and the at least one transistor such that heat
generated during operation of the at least one transistor is
transferred through the silicon substrate before being transferred
to the metal pillar. The multi-chip module further comprises an
output matching network die including an output matching network
circuit configured to match an impedance of a fundamental frequency
of the amplified output signal. In an embodiment, the at least one
amplifier includes an emitter-ballasted SiGe power amplifier.
[0025] According to a number of embodiments, the disclosure relates
to a method to implement an emitter-ballasted amplifier in a flip
chip configuration. The method comprises forming at least one
transistor over a silicon substrate, forming a metal pillar over
the silicon substrate, and forming a first resistor having a first
end in electrical communication with an emitter of the at least one
transistor and a second end in electrical communication with the
metal pillar, where the first resistor is configured to provide
emitter-ballasting for a radio frequency amplifier that includes
the at least one transistor, and the metal pillar is configured to
provide a ground connection for the radio frequency amplifier.
[0026] In an embodiment, the metal pillar is configured to provide
a flip chip interconnection for the radio frequency amplifier. In
another embodiment, the metal pillar is further configured to
provide a thermal path for heat generated by the at least one
transistor when the radio frequency amplifier is operating. In a
further embodiment, the silicon substrate, the metal pillar, and
the at least one transistor are arranged with respect to one
another to provide the thermal path for heat generated by the at
least one transistor.
[0027] In an embodiment, the method further comprises forming a
second resistor in electrical communication with a base of the at
least one transistor. In another embodiment, the method further
forming inter-level metals and contacts under the metal pillar,
between the metal pillar and the silicon substrate, where the
inter-level metals form a part of the thermal path. In a further
embodiment, the inter-level metals and contacts are in electrical
communication with the metal pillar and the second end of the first
resistor. In a yet further embodiment, the inter-level metals and
contacts form a grounding point for the emitter-ballasted amplifier
that provides emitter degeneration inductance for the
emitter-ballasted amplifier when the metal pillar is electrically
connected to a ground plane on an interposer.
[0028] In an embodiment, the metal pillar includes copper. In
another embodiment, the metal pillar forms at least one solder bump
of a flip chip. In a further embodiment, the at least one
transistor comprises an NPN bipolar junction transistor. In a yet
further embodiment, the emitter-ballasted amplifier comprises a
SiGe power amplifier.
[0029] Certain embodiments relate to an emitter-ballasted amplifier
comprising at least one transistor formed over a silicon substrate,
a metal pillar formed over the silicon substrate, and a first
resistor having a first end in electrical communication with an
emitter of the at least one transistor and a second end in
electrical communication with the metal pillar, where the first
resistor is configured to provide emitter-ballasting for a radio
frequency amplifier that includes the at least one transistor, and
the metal pillar is configured to provide a ground connection for
the radio frequency amplifier.
[0030] In an embodiment, the silicon substrate, the metal pillar,
and the at least one transistor are arranged with respect to one
another to provide a thermal path for heat generated by the at
least one transistor. In another embodiment, the silicon substrate,
the metal pillar, and the at least one transistor are arranged with
respect to one another to provide the thermal path for heat
generated by the at least one transistor. In a further embodiment,
the emitter-ballasted amplifier further comprises inter-level
metals and contacts under the metal pillar, between the metal
pillar and the silicon substrate, the inter-level metals forming a
part of the thermal path. In a yet further embodiment, the metal
pillar is configured to provide a flip chip interconnection for the
radio frequency amplifier. In an embodiment, the emitter-ballasted
amplifier further comprises a second resistor in electrical
communication with a base of the at least one transistor.
[0031] According to further embodiments, the disclosure relates to
a wireless mobile device comprising an antenna configured to
receive and transmit radio frequency signals, a transmit/receive
switch configured to pass an amplified radio frequency signal to
the antenna for transmission, and a multi-chip module including a
flip chip amplifier die. The a flip chip amplifier die includes at
least one emitter-ballasted amplifier configured to amplify a radio
frequency input signal and to generate the amplified radio
frequency signal, where the at least one emitter-ballasted
amplifier includes at least one transistor formed over a silicon
substrate, a metal pillar formed over the silicon substrate, and a
first resistor having a first end in electrical communication with
an emitter of the at least one transistor and a second end in
electrical communication with the metal pillar. The first resistor
is configured to provide emitter-ballasting for a radio frequency
amplifier that includes the at least one transistor. The metal
pillar is configured to provide a ground connection for the radio
frequency amplifier. The multi-chip module further comprises an
output matching network die including an output matching network
circuit configured to match an impedance of a fundamental frequency
of the amplified radio frequency signal. In an embodiment, the at
least one emitter-ballasted amplifier further includes a second
resistor in communication with a base of the at least one
transistor to provide base resistance.
[0032] Certain other embodiments relate to an amplifier die
comprising at least one transistor formed over a silicon substrate,
a metal pillar formed over the silicon substrate, and a first
resistor having a first end in electrical communication with an
emitter of the at least one transistor and a second end in
electrical communication with the metal pillar, where the first
resistor is configured to provide emitter-ballasting for a radio
frequency amplifier that includes the at least one transistor, the
metal pillar is configured to provide a ground connection for the
RF amplifier. The amplifier die further comprises an input pad
electrically connected to a first terminal of the RF amplifier, an
output pad electrically connected to a second terminal of the RF
amplifier, and a plurality of interconnections configured to
electrically connect at least the second end of the first resistor
to the metal pillar. In an embodiment, a portable transceiver
comprises the amplifier die.
[0033] According to a number of embodiments, the disclosure relates
to a multi-chip module comprising a flip chip amplifier die
including at least one emitter-ballasted amplifier configured to
amplify an input signal and to generate an amplified output signal.
The at least one emitter-ballasted amplifier includes at least one
transistor formed over a silicon substrate, a metal pillar formed
over the silicon substrate, and a first resistor having a first end
in electrical communication with an emitter of the at least one
transistor and a second end in electrical communication with the
metal pillar, where the first resistor is configured to provide
emitter-ballasting for a radio frequency amplifier that includes
the at least one transistor, and the metal pillar is configured to
provide a ground connection for the RF amplifier. The multi-chip
module further comprises an output matching network die including
an output matching network circuit configured to match an impedance
of a fundamental frequency of the amplified output signal. In an
embodiment, the RF amplifier includes a SiGe power amplifier.
[0034] Advantages of embodiments disclosed herein include:
[0035] 1. An efficient method to remove heat from a SiGe NPN power
transistor array which results in equivalent or lower thermal
resistance than emitter bumping, thereby improving power, gain, and
linearity of the SiGe power amplifier.
[0036] 2. Emitter ballasting instead of base ballasting for thermal
stability and improved linearity of a SiGe power amplifier.
[0037] 3. An efficient design of collector and base power combining
networks. When emitter bumps are used, the collector and base of
the transistor exit the array orthogonally to the emitter, which
creates unequal phase distribution between the base and collector
or equal phase with less optimum impedance transformation networks
from additional routing.
[0038] 4. A straightforward conversion from chip-on-board (COB)
and/or through-silicon-via (TSV) to flip chip (FC) package design
and vice versa due to fewer changes to matching network layout and
the overall IC floor plan.
[0039] 5. A low impedance substrate connection, which achieves
optimum linearity, output power, and efficiency from the NPN
transistor array.
[0040] 6. Superior linearity and ruggedness due to the use of
emitter ballasting, as base ballasting degrades amplifier
performance due to the reduction in collector to emitter breakdown
voltage (ruggedness), reduction in peak current (Vbe droop), and
increased base band impedance which degrades linearity (memory
effect).
[0041] 7. Prevents thermal coupling between adjacent arrays. The
emitter bump removes heat that would otherwise be transferred to
adjacent transistor arrays. Removal of the heat reduces current
mismatch conditions, limits the amount of current collapse, and
reduces thermal run away of the transistor arrays, which increases
the safe operating area, increases reliability, and increases
linearity of the amplifier.
BRIEF DESCRIPTION OF THE DRAWINGS
[0042] FIG. 1 illustrates an exemplary amplifying circuit,
according to certain embodiments.
[0043] FIG. 2 is a schematic illustrating a base-ballasted
amplifying circuit, according to certain embodiments.
[0044] FIG. 3 is a schematic illustrating an emitter-ballasted
amplifying circuit, according to certain embodiments.
[0045] FIG. 4 illustrates an exemplary flip-chip interconnection of
semiconductor devices, according to certain embodiments.
[0046] FIG. 5 illustrates a top view of an exemplary flip-chip
amplifier layout for a base-ballasted amplifier, according to
certain embodiments.
[0047] FIG. 6 illustrates a cross section of the base-ballasted
amplifier of FIG. 5, according to certain embodiments.
[0048] FIG. 7 illustrates a top view of an exemplary flip-chip
amplifier layout for an emitter-ballasted amplifier, according to
certain embodiments.
[0049] FIG. 8 illustrates a cross section of the emitter-ballasted
amplifier of FIG. 7, according to certain embodiments.
[0050] FIG. 9 is a schematic illustrating a base and
emitter-ballasted amplifying circuit, according to certain
embodiments.
[0051] FIG. 10 illustrates a top view of an exemplary flip-chip
amplifier layout for a base and emitter-ballasted amplifier,
according to certain embodiments.
[0052] FIG. 11 illustrates a cross section of the base and
emitter-ballasted amplifier of FIG. 10, according to certain
embodiments.
[0053] FIG. 12 illustrates a perspective view of an exemplary
amplifier layout showing Cu pillars beside transistors arrays,
according to certain embodiments.
[0054] FIG. 13 is an exemplary block diagram of an amplifier die,
according to certain embodiments.
[0055] FIG. 14 is an exemplary block diagram of an amplifier
module, according to certain embodiments.
[0056] FIG. 15 is an exemplary block diagram illustrating a
simplified portable transceiver including embodiments of flip-chip
power amplifier layouts, according to certain embodiments.
DETAILED DESCRIPTION
[0057] FIG. 1 is a schematic of an exemplary amplifying circuit 100
comprising an amplifier 102 that is configured to amplify an input
signal Vin to provide an amplified output signal Vout. In an
embodiment, the amplifier 102 comprises a power amplifier. In an
embodiment, an output matching network receives the amplified
output signal Vout and matches an impedance of a fundamental
frequency of the amplified output signal. In an embodiment, a front
end module comprises the amplifier 102 and the output matching
network.
[0058] In the design of bipolar power amplifier devices, ballasting
is employed to limit the amount of current in the device to
maintain thermal stability and achieve good electrical performance.
In an embodiment, ballasting resistors electrically couple to the
individual NPN cells that make up a power transistor array. Either
base or emitter ballasting can prevent thermal runaway and
catastrophic failure of the NPN array.
[0059] FIG. 2 illustrates an embodiment of a base-ballasted
amplifier 200 comprising an array of 1 to N base-ballasted
transistor pairs 202(1)-202(n). In an embodiment, each
base-ballasted transistor pair 202(n) comprises a first transistor
Q1n, a second transistor Q2n, where each transistor Q1n, Q2n has a
base, an emitter, and a collector. Each base-ballasted transistor
pair 202(n) further comprises a first base resistor Rb1n, a second
base resistor Rb2n, a first base capacitor Cb1n, and a second case
capacitor Cb2n. In an embodiment, the amplifier 200 comprises a
power amplifier. In a further embodiment, the amplifier 200
comprises a SiGe power amplifier.
[0060] For each base-ballasted transistor pair 202(n), a base
terminal of the first transistor Q1n electrically couples to a
first terminal of the first base resistor Rb1n and a first terminal
of the first base capacitor Cb1n. And a base terminal of the second
transistor Q2n electrically couples to a first terminal of the
second base resistor Rb2n and a first terminal of the second base
capacitor Cb2n.
[0061] Second terminals of the first base capacitors Cb11 through
Cb1n electrically couple to second terminals of the second base
capacitors Cb21 through Cb2n and to each other to form an amplifier
base or an input 204 to the base-ballasted amplifier 200. In an
embodiment, the input 204 comprises an RF input.
[0062] Second terminals of the first base resistors Rb11 through
Rb1n electrically couple to second terminals of the second base
resistors Rb21 through Rb2n and to each other and are in
communication with a DC base signal 206. In an embodiment, the DC
base signal 206 comprises a ground signal.
[0063] Collector terminals the first transistors Q11 through Q1n
electrically couple to collector terminals of the second
transistors Q21 through Q2n and to each other to form an amplifier
collector or an output 208 from the base-ballasting amplifier 200.
In an embodiment, the output 208 comprises an RF output.
[0064] Emitter terminals the first transistors Q11 through Q1n
electrically couple to emitter terminals of the second transistors
Q21 through Q2n and to each other to form an amplifier emitter 210
of the base-ballasting amplifier 200.
[0065] FIG. 3 illustrates an embodiment of an emitter-ballasted
amplifier 300 comprising an array of 1 to N emitter-ballasted
transistor pairs 302(1)-302(n). In an embodiment, each
emitter-ballasted transistor pair 302(n) comprises the first
transistor Q1n, the second transistor Q2n, where each transistor
Q1n, Q2n has a base, an emitter, and a collector. Each
emitter-ballasted transistor pair 302(n) further comprises a first
emitter resistor Re1n, a second emitter resistor Re2n, the first
base capacitor Cb1n, and the second case capacitor Cb2n. In an
embodiment, the amplifier 300 comprises a power amplifier. In a
further embodiment, the amplifier 300 comprises a SiGe power
amplifier.
[0066] For each emitter-ballasted transistor pair 302(n), the
emitter terminal of the first transistor Q1n electrically couples
to a first terminal of the first emitter resistor Re1n. And the
emitter terminal of the second transistor Q2n electrically couples
to a first terminal of the second emitter resistor Re2n. Second
terminals of the first emitter resistors Re11 through Re1n
electrically couple to second terminals of the second emitter
resistors Re21 through Re2n and to each other to form an amplifier
emitter 310 of the emitter-ballasted amplifier 300.
[0067] Base terminals of the first transistors Q11 through Q1n
electrically couple to base terminals of the second transistors Q21
through Q2n, to first terminals of the first base capacitors Cb11
through Cb1n, and to first terminals of the second base capacitors
Cb21 through Cb2n and are in communication with a DC base signal
306. In an embodiment, the DC base signal 306 comprises a ground
signal.
[0068] Second terminals of the first base capacitors Cb11 through
Cb1n electrically couple to second terminals of the second base
capacitors Cb21 through Cb2n and to each other to form an amplifier
base or an input 304 to the emitter-ballasted amplifier 300. In an
embodiment, the input 304 comprises an RF input.
[0069] Collector terminals the first transistors Q11 through Q1n
electrically couple to collector terminals of the second
transistors Q21 through Q2n and to each other to form an amplifier
collector or an output 308 from the emitter-ballasting amplifier
300. In an embodiment, the output 308 comprises an RF output.
[0070] For linear SiGe power amplifiers, emitter ballasting is
typically preferred over base ballasting because base ballasting
has many adverse effects on performance, such as but not limited
to, lower breakdown voltage and poorer linearity. Emitter
ballasting not only provides thermal stability but also achieves
better electrical performance than base ballasting.
[0071] Flip chip, also known as controlled collapse chip connection
or its acronym, C4, is a method for interconnecting semiconductor
devices, such as integrated circuits or IC chips and
microelectromechanical systems (MEMS), to external circuitry with
solder bumps that have been deposited onto bump pads.
[0072] FIG. 4 illustrates an exemplary flip-chip assembly 400
comprising an integrated circuit (IC) 410. In an embodiment, the IC
410 comprises an amplifier, such as, but not limited to amplifier
200, 300. In another embodiment, the IC 410 comprises a power
amplifier. In a further embodiment, the IC 410 comprises a SiGe
power amplifier.
[0073] Copper (Cu) pillars or solder bumps 402 are deposited on Cu
solder pads or bump pads 404 on the top side of the wafer
associated with the IC 410 during the final wafer-processing step.
In order to mount the IC 410 to external circuitry 406 (e.g., a
circuit board or another chip or wafer), it is flipped over so that
its top side faces down, and aligned so that its Cu solder pads 404
align with matching pads 408 on the external circuitry 406, and
then the solder is reflowed to complete the interconnect. This is
in contrast to wire bonding, in which an integrated circuit is
mounted upright, and wires are used to interconnect chip pads to
the external circuitry 406.
[0074] In power amplifier design, it is important to minimize the
thermal resistance and limit the negative effects of excess heat on
circuit performance parameters, such as but not limited to power,
gain, and linearity. In flip-chip power-amplifier design, the
amplifier emitters 210, 310 often connect directly to a copper (Cu)
pillar pad associated with a Cu pillar, which provides heat sinking
for heat dissipation.
[0075] FIG. 5 illustrates a top view of an exemplary flip-chip
amplifier layout for electrothermal management of a base-ballasted
amplifier 500. A Cu pillar 502 sits over the amplifier 500, which
comprises an array 504 of transistors Q11-Q1n, Q21-Q2n and a
plurality of base-ballasting resistors 506.
[0076] FIG. 6 illustrates a cross section 600 of the base-ballasted
amplifier 500 of FIG. 5. FIG. 6 shows base-ballasted transistors
Q1, Q2 of the array 504 formed over a bulk silicon substrate 610.
The base terminal of the transistor Q1, Q2 is in communication with
the base-ballasting resistor 506. FIG. 6 further shows the emitter
of the transistor Q1, Q2 in communication with an emitter-contact
via 602. In an embodiment, the emitter-contact via 602 comprises a
polysilicon-emitter-contact via. Inter-level metals and contacts
608, in an embodiment, comprise L3 metal, inter-level contacts
(ILC), and L2 metal, and are in communication with the emitter
contact 602 and the Cu pillar 502. The Cu pillar 502, through a Cu
solder pad, is in contact with a laminate interposer or printed
circuit board 606. The laminate interposer or printed circuit board
606 comprises the Cu solder pad, a Cu via, and a Cu heat
sink/ground plane 604.
[0077] Referring to FIGS. 5 and 6, in an embodiment, a solution for
thermal management in flip-chip power-amplifier design comprises
connecting the emitter-contact via 602 to the Cu pillar 502 using
all metal levels and contact-via levels 608 available in the
technology. The Cu pillar 502 then connects to the heat sink/ground
604 on the laminate interposer or printed circuit board 606. Heat
is removed from the emitter through relatively small area
polysilicon-emitter contact vias 602, which transition up through
the inter-level metals and contacts 608 to the Cu pillar 502 and to
the heat sink/ground plane 604. The emitter contact area is
substantially less than that achieved with silicon bumping, which
results in restricted heat flow.
[0078] For example, the Cu pillar 502, which can measure
approximately 90 .mu.m.times.180 .mu.m, is transitioned and reduced
down to the size of the polysilicon-emitter-contact via 602 which,
in an embodiment, is approximately 25 .mu.m.times.0.4 .mu.m or
less. In certain embodiments, there may be approximately 60 or more
emitter contacts 602 made to a single Cu pillar 502. The area of
the inter-level metals and contacts 608 is also constricted due to
the presence of the collector terminals and the desire to make
robust electrical contact to the collector terminals. This
reduction in metal and contact area increases thermal
resistance.
[0079] While emitter ballasting would improve electrical properties
of the amplifier 500, applying emitter ballasting may be
impractical to implement and it may lead to an excessive rise in
the thermal resistance and junction temperature due to the
discontinuity caused by the emitter-ballasting resistor in the heat
transfer path. Thus, base ballasting is used to provide thermal
stability since emitter ballasting is neither possible nor
desirable without causing significant degradation in the thermal
conductivity.
[0080] For at least these reasons, connecting the polysilicon
emitter directly to the Cu pillar 502 and heat sink 604 with base
ballasting, instead of the more electrically optimal emitter
ballasting, has traditionally been the electrothermal solution for
flip-chip power-amplifier design.
[0081] Embodiments of better electrothermal design for amplifiers
implemented in flip chip configuration are disclosed herein. In an
embodiment, the amplifiers comprise power amplifiers. In another
embodiment, the amplifiers comprise SiGe power amplifiers.
[0082] FIG. 7 illustrates a top view of an exemplary flip-chip
amplifier layout for electrothermal management of an
emitter-ballasted amplifier 700 that can be used for RF power
generation. Amplifier 700 comprises an array 704 of transistors
Q11-Q1n, Q21-Q2n and a plurality of emitter-ballasting resistors
708.
[0083] FIG. 8 illustrates a cross section of the emitter-ballasted
amplifier 700 of FIG. 7. FIG. 8 shows emitter-ballasted transistors
Q1, Q2 of the array 704 formed over a bulk silicon substrate 810.
The emitter terminal of the transistor Q1, Q2 is in communication
with the emitter-ballasting resistor 706, which introduces a
discontinuity in the heat transfer of the heat generated in the
emitter to the Cu pillar 702. FIG. 8 further shows inter-level
metals and contacts 808 in communication with the bulk silicon
substrate 810 and the Cu pillar 702. In an embodiment, the
inter-level metals and contacts 808 comprise L3 metal, inter-level
contacts (ILC), L2 metal, and L1 metal. The Cu pillar 702, through
a Cu solder pad, is in contact with the laminate interposer or
printed circuit board 806. The laminate interposer or printed
circuit board 806 comprises the Cu solder pad, a Cu via, and a Cu
heat sink/ground plane 804.
[0084] Referring to FIGS. 7 and 8, in an embodiment, a solution for
thermal management in flip-chip power-amplifier design comprises
placing the metal bumps or Cu pillars 702 adjacent to the
transistor arrays 704 and over inter-level metals and contacts 808.
By placing the metal of the Cu pillar 702 and the inter-level
metals and contacts 808 in intimate contact with the bulk silicon
substrate 810, the heat generated by the transistor arrays 704
flows into the silicon substrate 810, through the inter-level
metals and contacts 808, and then out the Cu pillar 702 which is in
thermal contact with the heat sink/ground plane 804 of the laminate
interposer or printed circuit board 806.
[0085] Thus, the thermal properties of the silicon substrate 810
spread the heat to the substrate contacts, such as the inter-level
metals and contacts 808. The heat is then removed through the large
area of the substrate contacts, to the Cu pillars 702 and then to
the heat sink/ground plane 804.
[0086] The substrate contacts provided by the inter-level metals
and contacts 808 and the Cu pillars 702 also limit mutual heating
of adjacent transistor arrays 704, which improves many electrical
characteristics, such as current uniformity, gain versus time
characteristics, and the like, of the power amplifier 700.
[0087] In another embodiment, the metal bump or Cu pillar 702 forms
an electrical ground connection to the ground plane 804, which in
turn forms a grounding point through the inter-level metals and
contacts 808. The Cu pillar 702 is in close proximity to the
transistor array 704 and, the emitter-ballasting resistors 708 can
be in communication with the grounding point. In an embodiment, the
grounding point provides emitter degeneration inductance to
maintain high gain over a temperature range. In an embodiment, the
ground is located on the interposed or printed circuit board (PCB)
406.
[0088] FIG. 9 illustrates an embodiment of a base and
emitter-ballasted amplifier 900 comprising an array of 1 to N base
and emitter-ballasted transistor pairs 902(1)-902(n). In an
embodiment, each base and emitter-ballasted transistor pair 902(n)
comprises a first transistor Q1n, a second transistor Q2n, where
each transistor Q1n, Q2n has a base, an emitter, and a collector.
Each base and emitter-ballasted transistor pair 902(n) further
comprises the first base resistor Rb1n, the second base resistor
Rb2n, the first base capacitor Cb1n, the second case capacitor
Cb2n, the first emitter resistor Re1n, and the second emitter
resistor Re2n. In an embodiment, the amplifier 900 comprises a
power amplifier. In a further embodiment, the amplifier 900
comprises a SiGe power amplifier.
[0089] For each base and emitter-ballasted transistor pair 902(n),
the base terminal of the first transistor Q1n electrically couples
to the first terminal of the first base resistor Rb1n and the first
terminal of the first base capacitor Cb1n. And the base terminal of
the second transistor Q2n electrically couples to the first
terminal of the second base resistor Rb2n and the first terminal of
the second base capacitor Cb2n.
[0090] Second terminals of the first base capacitors Cb11 through
Cb1n electrically couple to second terminals of the second base
capacitors Cb21 through Cb2n and to each other to form an amplifier
base or an input 904 to the base and emitter-ballasted amplifier
900. In an embodiment, the input 904 comprises an RF input.
[0091] Second terminals of the first base resistors Rb11 through
Rb1n electrically couple to second terminals of the second base
resistors Rb21 through Rb2n and to each other and are in
communication with a DC base signal 906. In an embodiment, the DC
base signal 906 comprises a ground signal.
[0092] For each base and emitter-ballasted transistor pair 902(n),
the emitter terminal of the first transistor Q1n electrically
couples to the first terminal of the first emitter resistor Re1n.
And the emitter terminal of the second transistor Q2n electrically
couples to the first terminal of the second emitter resistor Re2n.
Second terminals of the first emitter resistors Re11 through Re1n
electrically couple to second terminals of the second emitter
resistors Re21 through Re2n and to each other to form an amplifier
emitter 910 of the base and emitter-ballasted amplifier 900.
[0093] Collector terminals of the first transistors Q11 through Q1n
electrically couple to collector terminals of the second
transistors Q21 through Q2n and to each other to form an amplifier
collector or an output 908 from the base and emitter-ballasting
amplifier 900. In an embodiment, the output 908 comprises an RF
output.
[0094] In an embodiment, the base-ballasting resistor provides base
resistance for the base and emitter-ballasted amplifier 900. The
base resistance provides RF isolation and assists with low
frequency stability for the amplifier 900 under mismatched
termination conditions.
[0095] FIG. 10 illustrates a top view of an exemplary flip-chip
amplifier layout for electrothermal management of a base and
emitter-ballasted amplifier 1000. Amplifier 1000 comprises an array
1004 of transistors Q11-Q1n, Q21-Q2n, a plurality of
base-ballasting resistors 1006, and a plurality of
emitter-ballasting resistors 1008.
[0096] FIG. 11 illustrates a cross section 1700 of the base and
emitter-ballasted amplifier 1000 of FIG. 10. FIG. 11 shows base and
emitter-ballasted transistors Q1, Q2 of the array 1004 formed over
a bulk silicon substrate 1710. The base terminal of the transistor
Q1, Q2 is in communication with the base-ballasting resistor 1006.
The emitter terminal of the transistor Q1, Q2 is in communication
with the emitter-ballasting resistor 1008, which introduces a
discontinuity in the heat transfer of the heat generated in the
emitter to the Cu pillar 1002. FIG. 11 further shows inter-level
metals and contacts 1708 in communication with the bulk silicon
substrate 1710 and the Cu pillar 1002. In an embodiment, the
inter-level metals and contacts 1708 comprise L3 metal, inter-level
contacts (ILC), L2 metal, and L1 metal. The Cu pillar 1002, through
a Cu solder pad, is in contact with a laminate interposer or
printed circuit board 1706. The laminate interposer or printed
circuit board 1706 comprises the Cu solder pad, a Cu via, and a Cu
heat sink/ground plane 1704.
[0097] Referring to FIGS. 10 and 11, in an embodiment, a solution
for thermal management in flip-chip power-amplifier design
comprises placing metal bumps or Cu pillars 1002 adjacent to the
transistor arrays 1004 and over inter-level metals and contacts
1708. By placing the metal of the Cu pillar 1002 and the
inter-level metals and contacts 1708 in intimate contact with a
silicon substrate 1710, the heat generated by the transistor arrays
1004 flows into the silicon substrate 1710, through the inter-level
metals and contacts 1708, and then out the Cu pillar 1002 which is
in thermal contact with the heat sink/ground plane 1704 of the
laminate interposer or printed circuit board 1706.
[0098] Thus, as described above, the thermal properties of the
silicon substrate 1710 spread the heat to the substrate contacts,
such as the inter-level metals and contacts 1708. The heat is then
removed through the large area of the substrate contacts, to the Cu
pillars 1002 and the heat sink/ground plane 1704.
[0099] In another embodiment, the metal bump or Cu pillar 1002
forms an electrical ground connection to the ground plane 1704,
which in turn forms a grounding point through the inter-level
metals and contacts 1708. The Cu pillar 1002 is in close proximity
to the transistor array 1004 and, the emitter-ballasting resistors
1008 can be in communication with the grounding point.
[0100] FIG. 12 illustrates a perspective view of an exemplary flip
chip layout of an amplifier 1200 showing at least Cu pillars 1202
beside transistors arrays 1204. In an embodiment, the amplifier
1200 comprises at least one of a power amplifier, a SiGe power
amplifier, an emitter-ballasted amplifier, a base and
emitter-ballasted amplifier, and a base-ballasted amplifier. FIG.
12 further illustrates the current uniformity benefits of the
design. The three copper pillars 1202 are arranged with two
transistor arrays 1204 between the left copper pillar 1202 and the
middle copper pill 1202 and with another two transistor arrays 1204
between the middle copper pillar 1202 and the right copper pillar
1202. The middle pillar 1202 provides thermal sharing of the heat
generated by the transistor arrays 1204 on both sides of it. The
thermal sharing promotes uniform current density between all of the
transistor arrays 1204. When the currents are uniform, the
amplifier 1200 exhibits more linear performance than when the
currents are not uniform.
[0101] FIG. 13 illustrates an exemplary block diagram of an
amplifier die 1500 including an embodiment of an amplifier 1502. In
an embodiment, the amplifier 1502 comprises the amplifier circuit
or amplifier layout 102, 200, 300, 500, 600, 700, 800, 900, 1000,
1200, 1300, 1400, 1700.
[0102] FIG. 14 illustrates an exemplary block diagram of a module
1600 including amplifier die 1500 of FIG. 13. The module 1600
further includes connectivity 1602 to provide signal
interconnections, packaging 1604, such as for example, a package
substrate, for packaging of the circuitry, and other circuitry die
1606, such as, for example amplifiers, pre-filters, post filters
modulators, demodulators, down converters, and the like, as would
be known to one of skill in the art of semiconductor fabrication in
view of the disclosure herein. In an embodiment, the module 1600
comprises a front-end module.
[0103] FIG. 15 illustrates an exemplary block diagram illustrating
a simplified portable transceiver 1100 including an embodiment of
the amplifier 102, 200, 300, 500, 600, 700, 800, 900, 1000, 1200,
1300, 1400, 1500, 1600, 1700.
[0104] The portable transceiver 1100 includes a speaker 1102, a
display 1104, a keyboard 1106, and a microphone 1108, all connected
to a baseband subsystem 1110. A power source 1142, which may be a
direct current (DC) battery or other power source, is also
connected to the baseband subsystem 1110 to provide power to the
portable transceiver 1100. In a particular embodiment, portable
transceiver 1100 can be, for example but not limited to, a portable
telecommunication device such as a mobile cellular-type telephone.
The speaker 1102 and the display 1104 receive signals from baseband
subsystem 1110, as known to those skilled in the art. Similarly,
the keyboard 1106 and the microphone 1108 supply signals to the
baseband subsystem 1110.
[0105] The baseband subsystem 1110 includes a microprocessor
(.mu.P) 1120, memory 1122, analog circuitry 1124, and a digital
signal processor (DSP) 1126 in communication via bus 1128. Bus
1128, although shown as a single bus, may be implemented using
multiple busses connected as necessary among the subsystems within
the baseband subsystem 1110. The baseband subsystem 1110 may also
include one or more of an application specific integrated circuit
(ASIC) 1132 and a field programmable gate array (FPGA) 1130.
[0106] The microprocessor 1120 and memory 1122 provide the signal
timing, processing, and storage functions for portable transceiver
1100. The analog circuitry 1124 provides the analog processing
functions for the signals within baseband subsystem 1110. The
baseband subsystem 1110 provides control signals to a transmitter
1150, a receiver 1170, and a power amplifier 1180, for example.
[0107] It should be noted that, for simplicity, only the basic
components of the portable transceiver 1100 are illustrated herein.
The control signals provided by the baseband subsystem 1110 control
the various components within the portable transceiver 1100.
Further, the function of the transmitter 1150 and the receiver 1170
may be integrated into a transceiver.
[0108] The baseband subsystem 1110 also includes an
analog-to-digital converter (ADC) 1134 and digital-to-analog
converters (DACs) 1136 and 1138. In this example, the DAC 1136
generates in-phase (I) and quadrature-phase (Q) signals 1140 that
are applied to a modulator 1152. The ADC 1134, the DAC 1136, and
the DAC 1138 also communicate with the microprocessor 1120, the
memory 1122, the analog circuitry 1124, and the DSP 1126 via bus
1128. The DAC 1136 converts the digital communication information
within baseband subsystem 1110 into an analog signal for
transmission to the modulator 1152 via connection 1140. Connection
1140, while shown as two directed arrows, includes the information
that is to be transmitted by the transmitter 1150 after conversion
from the digital domain to the analog domain.
[0109] The transmitter 1150 includes the modulator 1152, which
modulates the analog information on connection 1140 and provides a
modulated signal to upconverter 1154. The upconverter 1154
transforms the modulated signal to an appropriate transmit
frequency and provides the upconverted signal to the power
amplifier 1180. The power amplifier 1180 amplifies the signal to an
appropriate power level for the system in which the portable
transceiver 1100 is designed to operate. In an embodiment, the
power amplifier 1180 comprises the amplifier module 1600.
[0110] Details of the modulator 1152 and the upconverter 1154 have
been omitted, as they will be understood by those skilled in the
art. For example, the data on connection 1140 is generally
formatted by the baseband subsystem 1110 into in-phase (I) and
quadrature (Q) components. The I and Q components may take
different forms and be formatted differently depending upon the
communication standard being employed.
[0111] A front-end module 1162 comprises the power amplifier (PA)
circuit 1180 and a switch/low noise amplifier (LNA) circuit 1172.
In an embodiment, the switch/low noise amplifier circuit 1172
comprises an antenna system interface that may include, for
example, a diplexer having a filter pair that allows simultaneous
passage of both transmit signals and receive signals, as known to
those having ordinary skill in the art.
[0112] In an embodiment, the front-end module 1162 comprises the
module 1600. In an embodiment, the amplifier circuit comprises the
amplifier 102, 200, 300, 500, 600, 700, 800, 900, 1000, 1200, 1300,
1400, 1700.
[0113] The power amplifier 1180 supplies the amplified transmit
signal to the switch/low noise amplifier circuit 1172. The transmit
signal is supplied from the front-end module 1162 to the antenna
1160 when the switch is in the transmit mode.
[0114] A signal received by antenna 1160 will be directed from the
switch/low noise amplifier 1172 of the front-end module 1162 to the
receiver 1170 when the switch is in the receive mode. The low noise
amplifier circuitry 1172 amplifies the received signal.
[0115] If implemented using a direct conversion receiver (DCR), the
downconverter 1174 converts the amplified received signal from an
RF level to a baseband level (DC), or a near-baseband level
(approximately 100 kHz). Alternatively, the amplified received RF
signal may be downconverted to an intermediate frequency (IF)
signal, depending on the application. The downconverted signal is
sent to the filter 1176. The filter 1176 comprises a least one
filter stage to filter the received downconverted signal as known
in the art.
[0116] The filtered signal is sent from the filter 1176 to the
demodulator 1178. The demodulator 1178 recovers the transmitted
analog information and supplies a signal representing this
information via connection 1186 to the ADC 1134. The ADC 1134
converts these analog signals to a digital signal at baseband
frequency and transfers the signal via bus 1128 to the DSP 1126 for
further processing.
[0117] The methods and apparatus described herein provide amplifier
designs for electrothermal management. In embodiments of the
amplifier 102, 200, 300, 700, 800, 900, 1000, 1180, 1200, 1300,
1400, 1500, 1600, 1700, the transistors Q1, Q2, Q11-Q1n, Q21-Q2n
comprise NPN bipolar junction transistors (BJTs). The amplifiers
102, 200, 300, 500, 600, 700, 800, 900, 1000, 1180, 1200, 1300,
1400, 1500, 1600, 1700 can also be implemented using different
technologies, such as, but not limited to SiGe, MOS, PNP BJT, HBT,
pHEMT, GaN, Gas, InGaP Gas HBT, MOSFET, SOI, Bulk CMOS, CMOS, and
the like.
Terminology
[0118] Some of the embodiments described above have provided
examples in connection with mobile phones. However, the principles
and advantages of the embodiments can be used for any other systems
or apparatus that have needs for power amplifier systems.
[0119] Such a system or apparatus can be implemented in various
electronic devices. Examples of the electronic devices can include,
but are not limited to, consumer electronic products, parts of the
consumer electronic products, electronic test equipment, etc.
Examples of the electronic devices can also include, but are not
limited to, memory chips, memory modules, circuits of optical
networks or other communication networks, and disk driver circuits.
The consumer electronic products can include, but are not limited
to, a mobile phone such as a smart phone, a telephone, a
television, a computer monitor, a computer, a hand-held computer, a
laptop computer, a tablet computer, a personal digital assistant
(PDA), a PC card, a microwave, a refrigerator, an automobile, a
stereo system, a cassette recorder or player, a DVD player, a CD
player, a VCR, an MP3 player, a radio, a camcorder, a camera, a
digital camera, a portable memory chip, a washer, a dryer, a
washer/dryer, a copier, a facsimile machine, a scanner, a
multi-functional peripheral device, a wrist watch, a clock, etc.
Further, the electronic devices can include unfinished
products.
[0120] Unless the context clearly requires otherwise, throughout
the description and the claims, the words "comprise," "comprising,"
and the like are to be construed in an inclusive sense, as opposed
to an exclusive or exhaustive sense; that is to say, in the sense
of "including, but not limited to." The word "coupled", as
generally used herein, refers to two or more elements that may be
either directly connected, or connected by way of one or more
intermediate elements. Likewise, the word "connected", as generally
used herein, refers to two or more elements that may be either
directly connected, or connected by way of one or more intermediate
elements. Additionally, the words "herein," "above," "below," and
words of similar import, when used in this application, shall refer
to this application as a whole and not to any particular portions
of this application. Where the context permits, words in the above
Detailed Description using the singular or plural number may also
include the plural or singular number respectively. The word "or"
in reference to a list of two or more items, that word covers all
of the following interpretations of the word: any of the items in
the list, all of the items in the list, and any combination of the
items in the list.
[0121] Moreover, conditional language used herein, such as, among
others, "can," "could," "might," "can," "e.g.," "for example,"
"such as" and the like, unless specifically stated otherwise, or
otherwise understood within the context as used, is generally
intended to convey that certain embodiments include, while other
embodiments do not include, certain features, elements and/or
states. Thus, such conditional language is not generally intended
to imply that features, elements and/or states are in any way
required for one or more embodiments or that one or more
embodiments necessarily include logic for deciding, with or without
author input or prompting, whether these features, elements and/or
states are included or are to be performed in any particular
embodiment.
[0122] The above detailed description of embodiments of the
invention is not intended to be exhaustive or to limit the
invention to the precise form disclosed above. While specific
embodiments of, and examples for, the invention are described above
for illustrative purposes, various equivalent modifications are
possible within the scope of the invention, as those skilled in the
relevant art will recognize. For example, while processes or blocks
are presented in a given order, alternative embodiments may perform
routines having steps, or employ systems having blocks, in a
different order, and some processes or blocks may be deleted,
moved, added, subdivided, combined, and/or modified. Each of these
processes or blocks may be implemented in a variety of different
ways. Also, while processes or blocks are at times shown as being
performed in series, these processes or blocks may instead be
performed in parallel, or may be performed at different times.
[0123] The teachings of the invention provided herein can be
applied to other systems, not necessarily the system described
above. The elements and acts of the various embodiments described
above can be combined to provide further embodiments.
[0124] While certain embodiments of the inventions have been
described, these embodiments have been presented by way of example
only, and are not intended to limit the scope of the disclosure.
Indeed, the novel methods, apparatus, and systems described herein
may be embodied in a variety of other forms; furthermore, various
omissions, substitutions, and changes in the form of the methods
and systems described herein may be made without departing from the
spirit of the disclosure. The accompanying claims and their
equivalents are intended to cover such forms or modifications as
would fall within the scope and spirit of the disclosure.
* * * * *