U.S. patent application number 15/332720 was filed with the patent office on 2018-04-26 for precise/designable finfet resistor structure.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Praneet Adusumilli, Shanti Pancharatnam, Alexander Reznicek, Oscar van der Straten.
Application Number | 20180114827 15/332720 |
Document ID | / |
Family ID | 61951842 |
Filed Date | 2018-04-26 |
United States Patent
Application |
20180114827 |
Kind Code |
A1 |
Adusumilli; Praneet ; et
al. |
April 26, 2018 |
PRECISE/DESIGNABLE FINFET RESISTOR STRUCTURE
Abstract
A resistive material is formed straddling over each
semiconductor fin that extends upward from a surface of a
substrate. The resistive material is then disconnected by removing
the resistive material from atop each semiconductor fin. Remaining
resistive material in the form of a U-shaped resistive material
liner is present between each semiconductor fin. Contact structures
are formed perpendicular to each semiconductor fin and contacting a
portion of a first set of the semiconductor fins and a first set of
the U-shaped resistive material liners.
Inventors: |
Adusumilli; Praneet;
(Albany, NY) ; Pancharatnam; Shanti; (Albany,
NY) ; Reznicek; Alexander; (Troy, NY) ; van
der Straten; Oscar; (Guilderland Center, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
61951842 |
Appl. No.: |
15/332720 |
Filed: |
October 24, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 28/24 20130101;
H01L 27/0629 20130101; H01L 21/76816 20130101; H01L 27/0635
20130101; H01L 27/0802 20130101; H01L 21/02697 20130101; H01L
29/785 20130101; H01L 21/8213 20130101 |
International
Class: |
H01L 49/02 20060101
H01L049/02 |
Claims
1.-10. (canceled)
11. A method of forming a resistor structure, the method
comprising: forming a layer of resistive material straddling over,
and in direct contact with, each semiconductor fin of a plurality
of semiconductor fins, wherein said layer of resistive material is
selected from the group consisting of a metal and a metal nitride;
removing the layer of resistive material from a topmost surface of
each semiconductor fin of the plurality of semiconductor fins,
wherein a U-shaped resistive material liner remains between each
semiconductor fin of the plurality of semiconductor fins; and
forming spaced apart contact structures that are oriented
perpendicular to each semiconductor fin of the plurality of
semiconductor fins, wherein each of the spaced apart contact
structures contacts a different portion of at least one neighboring
pair of semiconductor fins of the plurality of semiconductor fins
and the U-shaped resistive material liner that is located between
the at least one neighboring pair of semiconductor fins of the
plurality of semiconductor fins, and each of the spaced apart
contact structures is in direct physical contact with a topmost
surface of a vertical portion of the U-shaped resistive material
liner that is located between the at least one neighboring pair of
semiconductor fins of the plurality of semiconductor fins.
12. The method of claim 11, wherein the topmost surface of each of
the U-shaped resistive material liners is coplanar with the topmost
surface of each semiconductor fin of the plurality of semiconductor
fins.
13. The method of claim 11, wherein the removing the layer of
resistive material comprises: forming a dielectric material over
the layer of resistive material and over each semiconductor fin of
the plurality of semiconductor fins; and removing an upper portion
of the dielectric material and an upper portion of the layer of
resistive material that is present on the topmost surface of each
semiconductor fin of the plurality of semiconductor fins utilizing
a planarization process.
14. The method of claim 13, further comprising removing an entirety
of a remaining portion of the dielectric material that is present
on each of the U-shaped resistive material liners.
15. The method of claim 13, further comprising partially removing a
remaining portion of the dielectric material.
16. The method of claim 11, wherein the forming the spaced apart
contact structures comprises: forming a middle-of-the-line
dielectric material over each of the U-shaped resistive material
liners and over each semiconductor fin of the plurality of
semiconductor fins; forming contact openings that expose the
different portions of the neighboring pair of semiconductor fins of
the plurality of semiconductor fins and the U-shaped resistive
material liner that is located between the at least one neighboring
pair of semiconductor fins of the plurality of semiconductor fins;
and forming a metal or metal alloy in the contact openings.
17. The method of claim 16, wherein the metal or metal alloy that
provides each contact structure has a lower resistivity than a
metal or metal nitride that provides each of the U-shaped resistive
material liners.
18. The method of claim 17, wherein each of the U-shaped resistive
liners is composed of titanium nitride (TiN), titanium (Ti),
tantalum nitride (TaN), tantalum (Ta), tungsten nitride (WN) or
tungsten (W).
19. The method of claim 18, wherein each of the contact structures
is composed of tungsten (W), cobalt (Co), aluminum (Al), copper
(Cu), or an aluminum-copper (Al--Cu) alloy.
20. (canceled)
21.-22. (canceled)
23. The method of claim 11, wherein the resistor structure has a
resistivity value that can tuned by at least one of the following:
the choice of the metal or the metal nitride used as the layer of
resistive material, a thickness of the layer of resistive material,
a number of neighboring pairs of semiconductor fins of the
plurality of semiconductor fins, a length between each of the
contact structures, and a height of each semiconductor fins of the
plurality of semiconductor fins.
24.-25. (canceled)
26. A method of forming a resistor structure, the method
comprising: forming a layer of resistive material straddling over,
and in direct contact with, each semiconductor fin of a plurality
of semiconductor fins, wherein said layer of resistive material is
selected from the group consisting of a metal and a metal nitride;
removing the layer of resistive material from a topmost surface of
each semiconductor fin of the plurality of semiconductor fins,
wherein a U-shaped resistive material liner remains between each
semiconductor fin of the plurality of semiconductor fins; and
forming spaced apart contact structures that are oriented
perpendicular to each semiconductor fin of the plurality of
semiconductor fins, wherein each of the spaced apart contact
structures contacts a different portion of at least one neighboring
pair of semiconductor fins of the plurality of semiconductor fins
and the U-shaped resistive material liner that is located between
the at least one neighboring pair of semiconductor fins of the
plurality of semiconductor fins, and wherein each of the spaced
apart contact structures is in direct physically contact with a
horizontal surface of the U-shaped resistive material liner that is
located between the at least one neighboring pair of semiconductor
fins of the plurality of semiconductor fins.
Description
BACKGROUND
[0001] The present application relates to a semiconductor structure
and a method of forming the same. More particularly, the present
application relates to a semiconductor structure including a
plurality of U-shaped resistive material liners located between
each semiconductor fin that is present on a surface of a substrate,
and contact structures in contact with a portion of a first set of
the semiconductor fins and with a portion of a first set of the
U-shaped resistive material liners. The present application also
relates to a method of forming such a semiconductor structure.
[0002] A resistor, which is a passive two-terminal electrical
component that implements electrical resistance as a circuit
element, is one of the most common electrical components present in
almost every electrical device. In electronic circuits, resistors
can be used to limit current flow, to adjust signal levels, bias
active elements, and terminate transition lines.
[0003] Front-end-of-the-line (FEOL) resistors are normally created
with active materials (e.g., Si/SiGe), gate materials (e.g., doped
polysilicon) or metals or metal alloys (e.g., tantalum nitride).
Different resistivity resistors are usually offered using
polysilicon resistors, metal resistors and diffusion resistors.
Tuning the resistor value accurately to a specific application is
highly desired and can be difficult using prior resistor
architecture. There is thus a need for providing a resistor
architecture that can be accurately tuned.
SUMMARY
[0004] A resistive material is formed straddling over each
semiconductor fin that extends upward from a surface of a
substrate. The resistive material is then disconnected by removing
the resistive material from atop each semiconductor fin. Remaining
resistive material in the form of a U-shaped resistive material
liner is present between each semiconductor fin. Contact structures
are formed perpendicular to each semiconductor fin and contacting a
portion of a first set of the semiconductor fins and a first set of
the U-shaped resistive material liners. The resistivity value of
the structure can be tuned by any of the following: (1) choice of
resistive material employed as the U-shaped resistive material
liner, (2) the thickness of the U-shaped resistive material liner,
(3) the number of semiconductor fins and U-shaped resistive
material liners contacted, (4) length between contact structures,
and (5) height of each semiconductor fin.
[0005] In one aspect of the present application, a semiconductor
structure (e.g., a FinFET resistor structure) is provided. In one
embodiment of the present application, the semiconductor structure
includes a plurality of semiconductor fins extending upward from a
surface of a substrate. A U-shaped resistive material liner is
located between each neighboring pair of semiconductor fins. A
middle-of-the-line (MOL) dielectric material is located above each
U-shaped resistive material liner and a topmost surface of each
semiconductor fin. Contact structures are located in the MOL
dielectric material and contacting a portion of a first set of the
semiconductor fins and a portion of a first set of the U-shaped
resistive material liners.
[0006] In another aspect of the present application, a method of
forming a semiconductor structure (e.g., a FinFET resistor
structure) is provided. In one embodiment of the present
application, the method includes forming a layer of resistive
material straddling over each semiconductor fin of a plurality of
semiconductor fins. Next, the layer of resistive material is
removed from a topmost surface of each semiconductor fin, wherein a
U-shaped resistive material liner remains between each
semiconductor fin of the plurality of semiconductor fins. Contact
structures are then formed perpendicular to each semiconductor fin,
wherein each contact structure contacts a portion of a first set of
the semiconductor fins and a portion of a first set of the U-shaped
resistive material liners.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0007] FIG. 1 is a cross sectional view of an exemplary
semiconductor structure including a plurality of semiconductor fins
extending upward from a surface of a substrate.
[0008] FIG. 2 is a cross sectional view of the exemplary
semiconductor structure of FIG. 1 after forming a layer of
resistive material on the exposed surface of the substrate and on
exposed sidewalls and a topmost surface of each semiconductor
fin.
[0009] FIG. 3 is a cross sectional view of the exemplary
semiconductor structure of FIG. 2 after forming a dielectric
material on the layer of resistive material.
[0010] FIG. 4 is a cross sectional view of the exemplary
semiconductor structure of FIG. 3 after removing an upper portion
of the dielectric material and an upper portion of the layer of
resistive material to expose the topmost surface of each
semiconductor fin.
[0011] FIG. 5A is a cross sectional view of the exemplary
semiconductor structure of FIG. 4 after removing the remaining
portion of the dielectric material to expose each remaining portion
of the layer of resistive material.
[0012] FIG. 5B is a top down view of the exemplary semiconductor
structure of FIG. 5A.
[0013] FIG. 6 is a top down view of the exemplary semiconductor
structure of FIGS. 5A-5B after forming a middle-of-the-line (MOL)
dielectric material.
[0014] FIG. 7 is a top down view of the exemplary semiconductor
structure of FIG. 6 after forming contact openings in the MOL
dielectric material.
[0015] FIG. 8 is a top down view of the exemplary semiconductor
structure of FIG. 7 after forming a contact structure in each
contact opening.
DETAILED DESCRIPTION
[0016] The present application will now be described in greater
detail by referring to the following discussion and drawings that
accompany the present application. It is noted that the drawings of
the present application are provided for illustrative purposes only
and, as such, the drawings are not drawn to scale. It is also noted
that like and corresponding elements are referred to by like
reference numerals.
[0017] In the following description, numerous specific details are
set forth, such as particular structures, components, materials,
dimensions, processing steps and techniques, in order to provide an
understanding of the various embodiments of the present
application. However, it will be appreciated by one of ordinary
skill in the art that the various embodiments of the present
application may be practiced without these specific details. In
other instances, well-known structures or processing steps have not
been described in detail in order to avoid obscuring the present
application.
[0018] It will be understood that when an element as a layer,
region or substrate is referred to as being "on" or "over" another
element, it can be directly on the other element or intervening
elements may also be present. In contrast, when an element is
referred to as being "directly on" or "directly over" another
element, there are no intervening elements present. It will also be
understood that when an element is referred to as being "beneath"
or "under" another element, it can be directly beneath or under the
other element, or intervening elements may be present. In contrast,
when an element is referred to as being "directly beneath" or
"directly under" another element, there are no intervening elements
present.
[0019] Referring first to FIG. 1, there is illustrated an exemplary
semiconductor structure including a plurality of semiconductor fins
12 extending upward from a surface of a substrate 10. The number of
semiconductor fins 12 that are located on substrate 10 may vary as
long as at least two semiconductor fins 12 are present.
[0020] The exemplary semiconductor structure shown in FIG. 1 can be
formed by first providing a semiconductor substrate. In one
embodiment, the semiconductor substrate may be a bulk semiconductor
substrate. The term "bulk" when used in conjunction with the term
"semiconductor substrate" denotes a substrate that is entirely
composed of at least one semiconductor material having
semiconducting properties; no insulator materials and/or conductive
materials are present in a bulk semiconductor substrate. In such an
embodiment and after performing a patterning process (to be defined
in greater detail below), an upper portion of the bulk
semiconductor substrate constitutes the semiconductor fins 12,
while a remaining portion of the bulk semiconductor substrate
constitutes the substrate 10.
[0021] Examples of semiconductor materials that may provide at
least a portion of the bulk semiconductor substrate include silicon
(Si), germanium (Ge), silicon germanium alloys (SiGe), silicon
carbide (SiC), III-V compound semiconductors or II-VI compound
semiconductors. III-V compound semiconductors are materials that
include at least one element from Group III of the Periodic Table
of Elements and at least one element from Group V of the Periodic
Table of Elements. II-VI compound semiconductors are materials that
include at least one element from Group II of the Periodic Table of
Elements and at least one element from Group VI of the Periodic
Table of Elements. In one example, the bulk semiconductor substrate
may be entirely composed of silicon. In another example, the bulk
semiconductor substrate may include a multilayered semiconductor
material stack of, and in any order, Si and a silicon germanium
alloy.
[0022] The semiconductor material that provides the bulk
semiconductor substrate may be a single crystalline semiconductor
material. The semiconductor material that provides the bulk
semiconductor substrate may have any of the well known crystal
orientations. For example, the crystal orientation of the bulk
semiconductor substrate may be {100}, {110}, or {111}. Other
crystallographic orientations besides those specifically mentioned
can also be used in the present application.
[0023] In another embodiment, the semiconductor substrate that may
be used is a semiconductor-on-insulator (SOI) substrate. The SOI
substrate may include a handle substrate, an insulator layer and a
topmost semiconductor material layer. In some embodiments, the
handle substrate may be omitted. When an SOI substrate is employed,
the topmost semiconductor material layer of the SOI substrate is
patterned into the semiconductor fins 12 shown in FIG. 1, while
substrate 10 includes the insulator layer and, if present, the
handle substrate of the SOI substrate.
[0024] The handle substrate of the SOI substrate may include a
semiconductor material or a non-semiconductor material such as, for
example, a dielectric material and/or a conductive material. When
the handle substrate is a semiconductor material, the semiconductor
material that provides the handle substrate may include one of the
semiconductor materials mentioned above for the bulk semiconductor
substrate. The semiconductor material that can provide the handle
substrate can be a single crystalline semiconductor material and it
can have any of the crystal orientations mentioned above for the
semiconductor material that provides the bulk semiconductor
substrate.
[0025] The insulator layer of the SOI substrate may be a
crystalline or non-crystalline dielectric material. In one
embodiment, the insulator layer of the SOI substrate is a
dielectric oxide such as, for example, silicon dioxide. In another
embodiment, the insulator layer of the SOI substrate is a
dielectric nitride such as, for example, silicon nitride or boron
nitride. In yet another embodiment, the insulator layer of the SOI
substrate may include a multilayered stack of different dielectric
materials. In one example, the insulator layer may include a
multilayered stack of, and in any order, silicon dioxide and boron
nitride.
[0026] The topmost semiconductor layer of the SOI substrate may
include one of the semiconductor materials mentioned above for the
bulk semiconductor substrate. The semiconductor material that can
provide the topmost semiconductor layer of the SOI substrate can be
a single crystalline semiconductor material and it can have any of
the crystal orientations mentioned above for the semiconductor
material that provides the bulk semiconductor substrate. The
semiconductor material that provides the topmost semiconductor
layer of the SOI substrate may be the same as, or different from, a
semiconductor material that provides the handle substrate.
[0027] After providing the semiconductor substrate (i.e., bulk or
SOI), the semiconductor substrate can patterned to provide a
plurality of semiconductor fins 12 extending upward from substrate
10. Each semiconductor fin 12 constitutes either a remaining upper
portion of a bulk semiconductor substrate or the topmost
semiconductor layer of an SOI substrate, and substrate 10
constitutes either a remaining portion of the bulk semiconductor
substrate or at least the insulator layer of the SOI substrate. In
some embodiments, no material interface exists between the
semiconductor fins 12 and the substrate 10. In other embodiments, a
material interface exists between the semiconductor fins 12 and the
substrate 10.
[0028] In one embodiment, patterning may include lithography and
etching. The lithographic process includes forming a photoresist
(not shown) atop a material or material stack to be patterned,
exposing the photoresist to a desired pattern of radiation and
developing the exposed photoresist utilizing a conventional resist
developer. The photoresist may be a positive-tone photoresist, a
negative-tone photoresist or a hybrid-tone photoresist. The
photoresist may be formed utilizing a deposition process such as,
for example, spin-on coating. The etching process includes a dry
etching process (such as, for example, reactive ion etching, ion
beam etching, plasma etching or laser ablation), and/or a wet
chemical etching process. Typically, reactive ion etching is used
in providing the semiconductor fins 12 shown in FIG. 1 of the
present application.
[0029] In another embodiment, patterning may include a sidewall
image transfer (SIT) process. The SIT process includes forming a
mandrel material layer (not shown) atop the material or material
layers that are to be patterned. The mandrel material layer (not
shown) can include any material (semiconductor, dielectric or
conductive) that can be selectively removed from the structure
during a subsequently performed etching process. In one embodiment,
the mandrel material layer (not shown) may be composed of amorphous
silicon or polysilicon. In another embodiment, the mandrel material
layer (not shown) may be composed of a metal such as, for example,
Al, W, or Cu. The mandrel material layer (not shown) can be formed,
for example, by chemical vapor deposition or plasma enhanced
chemical vapor deposition. Following deposition of the mandrel
material layer (not shown), the mandrel material layer (not shown)
can be patterned by lithography and etching to form a plurality of
mandrel structures (also not shown) on the topmost surface of the
structure.
[0030] The SIT process continues by forming a spacer (not shown) on
each sidewall of each mandrel structure. The spacer can be formed
by deposition of a spacer material and then etching the deposited
spacer material. The spacer material may comprise any material
having an etch selectivity that differs from the mandrel material.
Examples of deposition processes that can be used in providing the
spacer material include, for example, chemical vapor deposition
(CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic
layer deposition (ALD). Examples of etching that be used in
providing the spacers include any etching process such as, for
example, reactive ion etching.
[0031] After formation of the spacers, the SIT process continues by
removing each mandrel structure. Each mandrel structure can be
removed by an etching process that is selective for removing the
mandrel material. Following the mandrel structure removal, the SIT
process continues by transferring the pattern provided by the
spacers into the underlying material or material layers. The
pattern transfer may be achieved by utilizing at least one etching
process. Examples of etching processes that can used to transfer
the pattern may include dry etching (i.e., reactive ion etching,
plasma etching, and ion beam etching or laser ablation) and/or a
chemical wet etch process. In one example, the etch process used to
transfer the pattern may include one or more reactive ion etching
steps. Upon completion of the pattern transfer, the SIT process
concludes by removing the spacers from the structure. Each spacer
may be removed by etching or a planarization process.
[0032] As used herein, a "semiconductor fin" refers to a
semiconductor material that includes a pair of vertical sidewalls
that are parallel to each other. As used herein, a surface is
"vertical" if there exists a vertical plane from which the surface
does not deviate by more than three times the root mean square
roughness of the surface. In one embodiment of the present
application, each semiconductor fin 12 has a height from 20 nm to
200 nm, and a width from 5 nm to 30 nm. Other heights and/or widths
that are lesser than, or greater than, the ranges mentioned herein
can also be used in the present application. Each semiconductor fin
12 is spaced apart from its nearest neighboring semiconductor fin
12 by a pitch of from 20 nm to 100 nm. Also, each semiconductor fin
12 is oriented parallel to each other. A gap 13 is present between
each neighboring pairs of semiconductor fins 12.
[0033] Referring now to FIG. 2, there is illustrated the exemplary
semiconductor structure of FIG. 1 after forming a layer of
resistive material 14L on the exposed surface of the substrate 10
and on exposed sidewalls and a topmost surface of each
semiconductor fin 12. The layer of resistive material 14L is a
continuous (without and breaks and/or voids) layer that straddles
over each semiconductor fin 12. By "straddles over" it is meant
that a material (such as, for example, the layer of resistive
material 14L) is present on sidewalls and a topmost surface of
another material (such as for example, the semiconductor fin
12).
[0034] The layer of resistive material 14L may include a metal or
metal alloy such as, for example, titanium nitride (TiN), titanium
(Ti), tantalum nitride (TaN), tantalum (Ta), tungsten nitride (WN)
or tungsten (W). The metal or metal alloy that provides the layer
of resistive material 14L determines, at least in part, the
resistivity of the resistor of the present application. The layer
of resistive material 14L may be formed utilizing a deposition
process such as, for example, chemical vapor deposition (CVD),
plasma enhanced chemical vapor deposition (PECVD) physical vapor
deposition (PVD) or atomic layer deposition (ALD).
[0035] The layer of resistive material 14L may have a thickness
from 10 nm to 100 nm. Other thicknesses that are lesser than, or
greater than, the aforementioned thickness range may also be used
as the thickness of the layer of resistive material 14L as long as
the thickness of the layer of resistive material 14L does not fill
in the entirety of gap 13. The thickness of the layer of resistive
material 14L determines, at least in part, the resistivity of the
resistor of the present application.
[0036] In some embodiments, the layer of resistive material 14L is
a conformal layer (i.e., a material whose vertical thickness above
a horizontal surface of an underlying material is the same as a
lateral thickness along a sidewall surface of laterally adjacent
material). In yet another embodiment, the layer of resistive
material 14L is a non-conformal layer. In such an embodiment, the
vertical thickness of the layer of resistive material 14L above a
horizontal surface of an underlying material may be greater than
the lateral thickness of the layer of resistive material 14L along
the sidewalls of a laterally adjacent material.
[0037] Referring now to FIG. 3, there is illustrated the exemplary
semiconductor structure of FIG. 2 after forming a dielectric
material 16 on the layer of resistive material 14L. The dielectric
material 16 that can be employed may include a middle-of-the line
(MOL) dielectric material.
[0038] The dielectric material 16 covers the substrate 10 and the
entirety of the layer of resistive material 14L. The dielectric
material 16 may be composed of, for example, silicon dioxide,
undoped silicate glass (USG), fluorosilicate glass (FSG),
borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer,
a chemical vapor deposition (CVD) low-k dielectric layer or any
combination thereof. The term "low-k" as used throughout the
present application denotes a dielectric material that has a
dielectric constant of less than silicon dioxide. In another
embodiment, a self-planarizing material such as a spin-on glass
(SOG) or a spin-on low-k dielectric material such as SiLK.TM. can
be used as the dielectric material 16. The use of a
self-planarizing dielectric material as dielectric material 16 may
avoid the need to perform a subsequent planarizing step.
[0039] In one embodiment, the dielectric material 16 can be formed
utilizing a deposition process including, for example, chemical
vapor deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), evaporation or spin-on coating. In some embodiments, a
planarization process or an etch back process follows the
deposition of the dielectric material 16. The thickness of the
dielectric material 16 that can be employed in the present
application may vary depending on the type of material employed as
well as the method that was employed in forming the same. In one
embodiment, the dielectric material 16 has a thickness from 80 nm
to 500 nm. Other thicknesses that are greater or lesser than the
range provided above can also be used for the dielectric material
16.
[0040] Referring now to FIG. 4, there is illustrated the exemplary
semiconductor structure of FIG. 3 after removing an upper portion
of the dielectric material 16 and an upper portion of the layer of
resistive material 14L to expose the topmost surface of each
semiconductor fin 12. The removal of the upper portion of the
dielectric material 16 and the upper portion of the layer of
resistive material 14L may be performed utilizing a planarization
process such as, for example, chemical mechanical polishing and/or
grinding. After removing the upper portion of the dielectric
material 16 and the upper portion of the layer of resistive
material 14L, a portion of the dielectric material 16 and a portion
of the layer of resistive material 14L remain in the gap 13.
[0041] Each remaining portion of the dielectric material 16 is
referred to herein as a dielectric material portion 16P and each
remaining portion of the layer of resistive material 14L may be
referred to herein as a U-shaped resistive material liner 14. By
"U-shaped" it is meant a material that has a horizontal portion
(labeled as element 14A) and two vertical portions (labeled as
element 14B) that extend upwards from each end of the horizontal
portion 14A. The vertical portions 14B of each U-shaped resistive
material liner 14 are present along a sidewall of one of the
semiconductor fins 12, while the horizontal portion 14A of the
U-shaped resistive material liner 14 is present on a topmost
surface of the substrate 10. As is shown, each U-shaped resistive
material liner 14 has a topmost that is coplanar with a topmost
surface of each semiconductor fin 12 as well the topmost surface of
each dielectric material portion 16P. At this point of the present
application, the U-shaped resistive material liners 14 are
disconnected from each other.
[0042] Referring now to FIGS. 5A-5B, there are shown various views
of the exemplary semiconductor structure of FIG. 4 after removing
the remaining portion of the dielectric material (i.e., dielectric
material portions 16P) to expose each remaining portion of the
layer of resistive material (i.e., the U-shaped resistive material
14). In some embodiments (and as shown), each dielectric material
portion 16P is entirely removed. In such an embodiment, the
entirety of each U-shaped restive material liner 14 is exposed. In
another embodiment (not shown), each dielectric material portion
16P is partially removed. In such an embodiment, the upper portion
of each U-shaped restive material liner 14 is exposed. In yet other
embodiments, this step of the present application may be
omitted.
[0043] The complete or partial removal of the dielectric material
portions 16P may be performed utilizing an anisotropic etching
process that is selective in removing the dielectric material that
provides each dielectric material portion 16P relative to the
resistive material that provides the U-shaped resistive material
liners 14 and the semiconductor material that provides the
semiconductor fins 12. In one example, and when an oxide is
employed as the dielectric material that provides each dielectric
material portion 16P, each dielectric material portion 16P may be
removed (entirely or partially) utilizing an anisotropic etching
process in which hydrofluoric acid (HF) or a mixture of ammonium
fluoride and hydrofluoric acid (so called buffer oxide etchant) can
be employed as a chemical etchant. In another example, and when an
oxide is employed as the dielectric material that provides each
dielectric material portion 16P, each dielectric material portion
16P may be removed (entirely or partially) utilizing an anisotropic
etching process in which a plasma of CF.sub.4, SF.sub.6 of NF.sub.3
can be employed as an etchant.
[0044] Referring now to FIG. 6, there is illustrated the exemplary
semiconductor structure of FIGS. 5A-5B after forming a
middle-of-the-line (MOL) dielectric material 18. The MOL dielectric
material 18 may include one of the dielectric materials mentioned
above for dielectric material 16. In some embodiments, the
dielectric material that provides the MOL dielectric material 18
may be the same as the dielectric material that provides dielectric
material 16. In other embodiments, the dielectric material that
provides the MOL dielectric material 18 may be a different
dielectric material than dielectric material 16. The MOL dielectric
material 18 may be formed utilizing one of the techniques mentioned
above in forming dielectric material 16. The MOL dielectric
material 18 may have a thickness within the range mentioned above
for dielectric material 16.
[0045] In some embodiments and when the dielectric material
portions 16P are completely removed, the MOL dielectric material 18
is formed within each gap 13 and directly on each U-shaped
resistive material liner 14. In such an embodiment, the MOL
dielectric material 18 is also formed directly on a topmost surface
of each semiconductor fin 12.
[0046] In other embodiments and when the dielectric material
portions 16P are partially removed, the MOL dielectric material 18
is formed within each gap 13 and directly on a remaining segment of
each dielectric material portion 16P and directly on any exposed
portion of each U-shaped resistive material liner 14. In such an
embodiment, the MOL dielectric material 18 is also formed directly
on a topmost surface of each semiconductor fin 12.
[0047] In yet further embodiments and when the dielectric material
portions 16P are not removed, the MOL dielectric material 18 is
formed directly on the topmost surfaces of each dielectric material
portion 16P and each semiconductor fin 12.
[0048] Referring now to FIG. 7, there is illustrated the exemplary
semiconductor structure of FIG. 6 after forming contact openings
20L, 20R in the MOL dielectric material 18. Each contact opening
20L, 20R is spaced apart from one another. Although the present
application illustrates the formation of two contact openings 20L,
20R, the present application is not limited to the formation of two
contact openings. Instead, more than two contact openings can be
formed as desired. The number of contact openings that are formed
can also, in part, determine the resistivity of the resistor of the
present application.
[0049] As is shown, each contact opening exposes a portion of a
first set of the semiconductor fins 12 and a portion of a first set
of the U-shaped resistive material liners 14 (including the
vertical portions 14B and the horizontal portions 14A of a
particular U-shaped resistive material liner 14). In the
illustrated embodiment, contact opening 20L exposes a first portion
of a first set of the semiconductor fins 12 and a first portion of
a first set of the U-shaped resistive material liners 14, while the
second contact opening exposes a second portion of the first set of
the semiconductor fins 12 and a second portion of the first set of
the U-shaped resistive material liners 14. The number of
semiconductor fins 12 and U-shaped resistive material liners 14
that are exposed by the contact openings may vary and is not
limited to two as is shown by way of one example in FIG. 7. Each
contact opening 20R, 20L can be formed utilizing conventional
techniques such as, for example, lithography and etching.
[0050] Referring now to FIG. 8, there is illustrated the exemplary
semiconductor structure of FIG. 7 after forming a contact structure
22L, 22R in each contact opening 20L, 20R; the contact structures
may also be referred to as metal contact structures. Each contact
structure 22L, 22R is spaced apart from each other by a specific
distance. As evident by comparing FIGS. 7 and 8 to each other, each
contact structure 22L, 22R is formed perpendicular to the
semiconductor fins 12. Although the present application illustrates
the formation of two contact structures 22L, 22R within two contact
openings 20L, 20R, the present application is not limited to the
formation of two contact structures. Instead, more than two contact
structures can be formed as desired. The length, i.e., distance,
between each contact structure 22L, 22R may also, in part,
determine the resistivity of the resistor of the present
application.
[0051] Each contact structure 22L, 22R may be composed of a metal
or metal alloy having a lower resistivity than the metal or metal
alloy that provides each U-shaped resistive material liner 14.
Stated in opposite terms, the metal or metal alloy that provides
each U-shaped resistive material liner 14 has a higher resistivity
than the metal or metal alloy that provides each contact structure
22L, 22R. Examples of metals or metal alloys that can be employed
as the contact structure 22L, 22R include, but are not to, tungsten
(W), cobalt (Co), aluminum (Al), copper (Cu), or an aluminum-copper
(Al--Cu) alloy. Each contact structure 22L, 22R may be formed by
deposition of a contact metal or metal alloy, followed by a
planarization process such as, for example, chemical mechanical
polishing. Each contact structure 22L, 22R has a topmost surface
that is coplanar with a topmost surface of the MOL dielectric
material 18.
[0052] As is shown, each contact 22L, 22R structure lies
perpendicular to each semiconductor fin 12. Also, each contact
structure 22L, 22R contacts the exposed portion of the first set of
the U-shaped resistive material liners 14 (notably each contact
structure contacts the vertical portions and horizontal portions of
each of the exposed U-shaped resistive material liners) and the
exposed portion of the first set of the semiconductor fins 12. In
the illustrated embodiment, the contact structure 22L contacts an
exposed first portion of the first set of the semiconductor fins 12
and an exposed first portion of the first set of the U-shaped
resistive material liners 14, while contact structure 22R contacts
the exposed second portion of the first set of the semiconductor
fins 12 and the exposed second portion of the first set of the
U-shaped resistive material liners 14.
[0053] It is noted that the desired resistivity value of the
structure can be tuned by any of the following: (1) choice of
resistive material employed as the U-shaped resistive material
liner 14, (2) the thickness of the U-shaped resistive material
liner 14, (3) the number of semiconductor fins 12 and U-shaped
resistive material liners 14 exposed by the contact openings 20A,
20B, (4) length between contact structures 22L, 22R, and (5) height
of each semiconductor fin 12.
[0054] While the present application has been particularly shown
and described with respect to preferred embodiments thereof, it
will be understood by those skilled in the art that the foregoing
and other changes in forms and details may be made without
departing from the spirit and scope of the present application. It
is therefore intended that the present application not be limited
to the exact forms and details described and illustrated, but fall
within the scope of the appended claims.
* * * * *