U.S. patent application number 15/189749 was filed with the patent office on 2017-12-28 for reflow enhancement layer for metallization structures.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten.
Application Number | 20170372954 15/189749 |
Document ID | / |
Family ID | 60516385 |
Filed Date | 2017-12-28 |
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United States Patent
Application |
20170372954 |
Kind Code |
A1 |
Adusumilli; Praneet ; et
al. |
December 28, 2017 |
REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES
Abstract
A reflow enhancement layer is formed in an opening prior to
forming and reflowing a contact metal or metal alloy. The reflow
enhancement layer facilitates the movement (i.e., flow) of the
contact metal or metal alloy during a reflow anneal process such
that a void-free metallization structure of the contact metal or
metal alloy is provided.
Inventors: |
Adusumilli; Praneet;
(Albany, NY) ; Reznicek; Alexander; (Troy, NY)
; van der Straten; Oscar; (Guilderland Center,
NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
60516385 |
Appl. No.: |
15/189749 |
Filed: |
June 22, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/76882 20130101;
H01L 23/53209 20130101; H01L 21/76843 20130101; H01L 21/76883
20130101; H01L 21/76864 20130101; H01L 23/53266 20130101 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 23/532 20060101 H01L023/532 |
Claims
1. A semiconductor structure comprising: a reflow enhancement liner
located in at least a portion of an opening present in a
dielectric-containing substrate, said reflow enhancement liner
having a horizontal portion and two vertical portions extending
from opposite ends of said horizontal portion; and a metallization
structure located on said horizontal portion of said reflow
enhancement liner and completely filling a volume located between
said two vertical portions of said reflow enhancement liner,
wherein said reflow enhancement liner and said metallization
structure have topmost surfaces that are coplanar with each other
and are located entirely within said opening, and wherein said
reflow enhancement liner is of a different composition than said
metallization structure.
2. The semiconductor structure of claim 1, further comprising a
diffusion barrier liner located beneath, and in direct with, said
reflow enhancement liner.
3. The semiconductor structure of claim 2, wherein
dielectric-containing structure is entirely composed of a
middle-of-the line dielectric material layer.
4. The semiconductor structure of claim 3, wherein said topmost
surfaces of each of said reflow enhancement liner and said
metallization structure are coplanar with a topmost surface of said
middle-of-the-line dielectric material layer.
5. The semiconductor structure of claim 4, further comprising a cap
located on said topmost surfaces of said reflow enhancement liner,
said metallization structure and said middle-of-the-line dielectric
material layer.
6. The semiconductor structure of claim 1, further comprising a
gate dielectric portion and a work function metal portion located
beneath said reflow enhancement liner, wherein said work function
metal portion directly contacts said reflow enhancement liner.
7. The semiconductor structure of claim 6, wherein said
dielectric-containing substrate includes a pair of dielectric
spacers surrounding said opening, and wherein said reflow
enhancement liner and said metallization structure are located in a
bottom portion of said opening.
8. The semiconductor structure of claim 7, further comprising a cap
located in an upper portion of said opening.
9. The semiconductor structure of claim 8, wherein said cap is
located on said topmost surfaces of each of said reflow enhancement
liner and said metallization structure, and wherein said cap has a
topmost surface that is coplanar with a topmost surface of said
middle-of-the-line dielectric material layer.
10. The semiconductor structure of claim 1, wherein said
metallization structure comprises cobalt.
11. The semiconductor structure of claim 10, wherein said reflow
enhancement liner is composed of a metal or metal alloy selected
from the group consisting of ruthenium, iridium, a tantalum-iridium
alloy, a niobium-ruthenium alloy and a niobium-iridium alloy.
12-20. (canceled)
21. A semiconductor structure comprising: a reflow enhancement
liner located in an opening present in a middle-of-the-line
dielectric material layer that is located on a surface of a
semiconductor substrate containing at least one semiconductor
device, said reflow enhancement liner having a horizontal portion
and two vertical portions extending from opposite ends of said
horizontal portion; and a metallization structure located on said
horizontal portion of said reflow enhancement liner and completely
filling a volume located between said two vertical portions of said
reflow enhancement liner, wherein said metallization structure,
said reflow enhancement liner, and middle-of-the-line dielectric
material layer have topmost surfaces that are coplanar with each
other, and wherein said reflow enhancement liner is of a different
composition than said metallization structure.
22. A semiconductor structure comprising: a gate cavity present in
a middle-of-the-line dielectric material layer that is located
above a semiconductor fin; a dielectric spacer located in said at
least one gate cavity, said dielectric spacer having a topmost
surface that is coplanar with a topmost structure of said
middle-of-the-line dielectric material layer; a gate dielectric
portion located adjacent each dielectric spacer and in a lower
portion of said at least one gate cavity; a work function metal
portion located on said gate dielectric portion and in said lower
portion of said at least one gate cavity; a reflow enhancement
liner located on said work function metal portion and in said lower
portion of said at least one gate cavity, said reflow enhancement
liner having a horizontal portion and two vertical portions
extending from opposite ends of said horizontal portion therein;
and a metallization structure located on said horizontal portion of
said reflow enhancement liner and completely filling a volume
located between said two vertical portions of said reflow
enhancement liner, wherein a topmost surface of said gate
dielectric portion, said work function metal portion, said reflow
enhancement liner, and said metallization structure are coplanar
with each other and are vertically offset and located beneath said
topmost surface of said middle-of-the-line dielectric material
layer, and wherein said reflow enhancement liner is of a different
composition than said metallization structure.
Description
BACKGROUND
[0001] The present application relates to a semiconductor structure
and a method of forming the same. More particularly, the present
application relates to a semiconductor structure in which a
void-free metallization structure is located on a surface of a
reflow enhancement layer and a method of forming such a
semiconductor structure.
[0002] As the dimensions of semiconductor devices including, for
example, middle-of-the-line (MOL) contacts, are scaled down, the
currently used tungsten (W) metallization scheme will not be able
to meet the resistance targets for future technology nodes. This
high resistance for tungsten is a result of the need for utilizing
thick diffusion barrier liners and poor tungsten gap fill.
[0003] Cobalt (Co) provides an alternative to tungsten fill for MOL
contacts, and is typically performed by chemical vapor deposition
(CVD) to fill the groundrule features followed by a physical vapor
deposition (PVD) to remove cobalt overburden. A high temperature
anneal is then applied to reduce seams in the cobalt.
[0004] Due to the need for this high temperature anneal, voids in
cobalt can migrate to the bottom of the features, and cause very
high contact resistance or openings. There is thus a need for
providing cobalt contacts (and other metallic contacts) that avoids
the migration of the metallic material to the bottom of the
features and thus lowers the contact resistance of the
structure.
SUMMARY
[0005] A reflow enhancement layer is formed in an opening prior to
forming and reflowing a contact metal or metal alloy. The reflow
enhancement layer facilitates the movement (i.e., flow) of the
contact metal or metal alloy during a reflow anneal process such
that a void-free metallization structure of the metal or metal
alloy is provided.
[0006] In one aspect of the present application, a semiconductor
structure including a void-free metallization structure and a
reflow enhancement liner is provided. In one embodiment of the
present application, the semiconductor structure includes a reflow
enhancement liner located in at least a portion of an opening
present in a dielectric-containing substrate, the reflow
enhancement liner has a horizontal portion and two vertical
portions extending from opposite ends of the horizontal portion. A
metallization structure is located on the horizontal portion of the
reflow enhancement liner and completely fills a volume located
between the two vertical portions of the reflow enhancement
liner.
[0007] In another aspect of the present application, a method of
forming a semiconductor structure including a void-free
metallization structure and a reflow enhancement liner is provided.
In one embodiment of the present application, the method includes
providing an opening in a dielectric-containing substrate. Next, a
reflow enhancement layer is formed in the opening and atop the
dielectric-containing substrate. A layer of a contact metal or
metal alloy is then formed on the reflow enhancement layer. Next, a
reflow anneal is performed to completely fill a remaining volume of
the opening with the contact metal or metal alloy of the layer of
contact metal or metal alloy. After the reflow anneal, the layer of
contact metal or metal alloy, and the reflow enhancement layer that
are located outside of the opening are removed. A portion of the
layer of contact metal or metal alloy, and a portion of the reflow
enhancement layer remain within the opening after the removal
process.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0008] FIG. 1 is a cross sectional view of an exemplary
semiconductor structure including a plurality of openings formed in
a middle-of-the-line (MOL) dielectric material layer, the openings
having vertical sidewalls and a constant width.
[0009] FIG. 2 is a cross sectional view of the exemplary
semiconductor structure of FIG. 1 after forming a diffusion barrier
material and a reflow enhancement layer.
[0010] FIG. 3 is a cross sectional view of the exemplary
semiconductor structure of FIG. 2 after depositing a layer of a
contact metal or metal alloy and performing a reflow anneal.
[0011] FIG. 4 is a cross sectional view of the exemplary
semiconductor structure of FIG. 3 after performing a planarization
process.
[0012] FIG. 5 is a cross sectional view of the exemplary
semiconductor structure of FIG. 4 after forming a cap on exposed
surfaces of the planarized structure.
[0013] FIG. 6 is a cross sectional view of another exemplary
semiconductor structure including at least one gate cavity
surrounded by a dielectric spacer and a middle-of-the line (MOL)
dielectric material layer.
[0014] FIG. 7 is a cross sectional view of the exemplary
semiconductor structure of FIG. 8 after forming a gate dielectric
material and a work function metal at least within each gate
cavity.
[0015] FIG. 8 is a cross sectional view of the exemplary
semiconductor structure of FIG. 7 after forming a reflow
enhancement layer on the work function metal.
[0016] FIG. 9 is a cross sectional view of the exemplary
semiconductor structure of FIG. 8 after depositing a layer of a
contact metal or metal alloy and performing a reflow anneal.
[0017] FIG. 10 is a cross sectional view of the exemplary
semiconductor structure of FIG. 9 after performing a planarization
process, recessing and formation of a cap.
DETAILED DESCRIPTION
[0018] The present application will now be described in greater
detail by referring to the following discussion and drawings that
accompany the present application. It is noted that the drawings of
the present application are provided for illustrative purposes only
and, as such, the drawings are not drawn to scale. It is also noted
that like and corresponding elements are referred to by like
reference numerals.
[0019] In the following description, numerous specific details are
set forth, such as particular structures, components, materials,
dimensions, processing steps and techniques, in order to provide an
understanding of the various embodiments of the present
application. However, it will be appreciated by one of ordinary
skill in the art that the various embodiments of the present
application may be practiced without these specific details. In
other instances, well-known structures or processing steps have not
been described in detail in order to avoid obscuring the present
application.
[0020] It will be understood that when an element as a layer,
region or substrate is referred to as being "on" or "over" another
element, it can be directly on the other element or intervening
elements may also be present. In contrast, when an element is
referred to as being "directly on" or "directly over" another
element, there are no intervening elements present. It will also be
understood that when an element is referred to as being "beneath"
or "under" another element, it can be directly beneath or under the
other element, or intervening elements may be present. In contrast,
when an element is referred to as being "directly beneath" or
"directly under" another element, there are no intervening elements
present.
[0021] Referring first to FIG. 1, there is illustrated an exemplary
semiconductor structure including a plurality of openings 14 formed
in a middle-of-the-line (MOL) dielectric material layer 12, the
openings 14 having vertical sidewalls, s1, and a constant width,
w1. In this embodiment of the present application, the MOL
dielectric material layer 12 is formed on a surface of a substrate
10. The substrate 10 may include a semiconductor substrate such as,
for example, silicon, containing one or more semiconductor devices,
i.e., transistors, formed thereon. The one or more semiconductor
devices are not shown but would be located on a surface of
substrate 10 and would be embedded within some portions of the MOL
dielectric material layer 12. Although a plurality of openings 14
is described and illustrated, the present application works when a
single opening 14 is formed into the MOL dielectric material layer
12.
[0022] In some embodiments of the present application, each opening
14 can extend entirely though the MOL dielectric material layer 12
and expose a portion of the substrate 10. In some embodiments, the
exposed portion of the substrate 10 represents a source/drain
region of a transistor.
[0023] In one embodiment of the present application, the substrate
10 is first provided and then the one or more semiconductor devices
are formed thereon. The MOL dielectric material layer 12 is then
formed. In other embodiments, sacrificial structures are formed on
the surface of the substrate 10 and then the MOL dielectric
material layer 12 is formed. After forming the MOL dielectric
material layer 12, the sacrificial structure may be replaced with a
functional semiconductor device.
[0024] In some embodiments, the MOL dielectric material layer 12
may be composed of, for example, silicon dioxide, undoped silicate
glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass
(BPSG), a spin-on low-k dielectric layer, a chemical vapor
deposition (CVD) low-k dielectric layer or any combination thereof.
The term "low-k" as used throughout the present application denotes
a dielectric material that has a dielectric constant of less than
silicon dioxide. In another embodiment, a self-planarizing material
such as a spin-on glass (SOG) or a spin-on low-k dielectric
material such as SiLK.TM. can be used as the MOL dielectric
material layer 12. The use of a self-planarizing dielectric
material as MOL dielectric material layer 12 may avoid the need to
perform a subsequent planarizing step.
[0025] In one embodiment, the MOL dielectric material layer 12 can
be formed utilizing a deposition process including, for example,
chemical vapor deposition (CVD), plasma enhanced chemical vapor
deposition (PECVD), evaporation or spin-on coating. In some
embodiments, particularly when non-self-planarizing dielectric
materials are used as MOL dielectric material layer 12, a
planarization process or an etch back process follows the
deposition of the dielectric material. The thickness of the MOL
dielectric material layer 12 that can be employed in the present
application may vary depending on the type of dielectric material
employed as well as the method that was employed in forming the
same. In one embodiment, the MOL dielectric material layer 12 has a
thickness from 80 nm to 100 nm. Other thicknesses that are greater
or lesser than the range provided above can also be used for the
MOL dielectric material layer 12.
[0026] The at least one opening 14 that is formed into the MOL
dielectric material layer 12 can be formed utilizing a patterning
process. In one embodiment, the patterning process may include
lithography and etching. The lithographic process includes forming
a photoresist (not shown) atop the MOL dielectric material layer
12, exposing the photoresist to a desired pattern of radiation and
developing the exposed photoresist utilizing a conventional resist
developer. The photoresist may be a positive-tone photoresist, a
negative-tone photoresist or a hybrid-tone photoresist. The etching
process includes a dry etching process (such as, for example,
reactive ion etching, ion beam etching, plasma etching or laser
ablation), and/or a wet chemical etching process. Typically,
reactive ion etching is used in providing the at least one opening
14.
[0027] Referring now to FIG. 2, there is illustrated the exemplary
semiconductor structure of FIG. 1 after forming a diffusion barrier
material 16 and a reflow enhancement layer 18. As is shown, the
diffusion barrier material 16 is formed as a continuous layer on
the exposed topmost surface of the MOL dielectric material layer 12
and along the sidewall surfaces, s1, and bottommost surface of each
opening 14. The reflow enhancement layer 18 is a continuous layer
that is formed on the diffusion barrier material 16.
[0028] The diffusion barrier material 16 includes Ta, TaN, Ti, TiN,
Ru, RuN, RuTa, RuTaN, W, WN or any other material that can serve as
a barrier to prevent a conductive material such as cobalt from
diffusing there through. In some embodiments, the diffusion barrier
material may include a material stack of such diffusion barrier
materials. In one example, the diffusion barrier may be composed of
a stack of Ta/TaN.
[0029] The thickness of the diffusion barrier material 16 may vary
depending on the deposition process used as well as the material
employed. In some embodiments, the diffusion barrier material 16
may have a thickness from 2 nm to 50 nm; although other thicknesses
for the diffusion barrier material 16 are contemplated and can be
employed in the present application. The diffusion barrier material
16 can be formed by a deposition process including, for example,
chemical vapor deposition (CVD), plasma enhanced chemical vapor
deposition (PECVD), atomic layer deposition (ALD), physical vapor
deposition (PVD), sputtering, chemical solution deposition or
plating.
[0030] The reflow enhancement layer 18 is then formed on the
diffusion barrier material 16. The reflow enhancement layer 18
includes any metal or metal alloy that facilities in the movement
(i.e., flow) of another deposited metal or metal alloy that differs
in composition from the reflow enhancement layer 18 during a
subsequently performed reflow anneal process. Examples of metals or
metal alloys that may be employed as the reflow enhancement layer
18 include ruthenium, iridium, a tantalum-iridium alloy, a
niobium-ruthenium alloy and a niobium-iridium alloy. In one
embodiment and when a layer of cobalt is to be subsequently formed
and reflowed, the reflow enhancement layer 18 is composed of
ruthenium or iridium.
[0031] The thickness of reflow enhancement layer 18 may vary
depending on the material of the reflow enhancement layer 18 as
well as the technique used in forming the same. Typically, the
reflow enhancement layer 18 has a thickness from 2 nm to 80 nm. The
reflow enhancement layer 18 can be formed by a conventional
deposition process including, for example, CVD, PECVD, ALD, or
PVD.
[0032] It is noted that the total thickness of the diffusion
barrier material 16 and the reflow enhancement layer 18 is
insufficient to completely fill the total volume of each opening
14. Thus, a portion (i.e., a volume) of each opening 14 is
available for further processing.
[0033] Referring now to FIG. 3, there is illustrated the exemplary
semiconductor structure of FIG. 2 after depositing a layer of
contact metal or metal alloy and performing a reflow anneal. In
FIG. 3, element 20 denotes the deposited and reflowed layer of
contact metal or metal alloy. As is shown, the deposited and
reflowed layer of contact metal or metal alloy 20 completely fills
in the remaining portion (i.e., volume) of each opening 14; an
overburden portion of the deposited and reflowed layer of contact
metal or metal alloy 20 forms outside each opening 14 and above the
topmost surface of the MOL dielectric material layer 12.
[0034] The deposited and reflowed layer of contact metal or metal
alloy 20 is formed by first depositing a contact metal or metal
alloy directly on the reflow enhancement layer 18 and then
performing a reflow anneal. The contact metal or metal alloy that
may be employed in the present application includes cobalt (Co),
platinum, (Pt), and/or nickel (Ni). The contact metal or metal
alloy can be formed by a deposition process including PVD, chemical
vapor deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), sputtering, chemical solution deposition or plating.
[0035] Next, a reflow anneal is performed. In one embodiment of the
present application, the reflow anneal is a thermal anneal. In one
example, the reflow anneal may include a furnace anneal or a hot
plate anneal. The reflow anneal may be performed at a temperature
from 100.degree. C. to 500.degree. C. Other temperatures can also
be employed so long as the selected reflow anneal temperature
causes the reflow of the contact metal or metal alloy. The duration
of the reflow anneal may vary depending upon the temperature used
during the thermal anneal. In one embodiment and for a temperature
from 100.degree. C. to 500.degree. C., the reflow anneal may be
performed for a duration of 20 minutes to 3 hours.
[0036] The reflow anneal is typically performed in a
nitrogen-containing ambient or a hydrogen-containing ambient. The
nitrogen-containing ambients that can be employed in the present
application include, but are not limited to, N.sub.2, or NH.sub.3,
and mixtures thereof. In some embodiments, the nitrogen-containing
ambient is used neat, i.e., non-diluted. In other embodiments, the
nitrogen-containing ambient can be diluted with an inert gas such
as, for example, He, Ne, Ar and mixtures thereof. In some
embodiments, H.sub.2 can be used to dilute the nitrogen-containing
ambient. Notwithstanding whether the nitrogen-containing ambient is
employed neat or diluted, the content of nitrogen within the
nitrogen-containing ambient employed in the present application is
typically from 10% to 100%, with a nitrogen content within the
nitrogen-containing ambient from 50% to 80% being more typical.
[0037] Referring now to FIG. 4, there is illustrated the exemplary
semiconductor structure of FIG. 3 after performing a planarization
process. The planarization process removes portions of the
deposited and reflowed layer of contact metal or metal alloy 20,
portions of the reflow enhancement layer 18, and portions of the
diffusion barrier material 16 that are present outside each opening
14. Planarization may be performed utilizing chemical mechanical
polishing and/or grinding.
[0038] After planarization, a portion of the deposited and reflowed
layer of contact metal or metal alloy 20, a portion of the reflow
enhancement layer 18, and a portion of the diffusion barrier
material 16 remain within each opening 14. Each remaining portion
of the deposited and reflowed layer of contact metal or metal alloy
20 can be referred to as a metallization structure 20S. Each
remaining portion of the reflow enhancement layer 18 can be
referred to herein as a reflow enhancement liner 18L, and each
remaining portion of the diffusion barrier material 16 may be
referred to herein as a diffusion barrier liner 16L. As is shown,
topmost surfaces of each of the metallization structure 20S, the
reflow enhancement liner 18L, and the diffusion barrier liner 16L
that are present in each opening 14 are coplanar with each other as
well as being coplanar with a topmost surface of the MOL dielectric
material layer 12.
[0039] As shown in FIG. 4, the reflow enhancement liner 18L located
in each opening 14 that is present in a dielectric-containing
substrate (i.e., the MOL dielectric material 12). The reflow
enhancement liner 18L is U-shape. By "U-shaped" it is meant a
material has a horizontal portion and two vertical portions
extending from opposite ends of the horizontal portion. The
diffusion barrier liner 16L that is present beneath the reflow
enhancement liner 18L is also U-shaped. In this embodiment,
metallization structure 20S is located on the horizontal portion of
the reflow enhancement liner 18L and the metallization structure
20S completely fills a volume located between the two vertical
portions of the reflow enhancement liner 18L.
[0040] Referring now to FIG. 5, there is illustrated the exemplary
semiconductor structure of FIG. 4 after forming a cap 24 on exposed
surfaces of the planarized structure. Cap 24 is formed on topmost
surfaces of each metallization structure 20S, each reflow
enhancement liner 18L, each diffusion barrier liner 16L and atop
the topmost surface of the MOL dielectric material layer 12.
[0041] In some embodiments of the present application, cap 24 is
composed of a dielectric capping material such as, for example,
SiC, Si.sub.3N.sub.4, SiO.sub.2, a carbon doped oxide, a nitrogen
and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof.
In other embodiments, cap 24 may be composed of a metal cap such
as, for example, CoWP. The cap 24 can be formed utilizing a
conventional deposition process such as, for example, chemical
vapor deposition, plasma enhanced chemical vapor deposition,
chemical solution deposition, evaporation, or atomic layer
deposition. The thickness of the cap 24 may vary depending on the
technique used to form the same as well as the material make-up of
the layer. Typically, the cap 24 has a thickness from 15 nm to 100
nm. Other thicknesses that are lesser than 15 nm, or greater 100 nm
may also be employed as the thickness of the cap 24.
[0042] Referring now to FIG. 6, there is illustrated another
exemplary semiconductor structure including at least one gate
cavity 31 surrounded by a dielectric spacer 33 and a middle-of-the
line (MOL) dielectric material layer 32. The exemplary
semiconductor structure also includes at least one semiconductor
fin 30. The at least one semiconductor fin 30 may include any
semiconductor material such as, for example, silicon. In this
embodiment, two gate cavities are shown by way of an example. In
such an embodiment, one of the gate cavities can be a region in
which a nFET device can be subsequently formed, and the other gate
cavity may be a region in which a pFET device region can be
subsequently formed. In the illustrated embodiment, each gate
cavity 31 is shown between two semiconductor fins 30.
[0043] In the exemplary semiconductor structure shown in FIG. 6,
each gate cavity 31 may be referred to as an opening. Each gate
cavity 31 may have a constant width, w1, and sidewall surfaces that
are perpendicular to the at least one semiconductor fin 30.
[0044] The exemplary semiconductor structure shown in FIG. 6 can be
formed by first providing a semiconductor substrate. The at least
one semiconductor fin 30 can then be formed by patterning an upper
semiconductor material portion of the semiconductor substrate. At
least one sacrificial gate structure (not shown) can then be formed
by depositing a sacrificial gate material and thereafter patterning
the sacrificial gate material. After formation of the at least one
sacrificial gate structure, dielectric spacers 33 can be formed on
exposed sidewall surfaces of the at least one sacrificial gate
structure utilizing a deposition process and etching. The
dielectric spacers 33 may be composed of any dielectric spacer
material such as, for example, silicon dioxide or silicon nitride.
Next, the MOL dielectric material layer 32 is formed. The MOL
dielectric material layer 32 of this embodiment may include one of
the dielectric materials mentioned above for the MOL dielectric
material layer 12 in the previous embodiment of the present
application. The MOL dielectric material layer 32 can be formed
utilizing one of the techniques described above in providing MOL
dielectric material layer 12. In this embodiment, MOL dielectric
material layer 32 has a topmost surface that is coplanar with a
topmost surface of the at least one sacrificial gate structure. The
at least one sacrificial gate structure is then removed by
utilizing an anisotropic etch so as to provide the gate cavities 31
shown in FIG. 6.
[0045] Referring now to FIG. 7, there is illustrated the exemplary
semiconductor structure of FIG. 8 after forming a gate dielectric
material 34 and work function metal 36 at least within each gate
cavity 31. The gate dielectric material 34 and the work function
metal 36 are continuous layers that are formed one atop the other.
Both the gate dielectric material 34 and the work function metal 36
include portions outside of, as well as within, each gate cavity
31.
[0046] The gate dielectric material 34 can be an oxide, nitride,
and/or oxynitride. In one example, the gate dielectric material 34
can be a high-k material having a dielectric constant greater than
silicon dioxide. Exemplary high-k dielectrics include, but are not
limited to, HfO.sub.2, ZrO.sub.2, La.sub.2O.sub.3, Al.sub.2O.sub.3,
TiO.sub.2, SrTiO.sub.3, LaAlO.sub.3, Y.sub.2O.sub.3,
HfO.sub.xN.sub.y, ZrO.sub.xN.sub.y, La.sub.2O.sub.xN.sub.y,
Al.sub.2O.sub.xN.sub.y, TiO.sub.XN.sub.y, SrTiO.sub.xN.sub.y,
LaAlO.sub.xN.sub.y, Y.sub.2O.sub.xN.sub.y, SiON, SiN.sub.x, a
silicate thereof, and an alloy thereof. Each value of x is
independently from 0.5 to 3 and each value of y is independently
from 0 to 2. In some embodiments, a multilayered gate dielectric
structure comprising different gate dielectric materials, e.g.,
silicon dioxide, and a high-k gate dielectric can be formed and
used as the gate dielectric material 34.
[0047] The gate dielectric material 34 can be formed by any
deposition process including, for example, chemical vapor
deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), physical vapor deposition (PVD), sputtering, or atomic
layer deposition. In one embodiment of the present application, the
gate dielectric material 34 can have a thickness in a range from 1
nm to 10 nm. Other thicknesses that are lesser than, or greater
than, the aforementioned thickness range can also be employed for
the gate dielectric material 34.
[0048] The work function metal 36 may be composed of, for example,
aluminum, lanthanum oxide, magnesium oxide, strontium titanate,
tantalum carbide, titanium nitride, and strontium oxide. The work
function metal 36 may have a thickness ranging from 0.5 nm to 50
nm, though greater and lesser thickness are explicitly
contemplated. The combined thickness of the gate dielectric
material 34 and the work function metal 36 is insufficient to fill
the entirety of the gate cavities 31. The work function metal 36
may be formed by any suitable deposition technique, such as, but
not limited to, atomic layer deposition (ALD), chemical vapor
deposition (CVD), physical vapor deposition (PVD), molecular beam
deposition (MBD), pulsed laser deposition (PLD), or liquid source
misted chemical deposition (LSMCD), sputtering, or plating.
[0049] Referring now to FIG. 8, there is illustrated the exemplary
semiconductor structure of FIG. 7 after forming a reflow
enhancement layer 38 on the work function metal 36. The flow
enhancement layer 38 of this embodiment is a continuous layer.
[0050] The reflow enhancement layer 38 includes any metal or metal
alloy that facilities in the movement (i.e., flow) of another
deposited metal or metal alloy that differs in composition from the
reflow enhancement layer during a subsequently performed reflow
anneal process. Examples of metals or metal alloys that may be
employed as the reflow enhancement layer 38 include ruthenium,
iridium, a tantalum-iridium alloy, a niobium-ruthenium alloy and a
niobium-iridium alloy. In one embodiment and when a layer of cobalt
is to be subsequently formed and reflowed, the reflow enhancement
layer 38 is composed of ruthenium or iridium.
[0051] The thickness of reflow enhancement layer 38 may vary
depending on the material of the reflow enhancement layer 38 as
well as the technique used in forming the same. Typically, the
reflow enhancement layer 38 has a thickness from 2 nm to 80 nm. The
reflow enhancement layer 28 can be formed by a conventional
deposition process including, for example, CVD, PECVD, ALD, or
PVD.
[0052] It is noted that the total thickness of the gate dielectric
material 34, the work function metal 36 and the reflow enhancement
layer 38 is insufficient to completely fill the total volume of
each of the gate cavities 31. Thus, a portion (i.e., a volume) of
each gate cavity 31 is available for further processing.
[0053] Referring now to FIG. 9, there is illustrated the exemplary
semiconductor structure of FIG. 8 after depositing a layer of a
contact metal or metal alloy and performing a reflow anneal. In
FIG. 9, element 40 denotes the deposited and reflowed layer of
contact metal or metal alloy. As such shown, the deposited and
reflowed layer of contact metal or metal alloy 40 completely fills
in the remaining portion (i.e., volume) of each gate cavity 31; an
overburden portion of the deposited and reflowed layer of contact
metal or metal alloy 40 forms outside each gate cavity 31 and above
the topmost surface of the MOL dielectric material layer 32.
[0054] The deposited and reflowed layer of contact metal or metal
alloy 40 is formed by first depositing a contact metal or metal
alloy directly on the reflow enhancement layer 38 and then
performing a reflow anneal. The contact metal or metal alloy that
may be employed in the present application includes cobalt (Co),
platinum, (Pt), and/or nickel (Ni). The contact metal or metal
alloy can be formed by a deposition process including PVD, chemical
vapor deposition (CVD), plasma enhanced chemical vapor deposition
(PECVD), sputtering, chemical solution deposition or plating.
[0055] Next, a reflow anneal is performed. The reflow anneal of
this embodiment of the present application is the same as described
in the previous embodiment of the present application.
[0056] Referring now to FIG. 10, there is illustrated the exemplary
semiconductor structure of FIG. 9 after performing a planarization
process, recessing and formation of a cap 42. The planarization
process of this embodiment of the present application includes
chemical mechanical polishing and/or grinding. The planarization
process removes all material (i.e., portions of elements 40, 38, 36
and 34) that is outside each gate cavity 31 and atop the topmost
surface of the MOL dielectric material 32. Portions of elements 40,
38, 36 and 34 remain in each of the gate cavities 31. Next, a
recess etch is performed to remove elements 40, 38, 36 and 34 from
an upper portion of each gate cavity 31. Portions of elements 40,
38, 36 and 34 remain in the lower portion of each gate cavity 31.
The remaining portion of the deposited and reflowed layer of
contact metal or metal alloy 40 can now be referred to as a
metallization structure 40S. The remaining portion of the reflow
enhancement layer 38 can now be referred to a reflow enhancement
liner 38L. The remaining portion of the work function metal 36 can
now be referred to as a work function portion 36L. The remaining
portion of the gate dielectric material can be referred to as a
gate dielectric portion 34L. As is shown, the topmost surface of
each of the metallization structure 40S, the reflow enhancement
liner 38L, the work function portion 36L and the gate dielectric
portion 34L are coplanar with each other.
[0057] As shown in FIG. 10, the reflow enhancement liner 38L is
located in a lower portion of each gate cavity 31 that is present
in a dielectric-containing substrate (i.e., the dielectric spacer
33). The reflow enhancement liner 38L is U-shape. The gate
dielectric portion 34L and the work function metal portion 36L that
are present beneath the reflow enhancement liner 38L are also
U-shaped. In this embodiment, metallization structure 40S is
located on the horizontal portion of the reflow enhancement liner
38L and the metallization structure 40S completely fills a volume
located between the two vertical portions of the reflow enhancement
liner 38L.
[0058] Cap 42 is then formed in the upper portion of each gate
cavity 31. Cap 42 of this embodiment of the present application may
include one of the materials mentioned above for cap 24. Cap 42 can
be formed utilizing a deposition process as described above for
providing cap 24. A planarization process may be used to complete
the formation of cap 42.
[0059] While the present application has been particularly shown
and described with respect to preferred embodiments thereof, it
will be understood by those skilled in the art that the foregoing
and other changes in forms and details may be made without
departing from the spirit and scope of the present application. It
is therefore intended that the present application not be limited
to the exact forms and details described and illustrated, but fall
within the scope of the appended claims.
* * * * *