U.S. patent application number 15/191554 was filed with the patent office on 2017-11-23 for circuit board and method for making the same.
The applicant listed for this patent is FuKui Precision Component (Shenzhen) Co., Ltd., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Zhen Ding Technology Co., Ltd.. Invention is credited to CHENG-JIA LI, YAN-LU LI, MEI YANG.
Application Number | 20170339795 15/191554 |
Document ID | / |
Family ID | 60329609 |
Filed Date | 2017-11-23 |
United States Patent
Application |
20170339795 |
Kind Code |
A1 |
LI; YAN-LU ; et al. |
November 23, 2017 |
CIRCUIT BOARD AND METHOD FOR MAKING THE SAME
Abstract
A method of manufacture of a circuit board without annular
through-hole rings and thus allowing a higher component density
includes a base layer, a first wire pattern layer, and a second
wire pattern layer on both sides of the base layer. A portion of
the base layer not covered by the first wire pattern layer defines
at least one first hole. The circuit board further includes a wire
layer. The wire layer includes at least a first portion and a
second portion connecting to the first portion. The first portion
is filled in the first hole. The second portion is formed on the
first portion extending away from the base layer. A diameter of the
second portion is less than an aperture diameter of the first hole.
The wire layer is electrically conductive between the first wire
pattern layer and the second wire pattern layer through the first
portion.
Inventors: |
LI; YAN-LU; (Qinhuangdao,
CN) ; YANG; MEI; (Qinhuangdao, CN) ; LI;
CHENG-JIA; (Qinhuangdao, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
FuKui Precision Component (Shenzhen) Co., Ltd.
Zhen Ding Technology Co., Ltd. |
Qinhuangdao
Shenzhen
Tayuan |
|
CN
CN
TW |
|
|
Family ID: |
60329609 |
Appl. No.: |
15/191554 |
Filed: |
June 24, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H05K 3/427 20130101;
H05K 2201/09845 20130101; H05K 3/4038 20130101; H05K 3/02 20130101;
H05K 2201/0367 20130101; H05K 3/0011 20130101; H05K 1/0298
20130101; H05K 1/09 20130101; H05K 3/0073 20130101; H05K 2203/0353
20130101; H05K 1/115 20130101; H05K 3/4644 20130101; H05K 2201/098
20130101; H05K 2201/095 20130101; H05K 3/108 20130101 |
International
Class: |
H05K 3/46 20060101
H05K003/46; H05K 3/40 20060101 H05K003/40; H05K 1/09 20060101
H05K001/09; H05K 1/02 20060101 H05K001/02; H05K 1/11 20060101
H05K001/11; H05K 3/00 20060101 H05K003/00; H05K 3/02 20060101
H05K003/02 |
Foreign Application Data
Date |
Code |
Application Number |
May 20, 2016 |
CN |
201610340047.1 |
Claims
1. A method of manufacturing a circuit board, comprising: providing
a substrate with double-side copper layers, wherein the substrate
comprises a base layer, a first copper layer and a second copper
layer, the first copper layer and the second copper layer are
formed on opposite surfaces of the base layer; opening a through
hole on the substrate, wherein the through hole comprises a first
hole and a second hole communicating with the first hole, the first
hole penetrates through the base layer and the second hole
penetrates through the first copper layer; forming a wire layer by
copper plating, wherein the wire layer comprises a first portion
filled in the through hole and a second portion formed on the first
portion extending in a direction facing away from the base layer,
the wire layer is electrically conductive between the first copper
layer and the second copper layer through the first portion;
wherein the manufacturing method of forming the wire layer is
further comprising the steps of: applying a first photosensitive
film and a second photosensitive film on the opposite surfaces of
the substrate, the first photosensitive film covers the first
copper layer and the open end of the through hole, the second
photosensitive film covers the second copper layer. forming a mask
pattern on the first and second photosensitive films after exposing
and developing the first and second photosensitive films, the mask
pattern comprises an opening which corresponds to the open end of
the through hole, the aperture diameter of the opening is less than
the aperture diameter of the through hole; forming a wire layer
corresponding to the mask pattern by copper plating, the second
portion is filled in the opening; and removing the first and second
photosensitive films; and removing the first copper layer and the
second copper layer which are not covered with the wire layer by
using a quick etching treatment so as to respectively form a first
wire pattern layer and a second wire pattern layer, and the first
portion which is flush with the first copper layer and not cover
with the second portion.
2. (canceled)
3. The method of manufacturing the circuit board of claim 1,
wherein the through hole is a straight hole.
4. The method of manufacturing the circuit board of claim 1,
wherein the first hole is a stepped hole, the first hole comprises
a wide portion and a narrow portion communicating with the wide
portion, the narrow portion is adjacent to a surface of the base
layer with the second copper layer.
5. The method of manufacturing the circuit board of claim 4,
wherein a depth of the wide portion is equal to one half or less of
the thickness of the base layer.
6. The method of manufacturing the circuit board of claim 1,
wherein the step of removing the first and second copper layers
which are not covered with the wire layer is further to remove the
first portion filled in the wide portion and not covered with the
second portion.
7. The method of manufacturing the circuit board of claim 2,
wherein the wire layer is formed on a surface of the first wire
pattern layer facing away from the base layer and a surface of the
second wire pattern layer facing away from the base layer.
8. The method of manufacturing a circuit board of claim 1, wherein
the method further comprises a copper reduction treatment process
prior to open the through hole, so that the thicknesses of the
first copper layer and the second copper layer are uniformly
reduced.
9. A method of manufacturing a circuit board, comprising: providing
a substrate with double-side copper layers, wherein the substrate
comprises a base layer, a first copper layer and a second copper
layer, the first copper layer and the second copper layer are
formed on opposite surfaces of the base layer; opening a through
hole on the substrate, wherein the through hole comprises a first
hole and a second hole communicating with the first hole, the first
hole penetrates through the base layer and the second hole
penetrates through the first copper layer; applying a plating layer
by copper plating the substrate, wherein the plating layer
comprises a first portion filled in the through hole, the plating
layer combines with the first copper layer and the second copper
layer to respectively form a first stacking copper layer and a
second stacking copper layer on opposite surfaces of the base
layer; forming a wire layer by copper plating, wherein the wire
layer comprises the plated copper and the first portion, and
further comprises a second portion connecting to the first portion,
the diameter of the second portion is less than the diameter of the
first portion, and the wire layer is electrically conductive
between the first copper layer and the second copper layer through
the first portion; and removing the first stacking copper layer and
the second stacking copper layer which are not covered with the
wire layer by using a quick etching treatment so as to respectively
form a first wire pattern layer and a second wire pattern layer,
and removing the first portion which is flush with the first copper
layer and not covered with the second portion.
10. The method of manufacturing a circuit board of claim 9, wherein
the manufacturing method of forming the wire layer is further
comprising the steps of: applying a first photosensitive film and a
second photosensitive film on opposite surfaces of the substrate
after applying the plating layer; forming a mask pattern on the
first and second photosensitive films after exposing and developing
the first and second photosensitive films, wherein the mask pattern
comprises an opening which corresponds to the open end of the
through hole, the diameter of the opening is less than the diameter
of the through hole; forming the wire layer corresponding to the
mask pattern by copper plating, wherein the wire layer is
constituted by the plated copper and the first portion, the wire
layer further comprises a second portion filled in the opening; and
removing the first and second photosensitive films.
11. The circuit board manufacturing method of claim 9, wherein the
through hole is a straight hole.
12. The method of manufacturing a circuit board of claim 9, wherein
the first hole is a stepped hole, the first hole comprises a wide
portion and a narrow portion communicating with the wide portion,
the wide portion is adjacent to a surface of the base layer with
the first copper layer, and the narrow portion is adjacent to
another surface of the base layer with the second copper layer.
13. The method of manufacturing a circuit board of claim 12,
wherein the depth of the wide portion is equal to one half or less
of the thickness of the base layer.
14. The circuit board manufacturing method of claim 13, wherein the
step of removing the first stacking copper layer and the second
stacking copper layer which are not covered with the wire layer, is
further to remove the first portion which is filled in the wide
portion and not covered with the second portion.
15. The method of manufacturing a circuit board of claim 10,
wherein the mask pattern is also formed on the second
photosensitive film and the first photosensitive film except for
the opening, and the wire layer is further formed on a surface of
the first wire pattern layer facing away from the base layer and a
surface of the second wire pattern layer facing away from the base
layer.
16. The circuit board manufacturing method of claim 9, wherein the
method further comprises a copper reduction treatment process prior
to open the through hole, the thicknesses of the first stacking
copper layer and the second stacking copper layer are reduced by a
copper reduction process.
17. A circuit board comprising a base layer, a first wire pattern
layer and a second wire pattern layer formed on opposite surfaces
of the base layer, the base layer comprising a first hole
penetrating through the base layer, the first hole is formed on the
base layer where is not covered with the first wire pattern layer;
a wire layer comprising a first portion and a second portion
connecting to the first portion, the first portion filled in the
first hole, the second portion formed on the first portion
extending in a direction facing away from the base layer, wherein
the diameter of the second portion is less than the aperture
diameter of the first hole; wherein the wire layer is electrically
conductive between the first wire pattern layer and the second wire
pattern layer through the first portion.
18. The circuit board of claim 17, wherein the first hole is a
straight hole.
19. The circuit board of claim 17, wherein the first hole is a
stepped hole, the first hole comprises a wide portion and a narrow
portion communicating with the wide portion, the wide portion is
adjacent to a surface of the base layer with the first copper
layer, and the narrow portion is adjacent to another surface of the
base layer with the second copper layer.
20. The circuit board of claim 19, wherein a depth of the wide
portion is equal to one half or less of the thickness of the base
layer.
Description
FIELD
[0001] The subject matter herein generally relates to printed
circuit boards and their manufacture.
BACKGROUND
[0002] Flexible printed circuit boards generally need a highly
complex, highly precise, and high-density wiring layout. However,
the annular rings around conductive holes of the flexible printed
circuit board reduce the utilization areas of the flexible printed
circuit board and prevent high-density circuit layouts.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Implementations of the present technology will now be
described, by way of example only, with reference to the attached
figures.
[0004] FIG. 1 shows a flowchart of a method for manufacturing a
circuit board according to a first exemplary embodiment.
[0005] FIG. 2 shows a cross sectional view of a substrate used in
the method of manufacturing a circuit board of FIG. 1.
[0006] FIG. 3 shows a cross sectional view of the substrate in FIG.
2 after thinning the first and second copper layers by a copper
reduction treatment process.
[0007] FIG. 4 shows a cross sectional view of the substrate in FIG.
3 after opening a through hole.
[0008] FIG. 5 shows a cross sectional view of the substrate in FIG.
4 after applying a first photosensitive film and a second
photosensitive film on opposite surfaces of the substrate.
[0009] FIG. 6 shows a cross sectional view of the substrate in FIG.
5 after forming a mask pattern on the first and second
photosensitive films by exposure and development.
[0010] FIG. 7 shows a cross sectional view of the substrate in FIG.
6 after forming a wire layer by copper plating.
[0011] FIG. 8 shows a cross sectional view of the substrate in FIG.
7 after removing the first and second photosensitive films.
[0012] FIG. 9 shows a cross sectional view of the substrate in FIG.
8 after removing the first and second copper layers which are not
covered with the wire layer to form the first and second wire
pattern layers by using a quick etching treatment.
[0013] FIG. 10 shows a flowchart of a method for manufacturing a
circuit board according to a second exemplary embodiment
[0014] FIG. 11 shows a cross sectional view of the substrate in
FIG. 4 after applying a plating layer to form the first and second
stacking copper layers according to a second exemplary
embodiment.
[0015] FIG. 12 shows a cross sectional view of the substrate in
FIG. 11 after thinning the thicknesses of the first and second
stacking copper layers by using a copper reduction treatment
process.
[0016] FIG. 13 shows a cross sectional view of the substrate in
FIG. 12 after applying the first and second photosensitive films on
the first and second stacking copper layers.
[0017] FIG. 14 shows a cross sectional view of the substrate in
FIG. 13 after forming a mask pattern on the first and second
photosensitive films by exposure and development.
[0018] FIG. 15 shows a cross sectional view of the substrate in
FIG. 14 after forming a wire layer by copper plating.
[0019] FIG. 16 shows a cross sectional view of the substrate in
FIG. 15 after removing the first and second photosensitive
films.
[0020] FIG. 17 shows a cross sectional view of the substrate in
FIG. 16 after removing the first and second stacking copper layers
which are not covered with the wire layer, by using a quick etching
treatment.
[0021] FIG. 18 shows a cross sectional view of a substrate after
opening a stepped hole according to a third and fourth exemplary
embodiments.
[0022] FIG. 19 shows a cross sectional view of a circuit board
according to the third exemplary embodiment.
[0023] FIG. 20 shows a cross sectional view of a circuit board
according to the fourth exemplary embodiment.
[0024] FIG. 21 shows a cross sectional view of a circuit board
according to a fifth exemplary embodiment.
[0025] FIG. 22 shows a cross sectional view of a circuit board
according to a sixth exemplary embodiment.
DETAILED DESCRIPTION
[0026] It will be appreciated that for simplicity and clarity of
illustration, where appropriate, reference numerals have been
repeated among the different figures to indicate corresponding or
analogous elements. In addition, numerous specific details are set
forth in order to provide a thorough understanding of the
embodiments described herein. However, it will be understood by
those of ordinary skill in the art that the embodiments described
herein may be practiced without these specific details. In other
instances, methods, procedures, and components have not been
described in detail so as not to obscure the related relevant
feature being described. Also, the description is not to be
considered as limiting the scope of the embodiments described
herein. The drawings are not necessarily to scale and the
proportions of certain parts may be exaggerated to better
illustrate details and features of the present disclosure.
[0027] The term "comprising," when utilized, means "including, but
not necessarily limited to"; it specifically indicates open-ended
inclusion or membership in the so-described combination, group,
series, and the like.
[0028] FIG. 1 shows a flowchart for a method of manufacturing a
circuit board 100 in accordance with a first example embodiment.
The first example method 1000 is provided by way of example, as
there are a variety of ways to carry out the method. The first
method 1000 described below can be carried out using the
configurations illustrated in FIGS. 2 to 9, for example, and
various elements of these figures are referenced in explaining the
first example method 1000. Each block shown in FIG. 1 represents
one or more processes, methods, or subroutines, carried out in the
first example method 1000. Furthermore, the illustrated order of
blocks is illustrative only and the order of the blocks can change.
Additional blocks can be added or fewer blocks may be utilized,
without departing from this disclosure. The first example method
1000 can begin at block 1002.
[0029] The circuit board 100 can be a high-density circuit board
(HDI board), rigid-flex board, flexible printed circuit board, or
IC substrate.
[0030] At block 1002, providing a substrate 10 with double-side
copper layers as a base board. The substrate 10 can be a
double-side board.
[0031] FIG. 2 illustrates the substrate 10 with double-side copper
layers. The substrate 10 includes a base layer 11, a first copper
layer 12, and a second copper layer 13 which are formed on the
opposite surfaces of the base layer 11.
[0032] In at least one embodiment, the base layer 11 is a flexible
resin, which can be made of polyimide (PI), polyethylene
terephthalate (PET), or Polyethylene Naphthalate (PEN).
[0033] At block 1004, thinning the first and second copper layers
of the substrate 10 by a copper reduction treatment process.
[0034] FIG. 3 illustrates the substrate 10 having a thinned first
copper layer 12 and a thinned second copper layer 13. Specifically,
the first copper layer 12 and the second copper layer 13 are etched
by chemical solutions, so that the thicknesses of the first copper
layer 12 and the second copper layer 13 are uniformly reduced.
[0035] At block 1006, opening at least one through hole 102 in the
substrate 10.
[0036] FIG. 4 illustrates the substrate 10 with a through hole 102.
Notwithstanding the name, the through hole 102 is a blind hole
which only penetrates through the first copper layer 12 and the
base layer 11. In at least one embodiment, the through hole 102 is
straight. The through hole 102 includes a first hole 104 and a
second hole 106 communicating with the first hole 104. The first
hole 104 penetrates through the base layer 11 and the second hole
106 penetrates through the first copper layer 12. In at least one
embodiment, both of the first hole 104 and the second hole 106 are
straight. The through hole 102 can be formed by laser processes. In
at least one embodiment, the aperture diameter of the through hole
102 is equal to or greater than 50 .mu.m. In other embodiments, an
aperture diameter of the through hole 102 can be according to
specific needs
[0037] At block 1008, applying a first photosensitive film and a
second photosensitive film on opposite surfaces of the substrate 10
with the through hole 102.
[0038] FIG. 5 illustrates a first photosensitive film 21 and a
second photo sensitive film 23 applied to opposite surfaces of the
substrate 10 with the through hole 102. The first photosensitive
film 21 covers the first copper layer 12 and the open end of the
through hole 102. The second photosensitive film 23 covers the
second copper layer 13.
[0039] A block 1010, forming a mask pattern 210 on the first and
second photosensitive films 21 and 23 by exposure and
development.
[0040] FIG. 6 illustrates a mask pattern 210 formed on the first
photosensitive film 21 and the second photosensitive film 23 after
exposing and developing the first photosensitive film 21 and the
second photosensitive film 23. The mask pattern 210 includes an
opening 211 which corresponds to the open end of the through hole
102.
[0041] In at least one embodiment, the mask pattern 210 is also
formed on the second photosensitive film 23 and the first
photosensitive film 21 except for the opening 211.
[0042] In at least one embodiment, a central axial line of the
opening 211 coincides with a central axial line of the through hole
102. The aperture diameter of the opening 211 is equal to one half
of or more than one half of the aperture diameter of the through
hole 102, but less than the aperture diameter of the through hole
102.
[0043] A block 1012, forming a wire layer 31 corresponding to the
mask pattern 210, by copper plating.
[0044] FIG. 7 illustrates a wire layer 31 corresponding to the mask
pattern 210 formed by copper plating. The wire layer 31 includes at
least a first portion 311 filled with the plated copper in the
through hole 102, and a second portion 312 filled with plated
copper in the opening 211. The second portion 312 connects to the
first portion 311. In at least one embodiment, the wire layer 31 is
also formed on a surface of the first copper layer 12 facing away
from the base layer 11 and a surface of the second copper layer 13
facing away from the base layer 11. The wire layer 31 is
electrically conductive between the first copper layer 12 and the
second copper layer 13 through the first portion 311.
[0045] A block 1014, removing the first and second photosensitive
films to expose a portion of the first and second copper layers
which are not covered with the wire layer 31.
[0046] FIG. 8 illustrates that the first photosensitive film 21 and
the second photosensitive film 23 are removed to expose the wire
layer 31 and a portion of the first copper layer 12 and the second
copper layer 13 which are not covered with the wire layer 31.
[0047] At block 1016, removing the first and second copper layers
which are not covered with the wire layer 31 so as to respectively
form a first wire pattern layer 120 and a second wire pattern layer
130.
[0048] FIG. 9 illustrates the first copper layer 12 and the second
copper layer 13 which are not covered with the wire layer 31 being
removed by using a quick etching treatment. A portion of the first
portion 311 which is flush with the first copper layer 12 and not
covered by the second portion 312 is also removed by using the
quick etching treatment. Thereby, the first copper layer 12 and the
second copper layer 13 after the quick etching treatment are
respectively formed as a first wire pattern layer 120 and a second
wire pattern layer 130 corresponding to the wire layer 31. In
addition, the first portion 311 is flush with the base layer 11 to
obtain the circuit board 100 after the quick etching treatment. In
at least one embodiment, the quick etching treatment is an
anisotropic etching process which has an etching rate in the
vertical direction much higher than an etching rate in the
horizontal direction. The vertical direction is substantially
normal to the base layer 11.
[0049] The method of manufacturing the circuit board 100 can omit
the copper reduction treatment process in block 1004 according to
specific needs.
[0050] Referring to FIG. 9, the circuit board 100 made by the
example method 1000 described in the above embodiments includes a
base layer 11, a first wire pattern layer 120, and a second wire
pattern layer 130. The first wire pattern layer 120 and the second
wire pattern layer 130 are formed on opposite surfaces of the base
layer 11. A portion of the base layer 11 which is not covered by
the first wire pattern layer 120 defines at least one first hole
104. The circuit board 100 further includes a wire layer 31. The
wire layer 31 includes at least a first portion 311 and a second
portion 312 connecting to the first portion. The first portion 311
is filled in the first hole 104. The second portion 312 is formed
on the first portion 311 extending in a direction facing away from
the base layer 11. A diameter of the second portion 312 is equal to
one half of or greater than one half of a diameter of the first
portion 311, the diameter of the second portion 312 being less than
an aperture diameter of the first hole 104. The wire layer 31 is
electrically conductive between the first wire pattern layer 120
and the second wire pattern layer 130 through the first portion
311.
[0051] FIG. 10 shows a flowchart for a method of manufacturing a
circuit board 100 in accordance with a second example embodiment.
The second example method 2000 is provided by way of example, as
there are a variety of ways to carry out the method. The second
method 2000 described below can be carried out using the
configurations illustrated in FIGS. 2 and 4 and 11 to 17, for
example, and various elements of these figures are referenced in
explaining the second example method 2000. Each block shown in FIG.
10 represents one or more processes, methods, or subroutines,
carried out in the second example method 2000. Furthermore, the
illustrated order of blocks is illustrative only and the order of
the blocks can change. Additional blocks can be added or fewer
blocks may be utilized, without departing from this disclosure. The
second example method 2000 can begin at block 2002.
[0052] The circuit board 100 can be a high-density circuit board
(HDI board), rigid-flex board, flexible printed circuit board, or
IC substrate.
[0053] At block 2002, providing a substrate 10 with double-side
copper layers as a base board. The substrate 10 can be a
double-side board.
[0054] FIG. 2 illustrates the substrate 10 with double-side copper
layers. The substrate 10 includes a base layer 11, a first copper
layer 12, and a second copper layer 13 formed on opposite surfaces
of the base layer 11.
[0055] In at least one embodiment, the base layer 11 is a flexible
resin, made of polyimide (PI), polyethylene terephthalate (PET), or
Polyethylene Naphthalate (PEN).
[0056] At block 2004, opening at least one through hole 102 on the
substrate 10.
[0057] FIG. 4 illustrates the substrate 10 with a through hole 102.
The through hole 102 is a blind hole which penetrates through the
first copper layer 12 and the base layer 11. The through hole 102
includes a first hole 104 and a second hole 106 communicating with
the first hole 104. The first hole 104 penetrates through the base
layer 11 and the second hole 106 penetrates through the first
copper layer 12. The through hole 102 can be formed by laser
processes. In at least one embodiment, the aperture diameter of the
through hole 102 is equal to or greater than 50 .mu.m. In other
embodiments, the aperture diameter of the through hole 102 can be
set according to specific needs
[0058] At block 2006, applying a plating layer 30 on the substrate
10.
[0059] FIG. 11 illustrates that a plating layer 30 is formed on the
substrate 10 by plating the substrate 10. The plating layer 30
includes at least a first portion 311 filled in the through hole
102. In at least one embodiment, the plating layer 30 further
covers the first copper layer 12 and the second copper layer 13.
The plating layer 30 combines with the first copper layer 12 to
constitute a first stacking copper layer 14. In addition, the
plating layer 30 combines with the second copper layer 13 to
constitute a second stacking copper layer 15.
[0060] At block 2008, thinning the thicknesses of the first
stacking copper layer 14 and the second stacking copper layer 15 by
a copper reduction treatment process.
[0061] FIG. 12 illustrates that the thicknesses of the first
stacking copper layer 14 and the second stacking copper layer 15
are both uniformly reduced after the copper reduction treatment
process.
[0062] At block 2010, applying a first photosensitive film and a
second photosensitive film on opposite surfaces of the substrate 10
with a plating layer 30.
[0063] FIG. 13 illustrates that a first photosensitive film 21 and
a second photo sensitive film 23 are applied on opposite surfaces
of the substrate 10 so as to cover at least the plating layer
30.
[0064] At block 2012, forming a mask pattern 210 on the first and
second photosensitive films by exposure and development.
[0065] FIG. 14 illustrates that a mask pattern 210 is formed on the
first photosensitive film 21 and the second photosensitive film 23
after exposing and developing the first photosensitive film 21 and
the second photosensitive film 23. The mask pattern 210 includes at
least an opening 211 corresponding to the through hole 102.
[0066] In at least one embodiment, a central axial line of the
opening 211 coincides with a central axial line of the through hole
102. The aperture diameter of the opening 211 is equal to one half
of or greater than one half of the aperture diameter of the through
hole 102, but less than the aperture diameter of the through hole
102.
[0067] In at least one embodiment, the mask pattern 210 is also
formed on the second photosensitive film 23 and the first
photosensitive film 21 except for the opening 211.
[0068] At block 2014, forming a wire layer 31 corresponding to the
mask pattern 210 by copper plating.
[0069] FIG. 15 illustrates a wire layer 31 corresponding to the
mask pattern 210 formed by copper plating. The wire layer 31
includes at least a first portion 311 filled with the plated copper
in the through hole 102, and a second portion 312 filled with
plated copper in the opening 211. The second portion 312 connects
to the first portion 311. In at least one embodiment, the wire
layer 31 is further formed on a surface of the first copper layer
12 facing away from the base layer 11 and a surface of the second
copper layer 13 facing away from the base layer 11. The wire layer
31 is electrically conductive between the first copper layer 12 and
the second copper layer 13 through the first portion 311.
[0070] At block 2016, removing the first and second photosensitive
films to expose a portion of the first and second copper layers 12
and 13 which are not covered with the wire layer 31.
[0071] FIG. 16 illustrates the first photosensitive film 21 and the
second photosensitive film 23 removed so as to expose the wire
layer 31, and also to expose a portion of the first copper layer 12
and the second copper layer 13 which are not covered with the wire
layer 31.
[0072] At block 2018, removing the first stacking copper layer 14
and the second stacking copper layer 15 which are not covered with
the wire layer 31 so as to form a first wire pattern layer 120 and
a second wire pattern layer 130.
[0073] FIG. 17 illustrates that the parts of the first stacking
copper layer 14 and the second stacking copper layer 15 which are
not covered with the wire layer 31 are removed using a quick
etching treatment. After the quick etching treatment, the first
stacking copper layer 14 and the second stacking copper layer 15
corresponding to the wire layer 31 respectively become a first wire
pattern layer 120 and a second wire pattern layer 130. In addition,
a portion of the first portion 311 is flush with the base layer 11
so as to obtain the circuit board 100. In at least one embodiment,
the quick etching treatment is an anisotropic etching process with
an etching rate in the vertical direction much higher than an
etching rate in the horizontal direction. The vertical direction is
substantially normal to the base layer 11.
[0074] The method of manufacturing the circuit board 100 in the
second embodiment can omit the copper reduction treatment process
according to specific needs.
[0075] FIG. 18 and FIG. 19 show a method of manufacturing a circuit
board 100 in a third exemplary embodiment. The difference between
the first and third embodiments is that the first hole 104 at block
1006 is a stepped hole. The first hole 104 includes a wide portion
107 and a narrow portion 108 in the third exemplary embodiment. The
wide portion 107 communicates with the second hole 106 and
constitutes a straight hole together with the second hole 106. The
narrow portion 108 communicates with the wide portion 107, and the
aperture diameter of the narrow portion 108 is smaller than the
aperture diameter of the wide portion 107. The wide portion 107 is
adjacent to a surface of the base layer 11 with the first copper
layer 12. The narrow portion 108 is adjacent to a surface of the
base layer 11 with the second copper layer 13.
[0076] In at least one embodiment, a depth of the wide portion 107
is equal to one half or less of the thickness of the base layer
11.
[0077] FIG. 18 and FIG. 20 show a method of manufacturing a circuit
board 100 in a fourth exemplary embodiment. The difference between
the second and fourth embodiments is that the first hole 104 at
block 2004 is a stepped hole. The first hole 104 includes a wide
portion 107 and a narrow portion 108 in the fourth exemplary
embodiment. The wide portion 107 communicates with the second hole
106 and constitutes a straight hole together with the second hole
106. The narrow portion 108 communicates with the wide portion 107,
and the aperture diameter of the narrow portion 108 is smaller than
the aperture diameter of the wide portion 107.
[0078] FIG. 21 shows a method of manufacturing a circuit board 100
in a fifth exemplary embodiment. The difference between the third
and fifth embodiments is that the first portion 311 filled in the
wide portion 107 and not covered by the second portion 312 is
etched by using the quick etching treatment described at block
1016.
[0079] FIG. 22 shows a method of manufacturing a circuit board 100
in a sixth exemplary embodiment. The difference between the fourth
and sixth embodiments is that the first portion 311 filled in the
wide portion 107 and not covered by the second portion 312 is
etched by using the quick etching treatment described at block
2018.
[0080] In these methods of manufacturing a flexible circuit board
100, filling and plating techniques are used to create electrical
conductivity between the first wire pattern layer 120 and the
second wire pattern layer 130, by infilling the first portion 311
and the second portion 312 in the through hole 102. In addition,
the opening 211 corresponding to the through hole 102 has an
aperture diameter which is less than the aperture diameter of the
through hole 102 after exposing and developing processes, so that
the diameter of the second portion 312 is less than the aperture
diameter of the first hole 104 after copper plating. This avoids an
annular ring occupying the usage area of the flexible circuit board
and increases the layout density of the flexible circuit board. A
high-density fine line production can be achieved when the second
portion 312 and the first portion 311 are electrically conductive.
The first holes 104 being stepped holes and the aperture diameter
of the wide portion 107 being greater than the aperture diameter of
the narrow portion 108 allows the wide portion 107 to have
positional tolerance to shift within the exposing and developing
processes. Therefore, a loss rate due to position shifting within
the exposing and developing processes is reduced and a yield rate
of manufacturing the flexible circuit board is increased.
[0081] The embodiments shown and described above are only examples.
Many details are often found in the art such as the other features
of manufacturing a circuit board. Therefore, many such details are
neither shown nor described. Even though numerous characteristics
and advantages of the present technology have been set forth in the
foregoing description, together with details of the structure and
function of the present disclosure, the disclosure is illustrative
only, and changes may be made in the detail, especially in matters
of shape, size, and arrangement of the parts within the principles
of the present disclosure, up to and including the full extent
established by the broad general meaning of the terms used in the
claims. It will therefore be appreciated that the embodiments
described above may be modified within the scope of the claims.
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