U.S. patent application number 15/057439 was filed with the patent office on 2017-09-07 for co-integration of silicon and silicon-germanium channels for nanosheet devices.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Michael A. Guillorn, Isaac Lauer, Nicolas J. Loubet.
Application Number | 20170256610 15/057439 |
Document ID | / |
Family ID | 59702248 |
Filed Date | 2017-09-07 |
United States Patent
Application |
20170256610 |
Kind Code |
A1 |
Guillorn; Michael A. ; et
al. |
September 7, 2017 |
CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR
NANOSHEET DEVICES
Abstract
Nanosheet semiconductor devices and methods of forming the same
include forming a first nanosheet stack in a first device region
with layers of a first channel material and layers of a sacrificial
material. A second nanosheet stack is formed in a second device
region with layers of a second channel material, layers of the
sacrificial material, and a liner formed around the layers of the
second channel material. The sacrificial material is etched away,
but the liner protects the second channel material from the etch.
Gate stacks are formed over and around the layers of first and
second channel material to form respective first and second
semiconductor devices in the first and second device regions.
Inventors: |
Guillorn; Michael A.; (Cold
Springs, NY) ; Lauer; Isaac; (Yorktown Heights,
NY) ; Loubet; Nicolas J.; (Guilderland, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
Armonk |
NY |
US |
|
|
Family ID: |
59702248 |
Appl. No.: |
15/057439 |
Filed: |
March 1, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0673 20130101;
H01L 21/823807 20130101; H01L 21/30604 20130101; H01L 21/845
20130101; H01L 21/823821 20130101; H01L 21/823828 20130101; H01L
21/02532 20130101; H01L 29/161 20130101; H01L 29/66545 20130101;
H01L 29/1054 20130101; H01L 29/42392 20130101; H01L 27/0924
20130101; H01L 29/78 20130101; H01L 21/32133 20130101; H01L 27/1211
20130101 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 21/306 20060101 H01L021/306; H01L 29/423 20060101
H01L029/423; H01L 27/092 20060101 H01L027/092; H01L 21/3213
20060101 H01L021/3213; H01L 21/84 20060101 H01L021/84; H01L 21/8238
20060101 H01L021/8238; H01L 27/12 20060101 H01L027/12; H01L 21/02
20060101 H01L021/02; H01L 29/66 20060101 H01L029/66 |
Claims
1. A method for forming nanosheet semiconductor devices,
comprising: forming a first nanosheet stack in a first device
region comprising layers of a first channel material and layers of
a sacrificial material; forming a second nanosheet stack in a
second device region comprising layers of a second channel
material, layers of the sacrificial material, and a liner formed
around the layers of the second channel material; etching away the
sacrificial material using a wet etch that is selective to the
sacrificial material and the second channel material and does not
affect the first channel material or the liner, wherein the liner
protects the second channel material from the wet etch; and forming
gate stacks over and around the layers of first and second channel
material to form respective first and second semiconductor devices
in the first and second device regions.
2. The method of claim 1, wherein the first channel material is
silicon and the second channel material is silicon germanium having
a germanium concentration of about 30%.
3. The method of claim 2, wherein the liner is silicon.
4. The method of claim 1, wherein the sacrificial material is
silicon germanium having a germanium concentration of about
50%.
5. (canceled)
6. The method of claim 1, further comprising: forming a dummy gate
stack over channel regions of the first and second nanosheet
stacks; depositing a passivating insulator layer around the dummy
gate stacks; and etching away the dummy gate stacks prior to
etching away the sacrificial material.
7. The method of claim 6, further comprising etching away material
of the first and second nanosheet stacks that is not covered by the
dummy gate stacks to form first and second channel region
stacks.
8. The method of claim 7, further comprising forming a vertical
liner on sidewalls of the second channel region stack, wherein the
vertical liner protects the second channel material from lateral
etching.
9. The method of claim 7, further comprising etching trenches in
the first and second nanosheet stacks to separate each nanosheet
stack into a first and second plurality of nanosheet fins.
10. The method of claim 9, further comprising depositing source and
drain regions at respective ends of each nanosheet fins, wherein
source and drain regions of the first plurality of nanosheet fins
are n-type doped and wherein the source and drain regions of the
second plurality of nanosheet fins are p-type doped.
11. A method for forming nanosheet semiconductor devices,
comprising: forming a first nanosheet stack in a first device
region comprising alternating layers of silicon and layers silicon
germanium having a germanium concentration of about 50%; forming a
second nanosheet stack in a second device region comprising layers
of silicon germanium having a germanium concentration of about 30%,
layers of silicon germanium having a germanium concentration of
about 50%, and a silicon liner formed around the layers of silicon
germanium having a germanium concentration of about 30%; etching
away the sacrificial material with a wet etch that is selective to
the silicon germanium layers and does not affect the silicon layers
or the silicon liner, wherein the silicon liner protects the layers
silicon germanium having a germanium concentration of about 30%
from the etch; and forming gate stacks over and around the layers
of silicon and the layers of silicon germanium having a germanium
concentration of about 30% to form respective first and second
semiconductor devices in the first and second device regions.
12. The method of claim 11, further comprising: forming a dummy
gate stack over channel regions of the first and second nanosheet
stacks; depositing a passivating insulator layer around the dummy
gate stacks; and etching away the dummy gate stacks prior to
etching away the sacrificial material.
13. The method of claim 12, further comprising etching away
material of the first and second nanosheet stacks that is not
covered by the dummy gate stacks to form first and second channel
region stacks.
14. The method of claim 13, further comprising forming a vertical
silicon liner on sidewalls of the second channel region stack,
wherein the vertical silicon liner protects the layers of silicon
germanium having a germanium concentration of about 30% from
lateral etching.
15. An integrated chip, comprising: a first semiconductor device
comprising a plurality of first nanosheet channel layers of a first
semiconductor material; a second semiconductor device comprising a
plurality of second nanosheet channel layers of a second
semiconductor material and a liner formed around the second
nanosheet channel layers; gate stacks formed over and around the
first and second nanosheet channel layers respectively; and a
vertical liner on sidewalls of the gate stack that is over the
second nanosheet channel layers.
16. The integrated chip of claim 15, wherein the first
semiconductor material is silicon and the second semiconductor
material is silicon germanium having a germanium concentration of
about 30%.
17. The integrated chip of claim 16, wherein the liner is
silicon.
18. (canceled)
19. The integrated chip of claim 15, further comprising first and
second source/drain regions at opposite ends of the respective
first and second nanosheet channel layers.
20. The integrated chip of claim 19, wherein the source and drain
regions of the first semiconductor device are n-type doped and
wherein the source and drain regions of the second semiconductor
device are p-type doped.
Description
BACKGROUND
[0001] Technical Field
[0002] The present invention relates to semiconductor devices and,
more particularly, to the integration of silicon and
silicon-germanium nanosheet devices on a single chip.
[0003] Description of the Related Art
[0004] Semiconductor devices may be formed with "nanosheets," where
a thin sheet of semiconductor material is used, for example, as the
channel of a field effect transistor (FET). While nanosheets may be
formed from a variety of semiconductor materials, forming multiple
such devices using different respective channel materials can be
challenging and may necessitate the use of exotic processes to
selectively etch only one type of channel material. These exotic
chemistries may be damaging to other device components, for example
making it difficult to form good source/drain isolation
SUMMARY
[0005] A method for forming nanosheet semiconductor devices
includes forming a first nanosheet stack in a first device region
comprising layers of a first channel material and layers of a
sacrificial material. A second nanosheet stack is formed in a
second device region comprising layers of a second channel
material, layers of the sacrificial material, and a liner formed
around the layers of the second channel material. The sacrificial
material is etched away. The liner protects the second channel
material from the etch. Gate stacks are formed over and around the
layers of first and second channel material to form respective
first and second semiconductor devices in the first and second
device regions.
[0006] A method for forming nanosheet semiconductor devices
includes forming a first nanosheet stack in a first device region
comprising alternating layers of silicon and layers silicon
germanium having a germanium concentration of about 50%. A second
nanosheet stack is formed in a second device region comprising
layers of silicon germanium having a germanium concentration of
about 30%, layers of silicon germanium having a germanium
concentration of about 50%, and a silicon liner formed around the
layers of silicon germanium having a germanium concentration of
about 30%. The sacrificial material is etched away with a wet etch
that is selective to the silicon germanium layers and does not
affect the silicon layers or the silicon liner. The silicon liner
protects the layers silicon germanium having a germanium
concentration of about 30% from the etch. Gate stacks are formed
over and around the layers of silicon and the layers of silicon
germanium having a germanium concentration of about 30% to form
respective first and second semiconductor devices in the first and
second device regions.
[0007] An integrated chip includes a first semiconductor device
comprising a plurality of first nanosheet channel layers of a first
semiconductor material. A second semiconductor device comprises a
plurality of second nanosheet channel layers of a second
semiconductor material and a liner formed around the second
nanosheet channel layers. Gate stacks are formed over and around
the first and second nanosheet channel layers respectively.
[0008] These and other features and advantages will become apparent
from the following detailed description of illustrative embodiments
thereof, which is to be read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0009] The disclosure will provide details in the following
description of preferred embodiments with reference to the
following figures wherein:
[0010] FIG. 1 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0011] FIG. 2 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0012] FIG. 3 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0013] FIG. 4 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0014] FIG. 5 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0015] FIG. 6 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0016] FIG. 7 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0017] FIG. 8 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0018] FIG. 9 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0019] FIG. 10 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0020] FIG. 11 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0021] FIG. 12 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0022] FIG. 13 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0023] FIG. 14 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0024] FIG. 15 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0025] FIG. 16 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles;
[0026] FIG. 17 is a cross-sectional diagram of a step in the
formation of multiple nanosheet semiconductor devices on a single
chip in accordance with the present principles; and
[0027] FIG. 18 is a block/flow diagram of a method of forming
multiple nanosheet semiconductor devices on a single chip in
accordance with the present principles.
DETAILED DESCRIPTION
[0028] Embodiments of the present invention form multiple nanosheet
devices on a same chip from multiple different materials. To
prevent etching processes for a first nanosheet material from
interfering with a second nanosheet material, a protective cladding
layer is used. This makes it possible to selectively etch features
of the respective devices without resorting to exotic
chemistries.
[0029] Referring now to the drawings in which like numerals
represent the same or similar elements and initially to FIG. 1, a
step in forming multiple nanosheet devices having different channel
materials is shown. A substrate is formed from a semiconductor
layer 104 on an insulator layer 102. It should be recognized that
the substrate layer 104 may alternatively be formed from a bulk
semiconductor material without the underlying insulator layer 102.
It is specifically contemplated that the insulator layer 102 may be
silicon dioxide, but it should be understood that any appropriate
material may be used including, e.g., any buried oxide or a glass
layer. A hardmask layer 106 is deposited over the substrate layer
104.
[0030] In one example, the semiconductor layer 104 may be formed
from a silicon-containing material. Illustrative examples of
silicon-containing materials suitable for the bulk-semiconductor
substrate include, but are not limited to, silicon, silicon
germanium, silicon germanium carbide, silicon carbide, polysilicon,
polysilicon, epitaxial silicon, amorphous silicon, and multi-layers
thereof. Although silicon is the predominantly used semiconductor
material in wafer fabrication, alternative semiconductor materials
can be employed, such as, but not limited to, germanium, gallium
arsenide, gallium nitride, cadmium telluride and zinc
sellenide.
[0031] Alternatively, the semiconductor layer 104 may be formed
from a type III-V semiconductor material. This denotes a
semiconductor material that includes at least one element from
Group III of the Periodic Table of Elements and at least one
element from Group V of the Periodic Table of Elements. Typically,
the III-V compound semiconductors are binary, ternary or quaternary
alloys including III/V elements. Examples of III-V compound
semiconductors that can be used in the present invention include,
but are not limited to alloys of aluminum antimonide, aluminum
arsenide, aluminum nitride, aluminum phosphide, gallium arsenide,
gallium phosphide, indium antimonide, indium arsenic, indium
nitride, indium phosphide, aluminum gallium arsenide, indium
gallium phosphide, aluminum indium arsenic, aluminum indium
antimonide, gallium arsenide nitride, gallium arsenide antimonide,
aluminum gallium nitride, aluminum gallium phosphide, indium
gallium nitride, indium arsenide antimonide, indium gallium
antimonide, aluminum gallium indium phosphide, aluminum gallium
arsenide phosphide, indium gallium arsenide phosphide, indium
arsenide antimonide phosphide, aluminum indium arsenide phosphide,
aluminum gallium arsenide nitride, indium gallium arsenide nitride,
indium aluminum arsenide nitride, gallium arsenide antimonide
nitride, gallium indium nitride arsenide aluminum antimonide,
gallium indium arsenide antimonide phosphide, and combinations
thereof.
[0032] It is specifically contemplated that the hardmask layer 106
may be formed from silicon nitride, but any appropriate dielectric
material may be used in its place. Other materials for the hardmask
layer 106 may include silicon oxides, silicon oxynitrides, silicon
carbides, silicon carbonitrides, etc. Spin-on dielectrics may also
be utilized as a hardmask material including, but not limited to:
silsequioxanes, siloxanes, and boron phosphate silicate glass
(BPSG).
[0033] In one embodiment, the hardmask layer 106 is deposited by
chemical vapor deposition (CVD), but it should be understood that
atomic layer deposition (ALD), physical vapor deposition (PVD), or
gas cluster ion beam (GCIB) deposition may be used instead.
[0034] CVD is a deposition process in which a deposited species is
formed as a result of chemical reaction between gaseous reactants
at greater than room temperature (e.g., from about 25.degree. C.
about 900.degree. C.). The solid product of the reaction is
deposited on the surface on which a film, coating, or layer of the
solid product is to be formed. Variations of CVD processes include,
but are not limited to, Atmospheric Pressure CVD (APCVD), Low
Pressure CVD (LPCVD), Plasma Enhanced CVD (EPCVD), and
Metal-Organic CVD (MOCVD) and combinations thereof may also be
employed. In alternative embodiments that use PVD, a sputtering
apparatus may include direct-current diode systems, radio frequency
sputtering, magnetron sputtering, or ionized metal plasma
sputtering. In alternative embodiments that use ALD, chemical
precursors react with the surface of a material one at a time to
deposit a thin film on the surface. In alternative embodiments that
use GCIB deposition, a high-pressure gas is allowed to expand in a
vacuum, subsequently condensing into clusters. The clusters can be
ionized and directed onto a surface, providing a highly anisotropic
deposition.
[0035] Referring now to FIG. 2, a step in forming multiple
nanosheet devices having different channel materials is shown. A
mask 202 is deposited over a first region 204 of the substrate 104.
The material of the hardmask layer 106 is stripped away from the
unmasked region 206. The two regions 204/206 define respective
p-type and n-type device regions, for example pFETs and nFETs. It
should be understood that the two regions 204 and 206 are shown as
being adjacent for the sake of compactness and ease of
description--in actual embodiments the two regions may be located
anywhere on a chip.
[0036] Referring now to FIG. 3, a step in forming multiple
nanosheet devices having different channel materials is shown. A
source/drain isolation layer 308 is formed on the second region
206. It is specifically contemplated that the channel region may be
a doped semiconductor material. In one embodiment, the source/drain
isolation layer 308 may be a p-type doped silicon or silicon
germanium layer that is in situ doped during formation or is formed
by ion implantation. The source/drain isolation layer 308 has a
dopant type opposite to that of the eventual source and drain
structures to provide junction isolation and reduce source-to-drain
leakage.
[0037] As used herein, "p-type" refers to the addition of
impurities to an intrinsic semiconductor that creates deficiencies
of valence electrons. In a silicon-containing substrate, examples
of p-type dopants, i.e., impurities, include but are not limited
to: boron, aluminum, gallium and indium. As used herein, "n-type"
refers to the addition of impurities that contributes free
electrons to an intrinsic semiconductor In a silicon containing
substrate examples of n-type dopants, i.e., impurities, include but
are not limited to antimony, arsenic and phosphorous. In this case,
a p-type dopant is used for the layer 308 of, e.g., an nFET second
region 206.
[0038] A stack of alternating semiconductor layers 302/304 is
deposited in the second region 206. It is specifically contemplated
that the stack may be formed from alternating silicon and silicon
germanium nanosheets, but it is should be understood that
alternative semiconductor materials may be used instead. In one
embodiment, there are seven layers, with silicon germanium layers
having a germanium concentration of about 50% being the first set
of layers 302, including a top layer, and with pure silicon layers
being the second set of layers 304. After formation of the stack in
the second region 206, the mask 202 is removed and an additional
layer of hardmask material 306 is deposited over all horizontal
surfaces.
[0039] Referring now to FIG. 4, a step in forming multiple
nanosheet devices having different channel materials is shown. A
mask 402 is deposited over the second device region 206. The
hardmask material over the first device region 204 is stripped away
to leave the first device region 204 exposed.
[0040] Referring now to FIG. 5, a step in forming multiple
nanosheet devices having different channel materials is shown. A
layer 508 is formed on the second region 206. It is specifically
contemplated that the channel region may be a doped semiconductor
material. In one embodiment, the layer 508 may be an n-type doped
silicon or silicon germanium layer that is in situ doped during
formation or is formed by ion implantation. In this case, an n-type
dopant is used for the layer 508 of, e.g., a pFET second region
204.
[0041] A stack of alternating semiconductor layers is 502/504 is
deposited in the first region 204 with a thin layer 506 of a third
semiconductor material in between each alternating layer 502/504.
It is specifically contemplated that the alternating layers 502/504
may be formed from alternating nanosheets of silicon germanium,
with a 50% concentration of germanium and with a 30% concentration
of germanium respectively. In one embodiment there are seven
layers, with the 50% layers being the first set of layers 502,
including a top layer, and with the 30% layers being the second set
of layers 504. It is specifically contemplated that the layers 506
of the third semiconductor material may be formed from pure silicon
and may have an exemplary thickness of about 2 nm. The layers 506
of the third semiconductor material are used to provide superior
mechanical stability for the stack and as an etch stop layer for
subsequent fabrication processes.
[0042] At this point, the sheets of alternating semiconductor
material may be etched and isolated to form multiple parallel fins.
The details of fin formation will be discussed below. It should be
understood that the following set of figures illustrate a single
fin, cut along its length.
[0043] Referring now to FIG. 6, a step in forming multiple
nanosheet devices having different channel materials is shown. Any
remaining hardmask material 306 is removed. Dummy gate stacks 600
are formed over the respective fins in device regions 204 and 206.
The dummy gate stacks 600 may include a dummy gate dielectric 602,
a dummy gate 604, a hardmask cap 606, and a mask 608. The dummy
gate 604 may be formed from semiconductor material, such as
polysilicon or amorphous silicon, or a dielectric material such as
an oxide, nitride, or oxynitride material. The dummy gate stack 600
may be formed by depositing the various layers and subsequently
removing any material not covered by, e.g., masks 606, using an
anisotropic etch such as a reactive ion etch (RIE).
[0044] RIE is a form of plasma etching in which during etching the
surface to be etched is placed on a radio-frequency powered
electrode. Moreover, during RIE the surface to be etched takes on a
potential that accelerates the etching species extracted from
plasma toward the surface, in which the chemical etching reaction
is taking place in the direction normal to the surface. Other
examples of anisotropic etching that can be used at this point of
the present invention include ion beam etching, plasma etching or
laser ablation.
[0045] Referring now to FIG. 7, a step in forming multiple
nanosheet devices having different channel materials is shown.
Dummy gate spacers 702 are deposited along the vertical sidewalls
of the dummy gate stacks 600. The stacks of semiconductor materials
are then etched anisotropically using, e.g., RIE, to trim any such
material outside of the channel regions 704 defined by the dummy
spacers 702. The stacks are trimmed down to the underlying layers
308 and 508.
[0046] Referring now to FIG. 8, a step in forming multiple
nanosheet devices having different channel materials is shown. A
thin liner layer 802 is deposited over the first device region 204.
In an embodiment where the first device region 204 defines a pFET
device having alternating layers of 50%-germanium silicon germanium
and 30%-germanium silicon germanium, the thin liner layer 802 may
be formed from silicon and may have an exemplary thickness of about
2 nm. This liner layer prevents lateral etch of the silicon
germanium in the first device region 204 during subsequent
processing steps. The liner 802 may be deposited using, e.g., CVD
or any other conformal deposition process and may be prevented from
forming in the second device region 206 by masking that region.
[0047] Referring now to FIG. 9, a step in forming multiple
nanosheet devices having different channel materials is shown. A
first source/drain material 902 is deposited in the first device
region 204 and a second source/drain material 904 is deposited in
the second device region 206. It is contemplated that the first
source/drain material 902 may include a semiconductor material that
is doped with an n-type dopant. In one specific embodiment, the
first source/drain material 902 may be boron-doped silicon
germanium. It is similarly contemplated that the second
source/drain material 904 may include a semiconductor material that
is doped with a p-type dopant. In one specific embodiment, the
second source/drain material 904 may be phosphorous-doped silicon
carbide.
[0048] As used herein, "p-type" refers to the addition of
impurities to an intrinsic semiconductor that creates deficiencies
of valence electrons. In a silicon-containing substrate, examples
of p-type dopants, i.e., impurities, include but are not limited
to: boron, aluminum, gallium and indium. As used herein, "n-type"
refers to the addition of impurities that contributes free
electrons to an intrinsic semiconductor In a silicon containing
substrate examples of n-type dopants, i.e., impurities, include but
are not limited to antimony, arsenic and phosphorous. A p-type
device may include, for example, a p-type channel region, whereas
an n-type device may include, for example, an n-type channel
region. Dopants may be introduced into the source/drain regions 902
and 904 by implantation or may be formed in situ. In one particular
embodiment, the source/drain regions 902 and 904 are grown
epitaxially with their respective dopants being formed in situ.
[0049] Referring now to FIG. 10, a step in forming multiple
nanosheet devices having different channel materials is shown. An
insulator layer 1002 is filled in around the spacers 702 and the
dummy gate stacks 600 are etched away. The insulator layer 1002 may
be deposited using, e.g., CVD or any other appropriate deposition
process. The insulator material may then be polished down to the
level of the dummy gate stacks 600 using CMP. The gate stacks 600
themselves may be removed using an anisotropic etch such as, e.g.,
RIE, stopping on the underlying semiconductor layers.
[0050] Referring now to FIG. 11, a step in forming multiple
nanosheet devices having different channel materials is shown. A
wet chemical etch is used to remove the semiconductor layers 502
from the stacks 600 in both device regions 204 and 206. In an
embodiment where these semiconductor layers are formed from
50%-germanium silicon germanium material, an etch using vapor-phase
hydrochloric acid or wet "standard clean" using ammonium hydroxide
and hydrogen peroxide is used to selectively remove the exposed
silicon germanium. In the first device region 204, where a
30%-germanium silicon germanium layers 504 would potentially also
be etched by the wet chemical etch, the thin semiconductor layer
506 (e.g., pure silicon) functions as an etch stop, preventing the
etch from reaching the remaining layers 504.
[0051] Referring now to FIG. 12, a step in forming multiple
nanosheet devices having different channel materials is shown. The
protective silicon liners 506 and 802 are etched away during
surface preparation using, e.g., oxidation with ozone or a
"standard clean" was as described above. A gate dielectric 1202 is
then conformally deposited around the remaining nanosheets 304 and
504 and a gate 1204 is filled in. The gate dielectric 1202 may be
formed from a high-k dielectric, with exemplary materials including
hafnium oxides, zirconium oxides, aluminum oxides, titanium oxides,
lanthanum oxides, strontium titanium oxides, lanthanum aluminum
oxides, and yttrium oxides. The gate 1204 may be formed from any
appropriate workfunction material, with exemplary gate materials
including titanium nitride and titanium carbide.
[0052] Referring now to FIG. 13, a step in forming multiple
nanosheet devices having different channel materials is shown. As
noted above, the preceding figures showed steps performed along a
single cross-section. FIG. 13 depicts an intermediate step between
FIGS. 5 and 6, along cross sections perpendicular to the cross
section depicted for each device region. This cross section occurs
at a point laterally distant from the region that will eventually
form the gate and channel regions, such that FIG. 13 and ensuing
figures illustrate the source/drain regions. After removal of the
hardmask 306, trenches 1302 are formed in the stacks in each of the
device regions 204 and 206. The trenches may be formed using any
appropriate anisotropic etch including, e.g., RIE. Notably, the
trenches extend downward into the underlying semiconductor layer
104. This separates the initial stack of sheets into discrete fins
1304.
[0053] Referring now to FIG. 14, a step in forming multiple
nanosheet devices having different channel materials is shown. This
figure follows the cross-section of FIG. 13 and illustrates the
deposition of an insulator 1402 in the trenches 1302 between the
fins 1304. It is specifically contemplated that silicon dioxide may
be used as the insulator 1402, but it should be understood that
other insulator materials may be used instead. In one embodiment,
the insulator 1402 may be deposited a height above the height of
the fins 1304 and then polished down to expose the tops of the fins
1304 using CMP.
[0054] Referring now to FIG. 15, a step in forming multiple
nanosheet devices having different channel materials is shown. The
insulator 1402 is etched down to expose the fins 1304, leaving a
remaining insulator layer 1502 between the fins' bases. The
insulator 1402 may be etched using a dry, plasma assisted etch
process or may, alternatively, be etched using a wet etch such as
with dilute hydrofluoric acid.
[0055] Referring now to FIG. 16, a step in forming multiple
nanosheet devices having different channel materials is shown. This
figure shows an alternative view of FIG. 7, as the fins 1304 are
etched in the source/drain regions to expose the underlying
source/drain isolation layers 308 and 508. The source/drain
isolation layers 308 and 508 can be formed with a high proportion
of germanium and selectively removed using, e.g., a vapor phase
hydrochloric acid etch or a wet "standard clean" etch and replaced
with dielectric material. Alternatively, the source/drain isolation
layers 308 and 508 may be selectively oxidized at moderate
temperatures if the germanium concentration is high enough (e.g.,
greater than about 50%).
[0056] Referring now to FIG. 17, a step in forming multiple
nanosheet devices having different channel materials is shown. This
step corresponds with FIG. 9 and shows the deposition of the
source/drain regions 902 and 904 for the first and second device
regions 204 and 206 respectively. As noted above, the material of
the first source/drain region 902 may be grown epitaxially and in
situ doped, with an exemplary embodiment using boron-doped silicon
germanium. The material of the second source/drain region 904 may
also be grown epitaxially and in situ doped, with an exemplary
embodiment using phosphorous-doped silicon carbide. The
source/drain regions on respective fin regions merge with one
another to form the merged source/drain regions shown. It should be
noted that the layers 308 and 508 may be used as a seed layer for
the epitaxial growth.
[0057] It is to be understood that the present invention will be
described in terms of a given illustrative architecture having a
wafer; however, other architectures, structures, substrate
materials and process features and steps may be varied within the
scope of the present invention.
[0058] It will also be understood that when an element such as a
layer, region or substrate is referred to as being "on" or "over"
another element, it can be directly on the other element or
intervening elements may also be present. In contrast, when an
element is referred to as being "directly on" or "directly over"
another element, there are no intervening elements present. It will
also be understood that when an element is referred to as being
"connected" or "coupled" to another element, it can be directly
connected or coupled to the other element or intervening elements
may be present. In contrast, when an element is referred to as
being "directly connected" or "directly coupled" to another
element, there are no intervening elements present.
[0059] A design for an integrated circuit chip may be created in a
graphical computer programming language, and stored in a computer
storage medium (such as a disk, tape, physical hard drive, or
virtual hard drive such as in a storage access network). If the
designer does not fabricate chips or the photolithographic masks
used to fabricate chips, the designer may transmit the resulting
design by physical means (e.g., by providing a copy of the storage
medium storing the design) or electronically (e.g., through the
Internet) to such entities, directly or indirectly. The stored
design is then converted into the appropriate format (e.g., GDSII)
for the fabrication of photolithographic masks, which typically
include multiple copies of the chip design in question that are to
be formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0060] Methods as described herein may be used in the fabrication
of integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0061] Reference in the specification to "one embodiment" or "an
embodiment" of the present principles, as well as other variations
thereof, means that a particular feature, structure,
characteristic, and so forth described in connection with the
embodiment is included in at least one embodiment of the present
principles. Thus, the appearances of the phrase "in one embodiment"
or "in an embodiment", as well any other variations, appearing in
various places throughout the specification are not necessarily all
referring to the same embodiment.
[0062] It is to be appreciated that the use of any of the following
"/", "and/or", and "at least one of", for example, in the cases of
"A/B", "A and/or B" and "at least one of A and B", is intended to
encompass the selection of the first listed option (A) only, or the
selection of the second listed option (B) only, or the selection of
both options (A and B). As a further example, in the cases of "A,
B, and/or C" and "at least one of A, B, and C", such phrasing is
intended to encompass the selection of the first listed option (A)
only, or the selection of the second listed option (B) only, or the
selection of the third listed option (C) only, or the selection of
the first and the second listed options (A and B) only, or the
selection of the first and third listed options (A and C) only, or
the selection of the second and third listed options (B and C)
only, or the selection of all three options (A and B and C). This
may be extended, as readily apparent by one of ordinary skill in
this and related arts, for as many items listed.
[0063] Referring now to FIG. 18, a method of forming multiple
nanosheet devices having different channel materials is shown.
Block 1802 forms a first nanosheet stack on a substrate and block
1804 forms a second nanosheet stack on the substrate, the second
nanosheet stack being formed with a different channel layer
composition and having a liner 506. In one particular embodiment,
the first nanosheet stack has channel layers 304 formed from
silicon while the second nanosheet stack has channel layers 504
formed from 30%-germanium silicon germanium. In this embodiment,
the liner 506 may be formed using silicon to protect the channel
layers 504 of the of the second nanosheet stack. The sacrificial
layers of the stack may be formed with, e.g., 50%-germanium silicon
germanium.
[0064] Block 1806 forms fin stacks 1304 from the nanosheet stacks
by etching the nanosheet stacks down, isolating adjacent fins from
one another. Block 1808 forms a fin isolation insulator by
depositing an insulator material 1402 (e.g., silicon dioxide) and
etching the insulator material down to form an isolation layer
1502. Block 1810 then forms the dummy gate stack 600 over the
respective fins of the first and second device regions.
[0065] Block 1812 etches the fin stack material outside of that
covered by the dummy gates to expose the source/drain seed surfaces
308 and 508. Block 1814 then forms the source/drain regions 902 and
904 for the respective device regions. In one embodiment, the
source/drain regions 902 and 904 are grown epitaxially and doped in
situ.
[0066] Block 1816 deposits a passivating insulator 1002 over the
fins and dummy gate stack 600. In one embodiment, the passivating
insulator 1002 may be formed from silicon dioxide and may be
deposited using CVD and planarized down to the level of the dummy
gate stacks 600. Block 1818 then removes the dummy gate stacks 600,
exposing the fin stacks. Block 1820 removes the sacrificial
nanosheet material (e.g., 50%-germanium silicon germanium) from the
fin stacks. In one embodiment the etch of block 1820 uses
vapor-phase hydrochloric acid or wet "standard clean" wash to
selectively remove silicon germanium while leaving pure silicon
intact. The liner 506 protects the channel layers of the second fin
stack from the etch of block 1820. Block 1822 then forms the gate
stack over and around the channel layers to form two sets of
semiconductor devices having distinct nanosheet channel
materials.
[0067] Having described preferred embodiments of co-integration of
silicon and silicon germanium channels for nanosheet devices (which
are intended to be illustrative and not limiting), it is noted that
modifications and variations can be made by persons skilled in the
art in light of the above teachings. It is therefore to be
understood that changes may be made in the particular embodiments
disclosed which are within the scope of the invention as outlined
by the appended claims. Having thus described aspects of the
invention, with the details and particularity required by the
patent laws, what is claimed and desired protected by Letters
Patent is set forth in the appended claims.
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