| Patent | Date |
|---|
Embedded Microstrip Transmission Line
App 20220123449 - Lauer; Isaac ; et al. | 2022-04-21 |
Vacuum Encapsulated Josephson Junction
App 20220102612 - Lauer; Isaac ; et al. | 2022-03-31 |
Superconducting Circuit Provided On An Encapsulated Vacuum Cavity
App 20220102613 - Lauer; Isaac ; et al. | 2022-03-31 |
Graphene/nanostructure Fet With Self-aligned Contact And Gate
App 20220093772 - Chang; Josephine ; et al. | 2022-03-24 |
Heavy-hex Connection Topology To Rectilinear Physical Layout
App 20220028927 - Lauer; Isaac ; et al. | 2022-01-27 |
Qubit Pulse Calibration Via Canary Parameter Monitoring
App 20220019927 - Lauer; Isaac | 2022-01-20 |
All microwave ZZ control
Grant 11,223,347 - Mckay , et al. January 11, 2 | 2022-01-11 |
Qubit Reset From Excited States
App 20210342161 - Lauer; Isaac ; et al. | 2021-11-04 |
Field Effect Transistor Structures
App 20210280674 - Chang; Josephine B. ; et al. | 2021-09-09 |
Target Qubit Decoupling In An Echoed Cross-resonance Gate
App 20210258079 - Lauer; Isaac ; et al. | 2021-08-19 |
Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETS
Grant 11,069,775 - Chang , et al. July 20, 2 | 2021-07-20 |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
Grant 11,004,678 - Doris , et al. May 11, 2 | 2021-05-11 |
Field effect transistor structures
Grant 11,004,933 - Chang , et al. May 11, 2 | 2021-05-11 |
Techniques for creating a local interconnect using a SOI wafer
Grant 10,699,955 - Chang , et al. | 2020-06-30 |
Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
Grant 10,680,061 - Chang , et al. | 2020-06-09 |
Nanowire with sacrificial top wire
Grant 10,658,461 - Chang , et al. | 2020-05-19 |
Sacrificial Layer For Channel Surface Retention And Inner Spacer Formation In Stacked-channel Fets
App 20200091289 - Chang; Josephine B. ; et al. | 2020-03-19 |
Strained semiconductor nanowire
Grant 10,580,894 - Chang , et al. | 2020-03-03 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20200066508 - Doris; Bruce B. ; et al. | 2020-02-27 |
Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
Grant 10,573,714 - Chang , et al. Feb | 2020-02-25 |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
Grant 10,522,342 - Doris , et al. Dec | 2019-12-31 |
Implementing A Hybrid Finfet Device And Nanowire Device Utilizing Selective Sgoi
App 20190288012 - Chang; Josephine B. ; et al. | 2019-09-19 |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
Grant 10,395,922 - Doris , et al. A | 2019-08-27 |
Sacrificial Layer For Channel Surface Retention And Inner Spacer Formation In Stacked-channel Fets
App 20190237541 - Chang; Josephine B. ; et al. | 2019-08-01 |
Hybrid III-V technology to support multiple supply voltages and off state currents on same chip
Grant 10,366,892 - Chang , et al. July 30, 2 | 2019-07-30 |
Co-integration of silicon and silicon-germanium channels for nanosheet devices
Grant 10,367,062 - Guillorn , et al. July 30, 2 | 2019-07-30 |
Implementing a hybrid finFET device and nanowire device utilizing selective SGOI
Grant 10,361,219 - Chang , et al. | 2019-07-23 |
Fabrication of a strained region on a substrate
Grant 10,361,304 - Lauer , et al. | 2019-07-23 |
Support for long channel length nanowire transistors
Grant 10,354,960 - Balakrishnan , et al. July 16, 2 | 2019-07-16 |
Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
Grant 10,325,983 - Chang , et al. | 2019-06-18 |
Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
Grant 10,217,817 - Chang , et al. Feb | 2019-02-26 |
Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET
Grant 10,170,609 - Cheng , et al. J | 2019-01-01 |
Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FET
Grant 10,170,608 - Cheng , et al. J | 2019-01-01 |
Co-integration of silicon and silicon-germanium channels for nanosheet devices
Grant 10,170,552 - Guillorn , et al. J | 2019-01-01 |
Wire-last gate-all-around nanowire FET
Grant 10,170,634 - Chang , et al. J | 2019-01-01 |
Gate-to-bulk substrate isolation in gate-all-around devices
Grant 10,170,636 - Chang , et al. J | 2019-01-01 |
Sacrificial Layer For Channel Surface Retention And Inner Spacer Formation In Stacked-channel Fets
App 20180366544 - Chang; Josephine B. ; et al. | 2018-12-20 |
Nanowire With Sacrificial Top Wire
App 20180350909 - Chang; Josephine B. ; et al. | 2018-12-06 |
Nanowire With Sacrificial Top Wire
App 20180331180 - Chang; Josephine B. ; et al. | 2018-11-15 |
Techniques for Creating a Local Interconnect Using a SOI Wafer
App 20180330989 - Chang; Josephine B. ; et al. | 2018-11-15 |
FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers
Grant 10,121,786 - Ando , et al. November 6, 2 | 2018-11-06 |
Fabrication Of A Strained Region On A Substrate
App 20180308976 - Lauer; Isaac ; et al. | 2018-10-25 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20180294151 - Doris; Bruce B. ; et al. | 2018-10-11 |
Nanowire with sacrificial top wire
Grant 10,096,673 - Chang , et al. October 9, 2 | 2018-10-09 |
Co-integration Of Silicon And Silicon-germanium Channels For Nanosheet Devices
App 20180277626 - Guillorn; Michael A. ; et al. | 2018-09-27 |
Strained Semiconductor Nanowire
App 20180254345 - Chang; Josephine B. ; et al. | 2018-09-06 |
Strained semiconductor nanowire
Grant 10,056,487 - Chang , et al. August 21, 2 | 2018-08-21 |
Techniques for creating a local interconnect using a SOI wafer
Grant 10,056,293 - Chang , et al. August 21, 2 | 2018-08-21 |
Fabrication of a strained region on a substrate
Grant 10,050,144 - Lauer , et al. August 14, 2 | 2018-08-14 |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
Grant 10,037,885 - Doris , et al. July 31, 2 | 2018-07-31 |
Co-integration of silicon and silicon-germanium channels for nanosheet devices
Grant 10,026,810 - Guillorn , et al. July 17, 2 | 2018-07-17 |
Hybrid III-V Technology to Support Multiple Supply Voltages and Off State Currents on Same Chip
App 20180174844 - Chang; Josephine B. ; et al. | 2018-06-21 |
Support for long channel length nanowire transistors
Grant 9,997,472 - Balakrishnan , et al. June 12, 2 | 2018-06-12 |
Integrated etch stop for capped gate and method for manufacturing the same
Grant 9,997,613 - Chang , et al. June 12, 2 | 2018-06-12 |
Stacked planar double-gate lamellar field-effect transistor
Grant 9,954,063 - Chang , et al. April 24, 2 | 2018-04-24 |
Stacked planar double-gate lamellar field-effect transistor
Grant 9,954,062 - Chang , et al. April 24, 2 | 2018-04-24 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20180096835 - Doris; Bruce B. ; et al. | 2018-04-05 |
Support for long channel length nanowire transistors
Grant 9,922,942 - Balakrishnan , et al. March 20, 2 | 2018-03-20 |
Hybrid III-V technology to support multiple supply voltages and off state currents on same chip
Grant 9,922,830 - Chang , et al. March 20, 2 | 2018-03-20 |
Mixed lithography approach for E-beam and optical exposure using HSQ
Grant 9,917,057 - Chang , et al. March 13, 2 | 2018-03-13 |
Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure
Grant 9,911,592 - Doris , et al. March 6, 2 | 2018-03-06 |
Fabrication Of A Strained Region On A Substrate
App 20180040730 - Lauer; Isaac ; et al. | 2018-02-08 |
Nanowire field effect transistor (FET) and method for fabricating the same
Grant 9,887,264 - Chu , et al. February 6, 2 | 2018-02-06 |
Through-silicon Via With Insulator Fill
App 20180005954 - ABRAHAM; DAVID W. ; et al. | 2018-01-04 |
Local germanium condensation for suspended nanowire and finFET devices
Grant 9,859,430 - Chang , et al. January 2, 2 | 2018-01-02 |
Stacked planar double-gate lamellar field-effect transistor
Grant 9,859,375 - Chang , et al. January 2, 2 | 2018-01-02 |
III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
Grant 9,812,370 - Chang , et al. November 7, 2 | 2017-11-07 |
Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure
Grant 9,812,321 - Doris , et al. November 7, 2 | 2017-11-07 |
Fabrication of a strained region on a substrate
Grant 9,793,398 - Lauer , et al. October 17, 2 | 2017-10-17 |
Co-integration Of Silicon And Silicon-germanium Channels For Nanosheet Devices
App 20170294357 - Guillorn; Michael A. ; et al. | 2017-10-12 |
Integrated Etch Stop For Capped Gate And Method For Manufacturing The Same
App 20170271475 - Chang; Josephine B. ; et al. | 2017-09-21 |
Co-integration Of Silicon And Silicon-germanium Channels For Nanosheet Devices
App 20170256610 - Guillorn; Michael A. ; et al. | 2017-09-07 |
Gate-to-bulk Substrate Isolation In Gate-all-around Devices
App 20170256655 - Chang; Josephine B. ; et al. | 2017-09-07 |
Co-integration Of Silicon And Silicon-germanium Channels For Nanosheet Devices
App 20170256612 - Guillorn; Michael A. ; et al. | 2017-09-07 |
Co-integration of silicon and silicon-germanium channels for nanosheet devices
Grant 9,755,017 - Guillorn , et al. September 5, 2 | 2017-09-05 |
Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth
Grant 9,754,965 - Chang , et al. September 5, 2 | 2017-09-05 |
Method For Fabricating A Semiconductor Device Including Gate-to-bulk Substrate Isolation
App 20170250290 - Chang; Josephine B. ; et al. | 2017-08-31 |
Method for fabricating a semiconductor device including gate-to-bulk substrate isolation
Grant 9,748,404 - Chang , et al. August 29, 2 | 2017-08-29 |
Fully-depleted SOI MOSFET with U-shaped channel
Grant 9,748,348 - Ando , et al. August 29, 2 | 2017-08-29 |
Support For Long Channel Length Nanowire Transistors
App 20170236944 - Balakrishnan; Karthik ; et al. | 2017-08-17 |
Nanowire With Sacrificial Top Wire
App 20170236900 - Chang; Josephine B. ; et al. | 2017-08-17 |
Semiconductor testing devices
Grant 9,728,624 - Chang , et al. August 8, 2 | 2017-08-08 |
Sacrificial Layer For Channel Surface Retention And Inner Spacer Formation In Stacked-channel Fets
App 20170221992 - Chang; Josephine B. ; et al. | 2017-08-03 |
Sacrificial Layer For Channel Surface Retention And Inner Spacer Formation In Stacked-channel Fets
App 20170213888 - Chang; Josephine B. ; et al. | 2017-07-27 |
FINFET with U-Shaped Channel
App 20170194325 - Ando; Takashi ; et al. | 2017-07-06 |
Wire-last Gate-all-around Nanowire Fet
App 20170194509 - Chang; Josephine B. ; et al. | 2017-07-06 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20170194510 - Doris; Bruce B. ; et al. | 2017-07-06 |
Support for long channel length nanowire transistors
Grant 9,691,715 - Balakrishnan , et al. June 27, 2 | 2017-06-27 |
Nanowire Field Effect Transistor (fet) And Method For Fabricating The Same
App 20170170270 - Chu; Jack O. ; et al. | 2017-06-15 |
Support For Long Channel Length Nanowire Transistors
App 20170154959 - Balakrishnan; Karthik ; et al. | 2017-06-01 |
Integrated etch stop for capped gate and method for manufacturing the same
Grant 9,653,547 - Chang , et al. May 16, 2 | 2017-05-16 |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
Grant 9,647,139 - Doris , et al. May 9, 2 | 2017-05-09 |
Semiconductor Testing Devices
App 20170125550 - Chang; Josephine B. ; et al. | 2017-05-04 |
Fully-Depleted SOI MOSFET with U-Shaped Channel
App 20170117373 - Ando; Takashi ; et al. | 2017-04-27 |
Support for long channel length nanowire transistors
Grant 9,627,330 - Balakrishnan , et al. April 18, 2 | 2017-04-18 |
Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
Grant 9,627,378 - Ando , et al. April 18, 2 | 2017-04-18 |
Strained Semiconductor Nanowire
App 20170084745 - Chang; Josephine B. ; et al. | 2017-03-23 |
Nanowire FET with tensile channel stressor
Grant 9,601,576 - Lauer , et al. March 21, 2 | 2017-03-21 |
Mixed Lithography Approach for E-Beam and Optical Exposure Using HSQ
App 20170077036 - Chang; Josephine B. ; et al. | 2017-03-16 |
Support For Long Channel Length Nanowire Transistors
App 20170069715 - Balakrishnan; Karthik ; et al. | 2017-03-09 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20170069763 - Doris; Bruce B. ; et al. | 2017-03-09 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20170069481 - Doris; Bruce B. ; et al. | 2017-03-09 |
Atomic Layer Deposition Sealing Integration For Nanosheet Complementary Metal Oxide Semiconductor With Replacement Spacer
App 20170069734 - Doris; Bruce B. ; et al. | 2017-03-09 |
Compound finFET device including oxidized III-V fin isolator
Grant 9,589,791 - Cheng , et al. March 7, 2 | 2017-03-07 |
Techniques for Dual Dielectric Thickness for a Nanowire CMOS Technology Using Oxygen Growth
App 20170062476 - Chang; Josephine B. ; et al. | 2017-03-02 |
III-V compound and Germanium compound nanowire suspension with Germanium-containing release layer
Grant 9,570,563 - Cohen , et al. February 14, 2 | 2017-02-14 |
III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
App 20170040219 - Chang; Josephine B. ; et al. | 2017-02-09 |
Techniques for multiple gate workfunctions for a nanowire CMOS technology
Grant 9,564,502 - Chang , et al. February 7, 2 | 2017-02-07 |
Mixed lithography approach for e-beam and optical exposure using HSQ
Grant 9,558,930 - Chang , et al. January 31, 2 | 2017-01-31 |
Support For Long Channel Length Nanowire Transistors
App 20170018608 - Balakrishnan; Karthik ; et al. | 2017-01-19 |
Support For Long Channel Length Nanowire Transistors
App 20170018508 - Balakrishnan; Karthik ; et al. | 2017-01-19 |
Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same
Grant 9,548,238 - Cheng , et al. January 17, 2 | 2017-01-17 |
Compound finFET device including oxidized III-V fin isolator
Grant 9,548,355 - Cheng , et al. January 17, 2 | 2017-01-17 |
Complementary metal-oxide silicon having silicon and silicon germanium channels
Grant 9,543,388 - Lauer , et al. January 10, 2 | 2017-01-10 |
Local Germanium Condensation For Suspended Nanowire And Finfet Devices
App 20170005190 - Chang; Josephine B. ; et al. | 2017-01-05 |
Internal Spacer Formation From Selective Oxidation For Fin-first Wire-last Replacement Gate-all-around Nanowire Fet
App 20170005180 - Cheng; Szu-Lin ; et al. | 2017-01-05 |
Implementing A Hybrid Finfet Device And Nanowire Device Utilizing Selective Sgoi
App 20170005112 - Chang; Josephine B. ; et al. | 2017-01-05 |
FINFET with U-Shaped Channel
App 20170005090 - Ando; Takashi ; et al. | 2017-01-05 |
Fully-Depleted SOI MOSFET with U-Shaped Channel
App 20170005173 - Ando; Takashi ; et al. | 2017-01-05 |
Internal Spacer Formation From Selective Oxidation For Fin-first Wire-last Replacement Gate-all-around Nanowire Fet
App 20170005188 - Cheng; Szu-Lin ; et al. | 2017-01-05 |
Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth
Grant 9,536,794 - Chang , et al. January 3, 2 | 2017-01-03 |
Hybrid FINFET/nanowire SRAM cell using selective germanium condensation
Grant 9,536,885 - Chang , et al. January 3, 2 | 2017-01-03 |
Compound Finfet Device Including Oxidized Iii-v Fin Isolator
App 20160380049 - Cheng; Szu-Lin ; et al. | 2016-12-29 |
Compound Finfet Device Including Oxidized Iii-v Fin Isolator
App 20160379820 - Cheng; Szu-Lin ; et al. | 2016-12-29 |
Strained semiconductor nanowire
Grant 9,530,876 - Chang , et al. December 27, 2 | 2016-12-27 |
Techniques for Multiple Gate Workfunctions for a Nanowire CMOS Technology
App 20160359011 - Chang; Josephine B. ; et al. | 2016-12-08 |
III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
Grant 9,496,184 - Chang , et al. November 15, 2 | 2016-11-15 |
Wire-last gate-all-around nanowire FET
Grant 9,496,338 - Chang , et al. November 15, 2 | 2016-11-15 |
Hybrid Finfet/nanowire Sram Cell Using Selective Germanium Condensation
App 20160293610 - Chang; Josephine B. ; et al. | 2016-10-06 |
Techniques for Dual Dielectric Thickness for a Nanowire CMOS Technology Using Oxygen Growth
App 20160284604 - Chang; Josephine B. ; et al. | 2016-09-29 |
Techniques For Multiple Gate Workfunctions For A Nanowire Cmos Technology
App 20160284810 - Chang; Josephine B. ; et al. | 2016-09-29 |
Iii-v Compound And Germanium Compound Nanowire Suspension With Germanium-containing Release Layer
App 20160284805 - Cohen; Guy M. ; et al. | 2016-09-29 |
Wire-last Gate-all-around Nanowire Fet
App 20160276432 - Chang; Josephine B. ; et al. | 2016-09-22 |
Epitaxial growth techniques for reducing nanowire dimension and pitch
Grant 9,449,820 - Cohen , et al. September 20, 2 | 2016-09-20 |
Techniques for multiple gate workfunctions for a nanowire CMOS technology
Grant 9,443,949 - Chang , et al. September 13, 2 | 2016-09-13 |
Multiple V.sub.T in III-V FETs
Grant 9,437,613 - Chang , et al. September 6, 2 | 2016-09-06 |
Nanowire field effect transistor (FET) and method for fabricating the same
Grant 9,431,301 - Chu , et al. August 30, 2 | 2016-08-30 |
Stacked Planar Double-gate Lamellar Field-effect Transistor
App 20160233314 - Chang; Josephine B. ; et al. | 2016-08-11 |
Stacked Planar Double-gate Lamellar Field-effect Transistor
App 20160233304 - Chang; Josephine B. ; et al. | 2016-08-11 |
Stacked Planar Double-gate Lamellar Field-effect Transistor
App 20160233320 - Chang; Josephine B. ; et al. | 2016-08-11 |
Complementary Metal-oxide Silicon Having Silicon And Silicon Germanium Channels
App 20160211328 - Lauer; Gen P. ; et al. | 2016-07-21 |
Complementary Metal-oxide Silicon Having Silicon And Silicon Germanium Channels
App 20160211327 - Lauer; Gen P. ; et al. | 2016-07-21 |
Stacked planar double-gate lamellar field-effect transistor
Grant 9,391,163 - Chang , et al. July 12, 2 | 2016-07-12 |
III-V compound and germanium compound nanowire suspension with germanium-containing release layer
Grant 9,390,980 - Cohen , et al. July 12, 2 | 2016-07-12 |
Static Memory Cell With Tfet Storage Elements
App 20160196867 - Chang; Leland ; et al. | 2016-07-07 |
Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same
Grant 9,385,122 - Cheng , et al. July 5, 2 | 2016-07-05 |
Multiple VT in III-V FETS
App 20160181277 - Chang; Josephine B. ; et al. | 2016-06-23 |
Epitaxial Growth Techniques for Reducing Nanowire Dimension and Pitch
App 20160181097 - Cohen; Guy M. ; et al. | 2016-06-23 |
Complementary metal-oxide silicon having silicon and silicon germanium channels
Grant 9,373,638 - Lauer , et al. June 21, 2 | 2016-06-21 |
Graphene/nanostructure FET with self-aligned contact and gate
Grant 9,368,599 - Chang , et al. June 14, 2 | 2016-06-14 |
Tuning gate lengths in semiconductor device structures
Grant 9,362,354 - Chang , et al. June 7, 2 | 2016-06-07 |
Nanowire FET with tensile channel stressor
Grant 9,324,801 - Lauer , et al. April 26, 2 | 2016-04-26 |
Stacked Planar Double-gate Lamellar Field-effect Transistor
App 20160099338 - Chang; Josephine B. ; et al. | 2016-04-07 |
Multiple V.sub.T in III-V FETs
Grant 9,299,615 - Chang , et al. March 29, 2 | 2016-03-29 |
FinFET field-effect transistors with atomic layer doping
Grant 9,287,136 - Chan , et al. March 15, 2 | 2016-03-15 |
Semiconductor device including an asymmetric feature
Grant 9,281,397 - Chang , et al. March 8, 2 | 2016-03-08 |
Mixed Lithography Approach for E-Beam and Optical Exposure Using HSQ
App 20160049294 - Chang; Josephine B. ; et al. | 2016-02-18 |
Gate to diffusion local interconnect scheme using selective replacement gate flow
Grant 9,263,550 - Chang , et al. February 16, 2 | 2016-02-16 |
Field Effect Transistor (fet) With Self-aligned Contacts, Integrated Circuit (ic) Chip And Method Of Manufacture
App 20160035743 - Cheng; Szu-Lin ; et al. | 2016-02-04 |
Techniques for Creating a Local Interconnect Using a SOI Wafer
App 20160020138 - Chang; Josephine B. ; et al. | 2016-01-21 |
Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
Grant 9,240,326 - Cheng , et al. January 19, 2 | 2016-01-19 |
Device and method for forming sharp extension region with controllable junction depth and lateral overlap
Grant 9,224,604 - Lauer , et al. December 29, 2 | 2015-12-29 |
Low temperature salicide for replacement gate nanowires
Grant 9,209,086 - Chang , et al. December 8, 2 | 2015-12-08 |
III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method
Grant 9,209,095 - Chang , et al. December 8, 2 | 2015-12-08 |
Diode structure and method for FINFET technologies
Grant 9,190,419 - Chang , et al. November 17, 2 | 2015-11-17 |
Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer
Grant 9,184,290 - Cheng , et al. November 10, 2 | 2015-11-10 |
Field effect transistor (FET) with self-aligned contacts, integrated circuit (IC) chip and method of manufacture
Grant 9,177,956 - Cheng , et al. November 3, 2 | 2015-11-03 |
Gate to Diffusion Local Interconnect Scheme Using Selective Replacement Gate Flow
App 20150303277 - Chang; Josephine B. ; et al. | 2015-10-22 |
Nanowire Fet With Tensile Channel Stressor
App 20150303262 - Lauer; Isaac ; et al. | 2015-10-22 |
Nanowire Fet With Tensile Channel Stressor
App 20150303303 - Lauer; Isaac ; et al. | 2015-10-22 |
Method Of Forming Well-controlled Extension Profile In Mosfet By Silicon Gemanium Based Sacrificial Layer
App 20150287826 - Cheng; Szu-lin ; et al. | 2015-10-08 |
Hybrid III-V Technology to Support Multiple Supply Voltages and Off State Currents on Same Chip
App 20150287600 - Chang; Josephine B. ; et al. | 2015-10-08 |
Iii-v, Ge, Or Sige Fin Base Lateral Bipolar Transistor Structure And Method
App 20150287650 - Chang; Josephine B. ; et al. | 2015-10-08 |
III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
App 20150287642 - Chang; Josephine B. ; et al. | 2015-10-08 |
Fabrication Of Field-effect Transistors With Atomic Layer Doping
App 20150236118 - CHAN; KEVIN K. ; et al. | 2015-08-20 |
Lateral bipolar transistor and CMOS hybrid technology
Grant 9,105,650 - Chang , et al. August 11, 2 | 2015-08-11 |
Method Of Manufacturing A Semiconductor Device Using Source/drain Epitaxial Overgrowth For Forming Self-aligned Contacts Without Spacer Loss And A Semiconductor Device Formed By Same
App 20150221643 - Cheng; Szu-Lin ; et al. | 2015-08-06 |
Silicidation blocking process using optically sensitive HSQ resist and organic planarizing layer
Grant 9,093,379 - Guillorn , et al. July 28, 2 | 2015-07-28 |
Device and method for forming sharp extension region with controllable junction depth and lateral overlap
Grant 9,087,772 - Lauer , et al. July 21, 2 | 2015-07-21 |
Strained Semiconductor Nanowire
App 20150179781 - Chang; Josephine B. ; et al. | 2015-06-25 |
Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same
Grant 9,059,205 - Cheng , et al. June 16, 2 | 2015-06-16 |
Stringer-free gate electrode for a suspended semiconductor fin
Grant 9,059,289 - Chang , et al. June 16, 2 | 2015-06-16 |
Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
Grant 9,059,095 - Cheng , et al. June 16, 2 | 2015-06-16 |
Fabrication of field-effect transistors with atomic layer doping
Grant 9,048,261 - Chan , et al. June 2, 2 | 2015-06-02 |
Stringer-free gate electrode for a suspended semiconductor fin
Grant 9,029,213 - Chang , et al. May 12, 2 | 2015-05-12 |
Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors
Grant 9,006,108 - Fuller , et al. April 14, 2 | 2015-04-14 |
Diode structure and method for wire-last nanomesh technologies
Grant 9,006,087 - Chang , et al. April 14, 2 | 2015-04-14 |
Diode structure and method for wire-last nanomesh technologies
Grant 8,994,108 - Chang , et al. March 31, 2 | 2015-03-31 |
Wire-last integration method and structure for III-V nanowire devices
Grant 8,969,145 - Chang , et al. March 3, 2 | 2015-03-03 |
Embedded silicon germanium N-type field effect transistor for reduced floating body effect
Grant 8,969,964 - Chang , et al. March 3, 2 | 2015-03-03 |
Method Of Manufacturing A Semiconductor Device Using Source/drain Epitaxial Overgrowth For Forming Self-aligned Contacts Without Spacer Loss And A Semiconductor Device Formed By Same
App 20150048428 - Cheng; Szu-Lin ; et al. | 2015-02-19 |
Method Of Manufacturing A Semiconductor Device Using A Self-aligned Opl Replacement Contact And Patterned Hsq And A Semiconductor Device Formed By Same
App 20150044870 - Cheng; Szu-Lin ; et al. | 2015-02-12 |
Field Effect Transistor (fet) With Self-aligned Contacts, Integrated Circuit (ic) Chip And Method Of Manufacture
App 20150035060 - Cheng; Szu-lin ; et al. | 2015-02-05 |
TFET with nanowire source
Grant 8,946,680 - Bangsaruntip , et al. February 3, 2 | 2015-02-03 |
Embedded silicon germanium N-type filed effect transistor for reduced floating body effect
Grant 8,940,591 - Chang , et al. January 27, 2 | 2015-01-27 |
Low Temperature Salicide for Replacement Gate Nanowires
App 20150021715 - Chang; Josephine B. ; et al. | 2015-01-22 |
Diode structure and method for gate all around silicon nanowire technologies
Grant 8,927,397 - Chang , et al. January 6, 2 | 2015-01-06 |
Gate stack of boron semiconductor alloy, polysilicon and high-K gate dielectric for low voltage applications
Grant 8,928,064 - Frank , et al. January 6, 2 | 2015-01-06 |
Diode structure and method for FINFET technologies
Grant 8,928,083 - Chang , et al. January 6, 2 | 2015-01-06 |
High-rate chemical vapor etch of silicon substrates
Grant 8,927,431 - Bedell , et al. January 6, 2 | 2015-01-06 |
Multi-orientation Semiconductor Devices Employing Directed Self-assembly
App 20140353761 - Guillorn; Michael A. ; et al. | 2014-12-04 |
Silicidation Blocking Process Using Optically Sensitive HSQ Resist and Organic Planarizing Layer
App 20140353825 - Guillorn; Michael A. ; et al. | 2014-12-04 |
Silicidation Blocking Process Using Optically Sensitive HSQ Resist and Organic Planarizing Layer
App 20140353826 - Guillorn; Michael A. ; et al. | 2014-12-04 |
High-Rate Chemical Vapor Etch of Silicon Substrates
App 20140357082 - Bedell; Stephen W. ; et al. | 2014-12-04 |
Multi-orientation Semiconductor Devices Employing Directed Self-assembly
App 20140353762 - Guillorn; Michael A. ; et al. | 2014-12-04 |
Diode structure for gate all around silicon nanowire technologies
Grant 8,901,655 - Chang , et al. December 2, 2 | 2014-12-02 |
Non-replacement gate nanomesh field effect transistor with pad regions
Grant 8,900,959 - Chang , et al. December 2, 2 | 2014-12-02 |
Gate stack including a high-k gate dielectric that is optimized for low voltage applications
Grant 8,900,952 - Frank , et al. December 2, 2 | 2014-12-02 |
Gate stack including a high-K gate dielectric that is optimized for low voltage applications
Grant 8,901,616 - Frank , et al. December 2, 2 | 2014-12-02 |
Multi-direction Wiring For Replacement Gate Lines
App 20140339639 - Chang; Josephine B. ; et al. | 2014-11-20 |
Stringer-free Gate Electrode For A Suspended Semiconductor Fin
App 20140332890 - Chang; Josephine B. ; et al. | 2014-11-13 |
Stringer-free Gate Electrode For A Suspended Semiconductor Fin
App 20140332892 - Chang; Josephine B. ; et al. | 2014-11-13 |
Semiconductor device including an asymmetric feature, and method of making the same
Grant 8,877,593 - Chang , et al. November 4, 2 | 2014-11-04 |
Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain
Grant 8,872,274 - Cohen , et al. October 28, 2 | 2014-10-28 |
Multi-direction wiring for replacement gate lines
Grant 8,872,241 - Chang , et al. October 28, 2 | 2014-10-28 |
Self-aligned Borderless Contacts Using A Photo-patternable Dielectric Material As A Replacement Contact
App 20140312395 - Cheng; Szu-lin ; et al. | 2014-10-23 |
Self-aligned Borderless Contacts Using A Photo-patternable Dielectric Material As A Replacement Contact
App 20140312397 - Cheng; Szu-lin ; et al. | 2014-10-23 |
Multi-direction wiring for replacement gate lines
Grant 8,865,531 - Chang , et al. October 21, 2 | 2014-10-21 |
Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
Grant 8,859,410 - Frank , et al. October 14, 2 | 2014-10-14 |
Semiconductor nanowire structure reusing suspension pads
Grant 8,853,790 - Chang , et al. October 7, 2 | 2014-10-07 |
Non-replacement Gate Nanomesh Field Effect Transistor With Pad Regions
App 20140264276 - Chang; Josephine B. ; et al. | 2014-09-18 |
Gate Stack Of Boron Semiconductor Alloy, Polysilicon And High-k Gate Dielectric For Low Voltage Applications
App 20140264639 - Frank; Martin M. ; et al. | 2014-09-18 |
Gate Stack Of Boron Semiconductor Alloy, Polysilicon And High-k Gate Dielectric For Low Voltage Applications
App 20140264638 - Frank; Martin M. ; et al. | 2014-09-18 |
Sacrificial Replacement Extension Layer To Obtain Abrupt Doping Profile
App 20140252501 - Cheng; Szu-Lin ; et al. | 2014-09-11 |
Sacrificial Replacement Extension Layer To Obtain Abrupt Doping Profile
App 20140252500 - Cheng; Szu-Lin ; et al. | 2014-09-11 |
Gate Stack Including A High-k Gate Dielectric That Is Optimized For Low Voltage Applications
App 20140252493 - Frank; Martin M. ; et al. | 2014-09-11 |
Gate Stack Including A High-k Gate Dielectric That Is Optimized For Low Voltage Applications
App 20140252492 - Frank; Martin M. ; et al. | 2014-09-11 |
Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
Grant 8,822,278 - Chang , et al. September 2, 2 | 2014-09-02 |
Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure
Grant 8,823,064 - Chang , et al. September 2, 2 | 2014-09-02 |
TFET with Nanowire Source
App 20140239258 - Bangsaruntip; Sarunya ; et al. | 2014-08-28 |
Nanowire efuses
Grant 8,816,327 - Chang , et al. August 26, 2 | 2014-08-26 |
Methodology For Fabricating Isotropically Recessed Source Regions Of Cmos Transistors
App 20140231809 - Fuller; Nicholas C. ; et al. | 2014-08-21 |
Replacement gate fin first wire last gate all around devices
Grant 8,809,131 - Bangsaruntip , et al. August 19, 2 | 2014-08-19 |
Gate electrode optimized for low voltage operation
Grant 8,802,527 - Frank , et al. August 12, 2 | 2014-08-12 |
Diode Structure and Method for Wire-Last Nanomesh Technologies
App 20140217502 - Chang; Josephine B. ; et al. | 2014-08-07 |
Diode Structure and Method for FINFET Technologies
App 20140217508 - Chang; Josephine B. ; et al. | 2014-08-07 |
Diode Structure and Method for Gate All Around Silicon Nanowire Technologies
App 20140217507 - Chang; Josephine B. ; et al. | 2014-08-07 |
Diode Structure and Method for Gate All Around Silicon Nanowire Technologies
App 20140217509 - Chang; Josephine B. ; et al. | 2014-08-07 |
Diode Structure and Method for Wire-Last Nanomesh Technologies
App 20140217364 - Chang; Josephine B. ; et al. | 2014-08-07 |
Diode Structure and Method for FINFET Technologies
App 20140217506 - Chang; Josephine B. ; et al. | 2014-08-07 |
Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain
Grant 8,796,742 - Chang , et al. August 5, 2 | 2014-08-05 |
Fabrication of a vertical heterojunction tunnel-FET
Grant 8,796,735 - Lauer , et al. August 5, 2 | 2014-08-05 |
Wire-Last Integration Method and Structure for III-V Nanowire Devices
App 20140203290 - Chang; Josephine B. ; et al. | 2014-07-24 |
Wire-Last Integration Method and Structure for III-V Nanowire Devices
App 20140203238 - Chang; Josephine B. ; et al. | 2014-07-24 |
Non-replacement gate nanomesh field effect transistor with pad regions
Grant 8,785,981 - Chang , et al. July 22, 2 | 2014-07-22 |
Gate electrode optimized for low voltage operation
Grant 8,778,759 - Frank , et al. July 15, 2 | 2014-07-15 |
Structure For Self-aligned Silicide Contacts To An Upside-down Fet By Epitaxial Source And Drain
App 20140183637 - COHEN; GUY M. ; et al. | 2014-07-03 |
Tunnel field effect transistor
Grant 8,766,353 - Doris , et al. July 1, 2 | 2014-07-01 |
Lateral Bipolar Transistor And Cmos Hybrid Technology
App 20140170829 - Chang; Josephine B. ; et al. | 2014-06-19 |
Self-aligned borderless contacts for high density electronic and memory device integration
Grant 8,754,530 - Babich , et al. June 17, 2 | 2014-06-17 |
Semiconductor Device Including An Asymmetric Feature, And Method Of Making The Same
App 20140131708 - Chang; Josephine ; et al. | 2014-05-15 |
Nanowire tunnel field effect transistors
Grant 8,723,162 - Bangsaruntip , et al. May 13, 2 | 2014-05-13 |
Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain
Grant 8,716,091 - Cohen , et al. May 6, 2 | 2014-05-06 |
Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors
Grant 8,716,798 - Fuller , et al. May 6, 2 | 2014-05-06 |
Gate-all around semiconductor nanowire FET's on bulk semicoductor wafers
Grant 8,698,128 - Sleight , et al. April 15, 2 | 2014-04-15 |
High performance devices and high density devices on single chip
Grant 8,686,506 - Chang , et al. April 1, 2 | 2014-04-01 |
Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices
Grant 8,673,731 - Chang , et al. March 18, 2 | 2014-03-18 |
Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers
Grant 8,674,342 - Sleight , et al. March 18, 2 | 2014-03-18 |
Lateral Bipolar Transistor And Cmos Hybrid Technology
App 20140073106 - Chang; Josephine B. ; et al. | 2014-03-13 |
Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices
Grant 8,669,167 - Chang , et al. March 11, 2 | 2014-03-11 |
Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices
Grant 8,669,615 - Chang , et al. March 11, 2 | 2014-03-11 |
Techniques For Metal Gate Workfunction Engineering To Enable Multiple Threshold Voltage Finfet Devices
App 20140061796 - Chang; Josephine B. ; et al. | 2014-03-06 |
Techniques For Metal Gate Workfunction Engineering To Enable Multiple Threshold Voltage Finfet Devices
App 20140065802 - Chang; Josephine B. ; et al. | 2014-03-06 |
Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices
Grant 8,659,084 - Chang , et al. February 25, 2 | 2014-02-25 |
Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices
Grant 8,659,006 - Chang , et al. February 25, 2 | 2014-02-25 |
Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices
Grant 8,658,518 - Chang , et al. February 25, 2 | 2014-02-25 |
Techniques For Gate Workfunction Engineering To Reduce Short Channel Effects In Planar Cmos Devices
App 20140051225 - Chang; Josephine B. ; et al. | 2014-02-20 |
Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices
App 20140051213 - Chang; Josephine B. ; et al. | 2014-02-20 |
Techniques For Gate Workfunction Engineering To Reduce Short Channel Effects In Planar Cmos Devices
App 20140048882 - Chang; Josephine B. ; et al. | 2014-02-20 |
Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices
App 20140048773 - Chang; Josephine B. ; et al. | 2014-02-20 |
Embedded Silicon Germanium N-type Filed Effect Transistor For Reduced Floating Body Effect
App 20140038368 - CHANG; Leland ; et al. | 2014-02-06 |
Embedded Silicon Germanium N-type Filed Effect Transistor For Reduced Floating Body Effect
App 20140035037 - CHANG; Leland ; et al. | 2014-02-06 |
Replacement Gate Fin First Wire Last Gate All Around Devices
App 20140021538 - Bangsaruntip; Sarunya ; et al. | 2014-01-23 |
Fin bipolar transistors having self-aligned collector and emitter regions
Grant 8,618,636 - Chang , et al. December 31, 2 | 2013-12-31 |
Fin bipolar transistors having self-aligned collector and emitter regions
Grant 08618636 - | 2013-12-31 |
8-transistor SRAM cell design with inner pass-gate junction diodes
Grant 08619465 - | 2013-12-31 |
Fin bipolar transistors having self-aligned collector and emitter regions
Grant 8,617,957 - Chang , et al. December 31, 2 | 2013-12-31 |
8-transistor SRAM cell design with inner pass-gate junction diodes
Grant 8,619,465 - Chang , et al. December 31, 2 | 2013-12-31 |
V-groove source/drain MOSFET and process for fabricating same
Grant 8,610,181 - Guillorn , et al. December 17, 2 | 2013-12-17 |
V-groove source/drain MOSFET and process for fabricating same
Grant 8,603,868 - Guillorn , et al. December 10, 2 | 2013-12-10 |
Embedded silicon germanium n-type filed effect transistor for reduced floating body effect
Grant 8,597,991 - Chang , et al. December 3, 2 | 2013-12-03 |
Gate-all around semiconductor nanowire FETs on bulk semiconductor wafers
Grant 8,592,295 - Sleight , et al. November 26, 2 | 2013-11-26 |
Device And Method For Forming Sharp Extension Region With Controllable Junction Depth And Lateral Overlap
App 20130264612 - Lauer; Isaac ; et al. | 2013-10-10 |
Device And Method For Forming Sharp Extension Region With Controllable Junction Depth And Lateral Overlap
App 20130264614 - Lauer; Isaac ; et al. | 2013-10-10 |
Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure
App 20130260516 - Chang; Josephine B. ; et al. | 2013-10-03 |
Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure
App 20130256797 - Chang; Josephine B. ; et al. | 2013-10-03 |
Method for fabricating transistor with high-K dielectric sidewall spacer
Grant 8,536,041 - Chang , et al. September 17, 2 | 2013-09-17 |
Replacement spacer for tunnel FETS
Grant 8,530,932 - Chang , et al. September 10, 2 | 2013-09-10 |
8-transistor SRAM cell design with Schottky diodes
Grant 8,531,871 - Chang , et al. September 10, 2 | 2013-09-10 |
8-transistor SRAM cell design with outer pass-gate diodes
Grant 8,526,228 - Chang , et al. September 3, 2 | 2013-09-03 |
Gate-All Around Semiconductor Nanowire FET's On Bulk Semicoductor Wafers
App 20130221319 - Sleight; Jeffrey W. ; et al. | 2013-08-29 |
Pad-Less Gate-All Around Semiconductor Nanowire FETs On Bulk Semiconductor Wafers
App 20130221328 - Sleight; Jeffrey W. ; et al. | 2013-08-29 |
Omega shaped nanowire tunnel field effect transistors
Grant 8,507,892 - Bangsaruntip , et al. August 13, 2 | 2013-08-13 |
Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance
Grant 8,502,325 - Chang , et al. August 6, 2 | 2013-08-06 |
8-transistor Sram Cell Design With Outer Pass-gate Diodes
App 20130176771 - Chang; Leland ; et al. | 2013-07-11 |
8-transistor Sram Cell Design With Inner Pass-gate Junction Diodes
App 20130176770 - Chang; Leland ; et al. | 2013-07-11 |
8-transistor Sram Cell Design With Schottky Diodes
App 20130176769 - Chang; Leland ; et al. | 2013-07-11 |
V-groove Source/drain Mosfet And Process For Fabricating Same
App 20130153971 - Guillorn; Michael A. ; et al. | 2013-06-20 |
V-Groove Source/Drain Mosfet and Process For Fabricating Same
App 20130153972 - GUILLORN; MICHAEL A. ; et al. | 2013-06-20 |
Methodology For Fabricating Isotropically Recessed Drain Regions Of Cmos Transistors
App 20130146965 - Fuller; Nicholas C. ; et al. | 2013-06-13 |
Nanowire Efuses
App 20130109167 - CHANG; JOSEPHINE B. ; et al. | 2013-05-02 |
Nanowire Efuses
App 20130106496 - Chang; Josephine B. ; et al. | 2013-05-02 |
Methodology for fabricating isotropically recessed drain regions of CMOS transistors
Grant 8,431,995 - Fuller , et al. April 30, 2 | 2013-04-30 |
Fabrication Of Field-effect Transistors With Atomic Layer Doping
App 20130032865 - Chan; Kevin K. ; et al. | 2013-02-07 |
Fabrication Of Field-effect Transistors With Atomic Layer Doping
App 20130032883 - Chan; Kevin K. ; et al. | 2013-02-07 |
Embedded silicon germanium n-type filed effect transistor for reduced floating body effect
Grant 8,367,485 - Chang , et al. February 5, 2 | 2013-02-05 |
Semiconductor Device Including An Asymmetric Feature, And Method Of Making The Same
App 20130026465 - Chang; Josephine ; et al. | 2013-01-31 |
Methodology For Fabricating Isotropically Recessed Source And Drain Regions Of Cmos Transistors
App 20130012026 - Fuller; Nicholas C. ; et al. | 2013-01-10 |
TFET with nanowire source
Grant 8,343,815 - Bangsaruntip , et al. January 1, 2 | 2013-01-01 |
High performance devices and high density devices on single chip
Grant 8,338,239 - Chang , et al. December 25, 2 | 2012-12-25 |
Method Of Making A Mosfet Having Self-aligned Silicided Schottky Body Tie Including Intentional Pull-down Of An Sti Exposing Sidewalls Of A Diffusion Region
App 20120313174 - Chang; Leland ; et al. | 2012-12-13 |
Methodology For Fabricating Isotropically Recessed Source Regions Of Cmos Transistors
App 20120305928 - Fuller; Nicholas C. ; et al. | 2012-12-06 |
Graphene/Nanostructure FET with Self-Aligned Contact and Gate
App 20120298949 - Chang; Josephine ; et al. | 2012-11-29 |
Structure For Use In Fabrication Of Pin Heterojunction Tfet
App 20120298963 - Bangsaruntip; Sarunya ; et al. | 2012-11-29 |
High Performance Devices and High Density Devices on Single Chip
App 20120299107 - Chang; Leland ; et al. | 2012-11-29 |
Embedded Silicon Germanium N-type Filed Effect Transistor For Reduced Floating Body Effect
App 20120299062 - CHANG; Leland ; et al. | 2012-11-29 |
Thin Body Silicon-on-insulator Transistor With Borderless Self-aligned Contacts
App 20120299101 - BABICH; Katherina E. ; et al. | 2012-11-29 |
Tunnel Field Effect Transistor
App 20120286350 - Doris; Bruce B. ; et al. | 2012-11-15 |
Method For Fabricating Transistor With High-k Dielectric Sidewall Spacer
App 20120289014 - CHANG; Leland ; et al. | 2012-11-15 |
Nanowire Tunnel Field Effect Transistors
App 20120273761 - Bangsaruntip; Sarunya ; et al. | 2012-11-01 |
Semiconductor Nanowire Structure Reusing Suspension Pads
App 20120256242 - Chang; Josephine B. ; et al. | 2012-10-11 |
Structure With Isotropic Silicon Recess Profile In Nanoscale Dimensions
App 20120193680 - Engelmann; Sebastian Ulrich ; et al. | 2012-08-02 |
Structure With Isotropic Silicon Recess Profile In Nanoscale Dimensions
App 20120193715 - Engelmann; Sebastian Ulrich ; et al. | 2012-08-02 |
Fabrication Of A Vertical Heterojunction Tunnel-fet
App 20120193678 - Lauer; Isaac ; et al. | 2012-08-02 |
Annealing Techniques For High Performance Complementary Metal Oxide Semiconductor (cmos) Device Fabrication
App 20120190216 - Chan; Kevin K. ; et al. | 2012-07-26 |
Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same
App 20120187506 - Chang; Leland ; et al. | 2012-07-26 |
Replacement Spacer For Tunnel Fets
App 20120175678 - Chang; Josephine B. ; et al. | 2012-07-12 |
Omega Shaped Nanowire Tunnel Field Effect Transistors
App 20120138900 - Bangsaruntip; Sarunya ; et al. | 2012-06-07 |
Graphene/Nanostructure FET with Self-Aligned Contact and Gate
App 20110309334 - Chang; Josephine ; et al. | 2011-12-22 |
Fabrication Of A Vertical Heterojunction Tunnel-fet
App 20110303950 - Lauer; Isaac ; et al. | 2011-12-15 |
High Performance Devices and High Density Devices on Single Chip
App 20110284962 - Chang; Leland ; et al. | 2011-11-24 |
Methodology For Fabricating Isotropically Source Regions Of Cmos Transistors
App 20110278580 - Fuller; Nicholas C. ; et al. | 2011-11-17 |
TFET with Nanowire Source
App 20110278542 - Bangsaruntip; Sarunya ; et al. | 2011-11-17 |
Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same
App 20100327376A1 - | 2010-12-30 |
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