U.S. patent application number 15/371366 was filed with the patent office on 2017-03-23 for low-temperature selective epitaxial growth of silicon for device integration.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to BAHMAN HEKMATSHOAR-TABARI, ALI KHAKIFIROOZ, ALEXANDER REZNICEK, DEVENDRA K. SADANA, GHAVAM G. SHAHIDI, DAVOOD SHAHRJERDI.
Application Number | 20170081781 15/371366 |
Document ID | / |
Family ID | 46651684 |
Filed Date | 2017-03-23 |
United States Patent
Application |
20170081781 |
Kind Code |
A1 |
HEKMATSHOAR-TABARI; BAHMAN ;
et al. |
March 23, 2017 |
LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE
INTEGRATION
Abstract
An epitaxy method includes providing an exposed crystalline
region of a substrate material. Silicon is epitaxially deposited on
the substrate material in a low temperature process wherein a
deposition temperature is less than 500 degrees Celsius. A source
gas is diluted with a dilution gas with a gas ratio of dilution gas
to source gas of less than 1000.
Inventors: |
HEKMATSHOAR-TABARI; BAHMAN;
(MOUNT KISCO, NY) ; KHAKIFIROOZ; ALI; (LOS ALTOS,
CA) ; REZNICEK; ALEXANDER; (MOUNT KISCO, NY) ;
SADANA; DEVENDRA K.; (PLEASANTVILLE, NY) ; SHAHIDI;
GHAVAM G.; (POUND RIDGE, NY) ; SHAHRJERDI;
DAVOOD; (OSSINING, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
ARMONK |
NY |
US |
|
|
Family ID: |
46651684 |
Appl. No.: |
15/371366 |
Filed: |
December 7, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14711403 |
May 13, 2015 |
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15371366 |
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13032866 |
Feb 23, 2011 |
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14711403 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
C30B 33/12 20130101;
H01L 21/02584 20130101; C30B 25/183 20130101; C30B 29/06 20130101;
H01L 21/02576 20130101; H01L 21/02395 20130101; H01L 21/02639
20130101; H01L 21/3065 20130101; C30B 25/04 20130101; C30B 25/105
20130101; H01L 21/02381 20130101; H01L 21/02532 20130101; C30B
25/14 20130101; C30B 25/186 20130101; H01L 21/0262 20130101 |
International
Class: |
C30B 25/04 20060101
C30B025/04; C30B 25/14 20060101 C30B025/14; H01L 21/3065 20060101
H01L021/3065; C30B 33/12 20060101 C30B033/12; H01L 21/02 20060101
H01L021/02; C30B 25/18 20060101 C30B025/18; C30B 29/06 20060101
C30B029/06 |
Claims
1. An epitaxy method, comprising: providing a crystalline substrate
material; growing an insulator on the substrate material; opening
the insulator to form exposed areas of the substrate material;
depositing silicon on the exposed areas of the substrate material
to form epitaxial silicon on the exposed areas and form
non-epitaxial silicon in other than the exposed areas in a low
temperature process wherein a deposition temperature is less than
500 degrees Celsius; and etching the non-epitaxial silicon using a
plasma to further epitaxial deposition of silicon over the exposed
areas, wherein the steps of depositing and etching are concurrently
performed.
2. The method as recited in claim 1, wherein depositing silicon
includes a radio frequency or direct current plasma enhanced
chemical vapor deposition process.
3. The method as recited in claim 1, wherein depositing silicon
includes diluting a source gas with a dilution gas including at
least one of H.sub.2, HCl, Cl.sub.2 and Ar with a gas ratio of
dilution gas to source gas of less than 1000, wherein the source
gas includes one of SiH.sub.4, dichlorosilane (DCS), SiF.sub.4 or
SiCl.sub.4.
4. The method as recited in claim 3, wherein diluting include
diluting SiH.sub.4 with at least one of H.sub.2 with a gas ratio of
over 5.
5. The method as recited in claim 1, wherein the deposition
temperature is less than 250 degrees Celsius.
6. The method as recited in claim 1, wherein the substrate material
includes one of Si, Ge, and III-V materials.
7. The method as recited in claim 1, further comprising introducing
a dopant with a gas ratio which provides a doped epitaxial
silicon.
8. The method as recited in claim 7, wherein the doped epitaxial
silicon includes at least one of carbon, germanium, phosphorus,
arsenic or boron.
9. The method as recited in claim 1, wherein the plasma includes at
least one of H.sub.2, HCl, Cl.sub.2 or Ar.
10. An epitaxy method, comprising: providing a crystalline
substrate material; growing an insulator on the substrate material;
opening the insulator to form exposed areas of the substrate
material; and depositing silicon on the exposed areas of the
substrate material to form epitaxial silicon on the exposed areas
areas in a low temperature process wherein a deposition temperature
is less than 500 degrees Celsius concurrently with etching
non-epitaxial silicon using a plasma.
11. The method as recited in claim 10, wherein depositing silicon
includes a radio frequency or direct current plasma enhanced
chemical vapor deposition process.
12. The method as recited in claim 10, wherein depositing silicon
includes diluting a source gas with a dilution gas including at
least one of H.sub.2, HCl, Cl.sub.2 and Ar with a gas ratio of
dilution gas to source gas of less than 1000, wherein the source
gas includes one of SiH.sub.4, dichlorosilane (DCS), SiF.sub.4 or
SiCl.sub.4.
13. The method as recited in claim 12, wherein diluting include
diluting SiH.sub.4 with at least one of H.sub.2 with a gas ratio of
over 5.
14. The method as recited in claim 10, wherein the deposition
temperature is less than 250 degrees Celsius.
15. The method as recited in claim 10, wherein the substrate
material includes one of Si, Ge, and III-V materials.
16. The method as recited in claim 10, further comprising
introducing a dopant with a gas ratio which provides a doped
epitaxial silicon.
17. The method as recited in claim 16, wherein the doped epitaxial
silicon includes at least one of carbon, germanium, phosphorus,
arsenic or boron.
18. The method as recited in claim 10, wherein the plasma includes
at least one of H.sub.2, HCl, Cl.sub.2 or Ar.
19. An epitaxy method, comprising: forming an insulator having an
opening exposing a portion of an underlying crystalline material;
depositing silicon on the exposed areas of the crystalline material
to form epitaxial silicon on the exposed areas and form
non-epitaxial silicon in other than the exposed areas in a low
temperature process wherein a deposition temperature is less than
500 degrees Celsius; and etching the non-epitaxial silicon using a
plasma to further epitaxial deposition of silicon over the exposed
areas, wherein the steps of depositing and etching are concurrently
performed.
20. The epitaxy method of claim 19, wherein the plasma includes at
least one of H.sub.2, HCl, Cl.sub.2 or Ar.
Description
BACKGROUND
[0001] Technical Field
[0002] The present invention relates to semiconductor processing
and more particularly to a low temperature epitaxial growth
process.
[0003] Description of the Related Art
[0004] Selective epitaxial growth (SEG) of highly doped silicon is
suitable for applications in raised source/drain (S/D) regions to
reduce parasitic series resistance associated with shallow-doped
S/D regions. However, conventional methods for SEG of silicon
require high temperature processing. The typical processing
temperatures are greater than 600.degree. C.
[0005] The high temperature requirement limits the processes and
applications which can utilize the conventional methods for SEG of
Si. Further, conventional high temperature depositions (over 600
degrees C.) for epitaxial growth of silicon lack selective growth
of Si on predetermined areas, e.g., where the c-Si is exposed.
SUMMARY
[0006] An epitaxy method includes providing an exposed crystalline
region of a substrate material. Silicon is epitaxially deposited on
the substrate material in a low temperature process wherein a
deposition temperature is less than 500 degrees Celsius. A source
gas is diluted with a dilution gas with a gas ratio of dilution gas
to source gas of less than 1000.
[0007] Another epitaxy method includes providing a crystalline
substrate material; growing an insulator on the substrate material;
opening the insulator to form exposed areas of the substrate
material; depositing silicon on the exposed areas of the substrate
material to form epitaxial silicon on the exposed areas and form
non-epitaxial silicon in other than the exposed areas in a low
temperature process wherein a deposition temperature is less than
500 degrees Celsius; and etching the non-epitaxial silicon using a
plasma to further epitaxial deposition of silicon over the exposed
areas.
[0008] Yet another epitaxy method includes providing an exposed
crystalline region of a substrate material and epitaxially
depositing silicon selectively on the substrate material in a low
temperature process wherein a deposition temperature is less than
500 degrees Celsius, by diluting a silane with a H.sub.2 with a gas
ratio of dilution gas to source gas of less than 1000.
[0009] These and other features and advantages will become apparent
from the following detailed description of illustrative embodiments
thereof, which is to be read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF DRAWINGS
[0010] The disclosure will provide details in the following
description of preferred embodiments with reference to the
following figures wherein:
[0011] FIG. 1 is a cross-sectional view of an illustrative
semiconductor device with raised source/drain regions formed with
selective epitaxial growth in accordance with one embodiment;
[0012] FIG. 2A is a diagram showing sheet resistance versus gas
ratio for [PH.sub.3]/[SiH.sub.4] showing three illustrative samples
in accordance with one embodiment;
[0013] FIG. 2B is a diagram showing atom concentration versus depth
for the three samples of FIG. 2A and further showing a linear
relationship between P concentration and PH.sub.3 flow in
accordance with one example;
[0014] FIG. 3A is a cross-sectional view of a device having a
selective epitaxial layer formed along with a non-epitaxial layer
in a low temperature process in accordance with one embodiment;
[0015] FIG. 3B is a cross-sectional view of the device in FIG. 3A
having the non-epitaxial layer etched to further form the selective
epitaxial layer in accordance with one embodiment;
[0016] FIG. 3C is a cross-sectional view of the device in FIG. 3B
after the non-epitaxial layer has been completely etched in
accordance with one embodiment;
[0017] FIG. 4 is a block/flow diagram showing an illustrative
method for selective epitaxial growth in accordance with the
present principles; and
[0018] FIG. 5 is a block/flow diagram showing another illustrative
method for selective epitaxial growth using etching in accordance
with the present principles.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0019] In accordance with the present principles, methods for
selective epitaxial growth of highly-doped silicon at low
temperatures are disclosed. In particularly useful embodiments,
growth temperatures as low as 150.degree. C. are achieved using
plasma enhanced chemical vapor deposition (PECVD). The epitaxial
growth is obtained by increasing and optimizing a gas ratio of
[H.sub.2]/[SiH.sub.4]. In another embodiment, an N.sup.+ doped
silicon is grown by, e.g., incorporating phosphorus using PH.sub.3
gas.
[0020] High dopant activation, e.g., greater than 1.times.10.sup.20
cm.sup.-3, can be obtained at 150.degree. C. Selective growth is
provided by etching a deposited silicon on regions where
crystalline-Si (c-Si) is not exposed, in H.sub.2 plasma. As a
result, the present embodiments offer an uninterrupted selective
epitaxial growth (SEG) of Si, where the epitaxial growth and the
plasma etching of the non-epitaxial Si occur in a same reactor.
Selective epitaxial growth of boron doped Si or other dopants is
also possible using the present methods.
[0021] The low temperature process in accordance with the present
principles opens up possibilities for many applications such as
three-dimensional (3D) integration of devices, raised source/drain
(S/D) regions for transistors fabricated on extremely thin
semiconductor on insulator (ETSOI), partially-depleted SOI (PDSOI),
bulk silicon substrates, etc. and other applications.
[0022] Plasma enhanced chemical vapor deposition (PECVD) may also
be employed for low-temperature deposition of amorphous,
microcrystalline, polycrystalline as well as epitaxial growth of
silicon on a c-Si substrate at temperatures below 300.degree.
C.
[0023] The flowchart and diagrams in the Figures illustrate the
architecture, functionality, and operation of possible
implementations of various embodiments of the present invention. It
should also be noted that, in some alternative implementations, the
functions noted in the blocks may occur out of the order noted in
the figures. For example, two blocks shown in succession may, in
fact, be executed substantially concurrently, or the blocks may
sometimes be executed in the reverse order, depending upon the
functionality involved. It will also be noted that each block of
the block diagrams and/or flowchart illustrations, and combinations
of blocks in the block diagrams and/or flowchart illustrations, can
be implemented by special purpose hardware-based systems that
perform the specified functions or acts, or combinations of special
purpose hardware and instructions.
[0024] It is to be understood that the present invention will be
described in terms of a given illustrative architecture using
silicon; however, other architectures, structures, substrate
materials and process features and steps may be varied within the
scope of the present invention.
[0025] Devices described herein may be part of a design for an
integrated circuit chip. The chip design may be created in a
graphical computer programming language, and stored in a computer
storage medium (such as a disk, tape, physical hard drive, or
virtual hard drive such as in a storage access network). If the
designer does not fabricate chips or the photolithographic masks
used to fabricate chips, the designer may transmit the resulting
design by physical means (e.g., by providing a copy of the storage
medium storing the design) or electronically (e.g., through the
Internet) to such entities, directly or indirectly. The stored
design is then converted into the appropriate format (e.g., GDSII)
for the fabrication of photolithographic masks, which typically
include multiple copies of the chip design in question that are to
be formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed.
[0026] The methods as described herein may be used in the
fabrication of integrated circuit chips. The resulting integrated
circuit chips can be distributed by the fabricator in raw wafer
form (that is, as a single wafer that has multiple unpackaged
chips), as a bare die, or in a packaged form. In the latter case,
the chip is mounted in a single chip package (such as a plastic
carrier, with leads that are affixed to a motherboard or other
higher level carrier) or in a multichip package (such as a ceramic
carrier that has either or both surface interconnections or buried
interconnections). In any case, the chip is then integrated with
other chips, discrete circuit elements, and/or other signal
processing devices as part of either (a) an intermediate product,
such as a motherboard, or (b) an end product. The end product can
be any product that includes integrated circuit chips, ranging from
toys and other low-end applications to advanced computer products
having a display, a keyboard or other input device, and a central
processor.
[0027] Referring now to the drawings in which like numerals
represent the same or similar elements and initially to FIG. 1, a
device or wafer 100 includes a substrate 102 wherein methods in
accordance with the present principles will be applied. Substrate
102 may include, e.g., a bulk monocrystalline silicon substrate, a
semiconductor-on-insulator (SOI), an extremely thin SOI (ETSOI)
substrate, a partially-depleted SOI (PDSOI) substrate or other
substrates. Other substrates may include Ge, III-V substrates
(e.g., GaAs), etc. In the present embodiment, silicon is a
preferred substrate material for epitaxial growth; however, other
crystalline substrate materials may also be employed in accordance
with the present principles.
[0028] The device 100 may be employed in three-dimensional (3D)
integration applications or other applications where epitaxial
growth is needed to form component layers. In a particularly useful
embodiment, the epitaxial growth is employed to form raised
source/drain (S/D) regions for transistors. The present embodiment
will illustratively describe forming raised S/D regions although
the present principles apply to any epitaxial growth and etching
applications.
[0029] A gate structure 106 is formed including a gate insulator
108 (e.g., an oxide), a gate conductor 110 (e.g., doped
polysilicon), and spacers 112 (e.g., nitride). Other gate
structures and materials may also be employed. FIG. 1
illustratively shows faceted S/D regions 120, although the S/D
regions 120 need not be faceted. S/D regions 120 are formed by
epitaxial growth. The epitaxial growth may include a highly doped
or undoped silicon at temperatures as low as 150 degrees C. on
predetermined areas of the substrate 102. This is preferably where
crystalline silicon (c-Si) is exposed, hence selective epitaxial
growth.
[0030] In one embodiment, the selective epitaxial growth of silicon
is performed in a hydrogen diluted silane environment using a
plasma enhanced chemical vapor deposition process (PECVD). The gas
ratio of hydrogen gas to silane gas ([H.sub.2]/[SiH.sub.4]) at 150
degrees C. is preferably between 0 to about 1000. In particularly
useful embodiments, epitaxially growth of silicon begins at a gas
ratio of about 5-10. The epitaxial Si quality is improved by
increasing the hydrogen dilution, e.g., to 5 or greater.
[0031] Epitaxial silicon can be grown using various gas sources,
e.g., silane (SiH.sub.4), dichlorosilane (DCS), SiF.sub.4,
SiCl.sub.4 or the like. The quality of epitaxial silicon improves
by increasing the dilution of hydrogen using these or other gases.
For higher hydrogen dilution, smoother interfaces were produced
(epitaxial silicon to crystalline silicon) and fewer stacking
faults and other defects were observed.
[0032] Radio-frequency (RF) or direct current (DC) plasma enhanced
chemical vapor deposition (CVD) is preferably performed at
deposition temperature ranges from about room temperature to about
500 degrees C., and preferably from about 150 degrees C. to about
250 degrees C. Plasma power density may range from about 2
mW/cm.sup.2 to about 2000 mW/cm.sup.2. A deposition pressure range
may be from about 10 mtorr to about 5 torr.
[0033] In one embodiment, high dopant activation can be obtained at
temperatures as low as 150 degrees C. This makes the present
methods attractive for applications in 3D integration and raised
S/D fabrications. The epitaxial Si may contain, e.g., carbon,
germanium, phosphorus, arsenic, boron, etc. The low-temperature
epitaxial Si may be grown on different substrates, such as Si, Ge,
and III-Vs. For example, an epitaxial silicon layer was grown by
the present inventors on GaAs at about 200 degrees Celsius in
accordance with the present principles.
[0034] Referring to FIG. 2A, sheet resistivity of phosphorus doped
epitaxial silicon (epi-Si) for various PH.sub.3 gas flows is shown.
Sheet resistivity for .about.40-50 nm thick epi-Si doped for
various PH.sub.3 gas flows indicates a high dopant activation in
silicon. The hydrogen to silane gas ratio was 14. Secondary ion
mass spectroscopy (SIMS) was carried out for the samples denoted as
1, 2, and 3.
[0035] FIG. 2B shows P concentration (atoms/cm.sup.3) versus depth
(nm) for samples 1, 2 and 3. The P concentration is linearly
proportional with PH.sub.3 (see inset 210). A corresponding level
of the electrically active dopants from the sheet resistivity
measurements for the samples 1 and 2 is in agreement with the
actual concentration of dopants given by the SIMS data. The
concentration of the electrically active dopants for the sample 3,
however, is much lower than the total incorporated dopants, evident
from the SIMS analysis of FIG. 2B. The epitaxial growth of silicon
was disrupted by increasing the [PH.sub.3]/[SiH.sub.4] for sample
3, and a non-epitaxial phase of silicon began to grow. Similar
results were obtained for Boron incorporation. It should be
understood that the dopant gas concentration should be maintained
below a threshold gas ratio to avoid a non-crystalline silicon
phase or to provide a non-epitaxial phase, if desired. With respect
to FIG. 2B, the threshold appears to be at about a gas ratio of
[PH.sub.3]/[SiH.sub.4] between about 5-8. Other gases/dopant
processes have other thresholds.
[0036] Referring to FIGS. 3A-3C, in another embodiment, selective
growth of epitaxial silicon 302 on predetermined areas of a
substrate 304 may be obtained by in-situ etching of non-epitaxial
silicon in H.sub.2 plasma 308. An etching process of amorphous
silicon is employed to concurrently form epitaxial silicon on
exposed crystalline silicon areas. It should be understood that the
epitaxial growth and etching may be performed sequentially or
concurrently as needed. In FIG. 3A, a window 312 is opened up
within an insulator (e.g., silicon oxide (SiO.sub.2)) layer 306,
which is formed on substrate 304. Silicon 302 is deposited at,
e.g., 500 mTorr, [H.sub.2]/[SiH.sub.4]=14 and power density of 4
mW/cm.sup.2. As a result, the silicon 302 is epitaxial within the
window areas 312 where the silicon 302 is exposed to c-Si of the
substrate 304. The silicon on the insulator (e.g., oxide) 306 forms
as non-epitaxial (e.g., amorphous) silicon 310.
[0037] In FIG. 3B, a H.sub.2 plasma etch 308 is performed at 150
degrees C. at 900 mtorr, resulting in an etch selectivity of
approximately 1:3 for c-Si 304 with respect to a-Si:H 310. FIG. 3C
shows the selective epitaxial silicon 302 and the non-epitaxial
(amorphous in this case) Si 310 removed. It should be understood
that a non-epitaxial portion (amorphous Si 310) grown on the
insulator 306 can be etched using gases such as, e.g., H.sub.2,
HCl, Cl.sub.2, Ar, etc. The epitaxial deposition and the H.sub.2
plasma etch may be performed sequentially or concurrently in a same
chamber. The selective epitaxial growth can be achieved either by
alternating gas pulses responsible for the epitaxial growth (e.g.,
silane and dopant species) and the etch (plasma etchants, e.g.,
H.sub.2, HCl, etc.) or by simultaneous flow of all the gases.
[0038] Referring to FIG. 4, a method for selective epitaxial growth
is illustratively shown. In block 402, an exposed crystalline
region of a substrate material is provided. This may include
opening up windows in a dielectric layer or patterning a layer on
the substrate. The substrate material may include Si, Ge, III-V
materials, etc.
[0039] In block 404, silicon is epitaxially deposited on the
substrate material in a low temperature process wherein a
deposition temperature is less than 500 degrees Celsius, and
preferably less than 250 degrees Celsius. The process is selective
to exposed areas of the substrate. The process preferably includes
a radio frequency or direct current plasma enhanced chemical vapor
deposition process.
[0040] In block 408, a source gas is diluted with a dilution gas
including at least one of H.sub.2, HCl, Cl.sub.2 and Ar with a gas
ratio of dilution gas to source gas of less than 1000. The source
gas may include one of SiH.sub.4, dichlorosilane (DCS), SiF.sub.4
or SiCl.sub.4. In a particular useful embodiment, SiH.sub.4 is
employed with H.sub.2 with a gas ratio [H.sub.2]/[SiH.sub.4] of
over 5.
[0041] In block 410, a dopant species or multiple dopant species
may be introduced with a gas ratio which provides a doped epitaxial
silicon. The doped epitaxial silicon may include at least one of
carbon, germanium, phosphorus, arsenic or boron.
[0042] Referring to FIG. 5, another method for selective epitaxial
growth is illustratively shown, which employs, e.g., an RF or DC
plasma enhanced chemical vapor deposition process. In block 502, a
crystalline substrate material is provided. The substrate material
may include Si, Ge, III-V materials, etc. In block 504, an oxide or
insulator is grown on the substrate material. In block 506, the
insulator (e.g., oxide) is opened up or patterned to form exposed
areas of the substrate material.
[0043] In block 512, silicon is deposited on the exposed areas of
the substrate material to form epitaxial silicon on the exposed
areas and form non-epitaxial silicon in other than the exposed
areas in a low temperature process (e.g., deposition temperature
less than 500 degrees Celsius, and more preferably less than 250
degrees Celsius). In block 514, silicon deposition includes
diluting a source gas with a dilution gas including at least one of
H.sub.2, HCl, Cl.sub.2 and Ar with a gas ratio of dilution gas to
source gas of less than 1000, wherein the source gas includes one
of SiH.sub.4, dichlorosilane (DCS), SiF.sub.4 or SiCl.sub.4.
[0044] In block 516, the non-epitaxial (e.g., amorphous or
polysilicon) silicon is selectively etched using a plasma, and
further epitaxial deposition of silicon is performed over the
exposed areas. The plasma may include at least one of H.sub.2, HCl,
Cl.sub.2 or Ar.
[0045] In block 518, a dopant species or multiple dopant species
may be introduced with a gas ratio which provides a doped epitaxial
silicon. The doped epitaxial silicon may include at least one of
carbon, germanium, phosphorus, arsenic or boron. In block 520,
selective epitaxial growth is provided by alternating the
depositing and etching steps, or the depositing and etching are
concurrently performed.
[0046] Having described preferred embodiments for ultra
low-temperature selective epitaxial growth of silicon for device
integration (which are intended to be illustrative and not
limiting), it is noted that modifications and variations can be
made by persons skilled in the art in light of the above teachings.
It is therefore to be understood that changes may be made in the
particular embodiments disclosed which are within the scope of the
invention as outlined by the appended claims. Having thus described
aspects of the invention, with the details and particularity
required by the patent laws, what is claimed and desired protected
by Letters Patent is set forth in the appended claims.
* * * * *