U.S. patent application number 15/134037 was filed with the patent office on 2016-08-11 for method for fabricating semiconductor package.
The applicant listed for this patent is Siliconware Precision Industries Co., Ltd.. Invention is credited to Cheng-Chia Chiang, Chu-Chi Hsu, Shu-Huei Huang, Chia-Kai Shih, Lung-Yuan Wang.
Application Number | 20160233205 15/134037 |
Document ID | / |
Family ID | 53521992 |
Filed Date | 2016-08-11 |
United States Patent
Application |
20160233205 |
Kind Code |
A1 |
Wang; Lung-Yuan ; et
al. |
August 11, 2016 |
METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE
Abstract
A method for fabricating a semiconductor package is provided,
which includes the steps of: providing a first substrate having a
plurality of first conductive posts on a surface thereof and
providing a second substrate having a third surface having a chip
disposed thereon and a fourth surface opposite to the third
surface; disposing the first substrate on the third surface of the
second substrate through the first conductive posts; forming an
encapsulant between the first substrate and the second substrate,
wherein the encapsulant has a first surface adjacent to the first
substrate and a second surface opposite to the first surface; and
removing the first substrate, thereby effectively preventing solder
bridging from occurring.
Inventors: |
Wang; Lung-Yuan; (Taichung,
TW) ; Chiang; Cheng-Chia; (Taichung, TW) ;
Hsu; Chu-Chi; (Taichung, TW) ; Shih; Chia-Kai;
(Taichung, TW) ; Huang; Shu-Huei; (Taichung,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Siliconware Precision Industries Co., Ltd. |
Taichung |
|
TW |
|
|
Family ID: |
53521992 |
Appl. No.: |
15/134037 |
Filed: |
April 20, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14309119 |
Jun 19, 2014 |
9343421 |
|
|
15134037 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/48227
20130101; H01L 2224/73204 20130101; H01L 2225/1035 20130101; H01L
2225/1058 20130101; H01L 2924/00014 20130101; H01L 2224/73265
20130101; H01L 24/73 20130101; H01L 2924/00014 20130101; H01L
2224/32145 20130101; H01L 2224/32225 20130101; H01L 2224/48091
20130101; H01L 2224/02331 20130101; H01L 23/3128 20130101; H01L
2224/48091 20130101; H01L 2224/73265 20130101; H01L 2924/15311
20130101; H01L 2224/12105 20130101; H01L 24/96 20130101; H01L
21/568 20130101; H01L 25/50 20130101; H01L 2225/0651 20130101; H01L
2924/181 20130101; H01L 2224/73265 20130101; H01L 23/5389 20130101;
H01L 2225/1041 20130101; H01L 2924/00014 20130101; H01L 2225/06548
20130101; H01L 2924/00014 20130101; H01L 25/105 20130101; H01L
2224/16225 20130101; H01L 2225/06562 20130101; H01L 2225/1023
20130101; H01L 2924/15311 20130101; H01L 2224/45099 20130101; H01L
2224/04105 20130101; H01L 2224/32225 20130101; H01L 2224/48227
20130101; H01L 2924/00012 20130101; H01L 2224/29099 20130101; H01L
2224/32225 20130101; H01L 2224/32145 20130101; H01L 2224/48227
20130101; H01L 2224/48227 20130101; H01L 2224/16225 20130101; H01L
2924/00012 20130101; H01L 2224/16225 20130101; H01L 2924/00014
20130101; H01L 2924/00 20130101; H01L 2924/00012 20130101; H01L
2924/00012 20130101; H01L 2224/73265 20130101; H01L 2224/73204
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2224/13099 20130101; H01L 2224/73204 20130101; H01L 2224/32225
20130101; H01L 24/03 20130101; H01L 2224/0231 20130101; H01L 24/19
20130101; H01L 23/49811 20130101; H01L 2924/181 20130101; H01L
2924/15311 20130101 |
International
Class: |
H01L 25/00 20060101
H01L025/00; H01L 25/10 20060101 H01L025/10; H01L 23/538 20060101
H01L023/538; H01L 23/00 20060101 H01L023/00; H01L 21/56 20060101
H01L021/56; H01L 23/31 20060101 H01L023/31 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 16, 2014 |
TW |
103101561 |
Claims
1. A method for fabricating a semiconductor package, comprising the
steps of: providing a first substrate having a plurality of first
conductive posts on a surface thereof and a second substrate having
a third surface having a chip disposed thereon and a fourth surface
opposite to the third surface, and disposing the first substrate on
the third surface of the second substrate through the first
conductive posts; forming an encapsulant between the first
substrate and the second substrate, wherein the encapsulant has a
first surface adjacent to the first substrate and a second surface
opposite to the first surface; and removing the first
substrate.
2. The method of claim 1, wherein the third surface of the second
substrate further has a plurality of conductive pads that are
correspondingly electrically connected to the first conductive
posts so as for the first substrate to be disposed on the second
substrate.
3. The method of claim 2, wherein a plurality of second conductive
posts are further formed on the conductive pads and correspondingly
electrically connected to the first conductive posts.
4. The method of claim 3, wherein a plurality of conductive
elements are further formed on top ends of the second conductive
posts.
5. The method of claim 1, wherein a plurality of conductive
elements are further formed on top ends of the first conductive
posts.
6. The method of claim 1, wherein the first substrate has a
dielectric layer, a first metal layer and a second metal layer
sequentially stacked, and the first conductive posts are formed on
the second metal layer.
7. The method of claim 6, wherein removing the first substrate
comprises removing the dielectric layer and the first metal layer
first and then removing the second metal layer.
8. The method of claim 1, after removing the first substrate,
further comprising forming an OSP (Organic Solderability
Preservative) layer on the first conductive posts.
9. The method of claim 1, after removing the first substrate,
further comprising forming a plurality of conductive elements on
the fourth surface of the second substrate.
10. The method of claim 1, wherein the second substrate has a first
carrier and an adhesive layer sequentially stacked such that the
first substrate is disposed on the second substrate with the first
conductive posts attached to the adhesive layer, and after the
first substrate is removed, the method further comprises removing
the second substrate so as to form a second redistribution layer on
the second surface of the encapsulant.
11. The method of claim 10, after forming the second redistribution
layer, further comprising forming a plurality of conductive
elements on the second redistribution layer.
12. The method of claim 1, after removing the first substrate,
further comprising forming a first redistribution layer on the
first surface of the encapsulant.
13. The method of claim 12, after forming the first redistribution
layer, further comprising: disposing a second carrier on the first
redistribution layer and removing the second substrate so as to
form a second redistribution layer on the second surface of the
encapsulant; and removing the second carrier.
14-15. (canceled)
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to semiconductor packages and
fabrication methods thereof, and more particularly, to a
semiconductor package and a fabrication method thereof applicable
to package on package (PoP) structures.
[0003] 2. Description of Related Art
[0004] In recent years, to meet the miniaturization requirement of
electronic products, PoP type packages have become an R&D focus
since they facilitate to save planar area of substrates while
maintaining good processing performances.
[0005] FIG. 1 is a schematic cross-sectional view of a conventional
PoP type package. Referring to FIG. 1, a plurality of solder balls
11 are provided to serve as an interconnection structure for
electrically connecting a lower packaging substrate 12 and an upper
packaging substrate 13. However, as the I/O density of the package
increases, if the size of the package does not change, the pitch
between the solder balls 11 must be reduced. As such, solder
bridging easily occurs between the solder balls 11.
[0006] Therefore, there is a need to provide a semiconductor
package and a fabrication method thereof so as to overcome the
above-described drawbacks.
SUMMARY OF THE INVENTION
[0007] In view of the above-described drawbacks, the present
invention provides a method for fabricating a semiconductor
package, which comprises the steps of: providing a first substrate
having a plurality of first conductive posts on a surface thereof
and a second substrate having a third surface having a chip
disposed thereon and a fourth surface opposite to the third
surface, and disposing the first substrate on the third surface of
the second substrate through the first conductive posts; forming an
encapsulant between the first substrate and the second substrate,
wherein the encapsulant has a first surface adjacent to the first
substrate and a second surface opposite to the first surface; and
removing the first substrate.
[0008] In the above-described method, the third surface of the
second substrate can further have a plurality of conductive pads
that are correspondingly electrically connected to the first
conductive posts so as to dispose the first substrate on the second
substrate. The first substrate can have a dielectric layer, a first
metal layer and a second metal layer sequentially stacked, and the
first conductive posts are formed on the second metal layer.
[0009] In the above-described method, removing the first substrate
can comprise removing the dielectric layer and the first metal
layer first and then removing the second metal layer. A plurality
of conductive elements can further be formed on top ends of the
first conductive posts. A plurality of second conductive posts can
further be formed on the conductive pads and correspondingly
electrically connected to the first conductive posts. A plurality
of conductive elements can further be formed on top ends of the
second conductive posts.
[0010] After removing the first substrate, the method can further
comprise forming an OSP (Organic Solderability Preservative) layer
on the first conductive posts. After removing the first substrate,
the method can further comprise forming a plurality of conductive
elements on the fourth surface of the second substrate.
[0011] In the above-described method, the second substrate can have
a first carrier and an adhesive layer sequentially stacked such
that the first substrate is disposed on the second substrate with
the first conductive posts attached to the adhesive layer, and
after removing the first substrate, the method further comprises
removing the second substrate so as to form a second redistribution
layer on the second surface of the encapsulant. After removing the
first substrate, the method can further comprise forming a first
redistribution layer on the first surface of the encapsulant.
[0012] After forming the first redistribution layer, the method can
further comprise: disposing a second carrier on the first
redistribution layer and removing the second substrate so as to
form a second redistribution layer on the second surface of the
encapsulant; and removing the second carrier. After forming the
second redistribution layer, the method can further comprise
forming a plurality of conductive elements on the second
redistribution layer.
[0013] The present invention further provides a semiconductor
package, which comprises: an encapsulant having a first surface and
a second surface opposite to the first surface; a chip embedded in
the encapsulant and exposed from the second surface of the
encapsulant; a plurality of conductive posts formed in the
encapsulant and penetrating the first and second surfaces; a first
redistribution layer formed on the first surface of the encapsulant
and electrically connected to the conductive posts; and a second
redistribution layer formed on the second surface of the
encapsulant and electrically connected to the chip and the
conductive posts.
[0014] The above-described semiconductor package can further
comprise a plurality of conductive elements formed on the second
redistribution layer.
[0015] Therefore, the prevent invention uses conductive posts to
electrically connect upper and lower substrates. Since less space
is consumed by the conductive posts compared with the conventional
solder balls, the present invention meets the fine pitch
requirement and prevents solder bridging from occurring.
BRIEF DESCRIPTION OF DRAWINGS
[0016] FIG. 1 is a schematic cross-sectional view of a conventional
PoP type package;
[0017] FIGS. 2A to 2I are schematic cross-sectional views showing a
method for fabricating a semiconductor package according to a first
embodiment of the present invention and an application example of
the semiconductor package, wherein FIG. 2B' shows another
embodiment of FIG. 2B, FIGS. 2C' and 2C'' show other embodiments of
FIG. 2C and FIG. 2D' shows another embodiment of FIG. 2D; and
[0018] FIGS. 3A to 3K are schematic cross-sectional views showing a
method for fabricating a semiconductor package according to a
second embodiment of the present invention and an application
example of the semiconductor package.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0019] The following illustrative embodiments are provided to
illustrate the disclosure of the present invention, these and other
advantages and effects can be apparent to those in the art after
reading this specification.
[0020] It should be noted that all the drawings are not intended to
limit the present invention. Various modifications and variations
can be made without departing from the spirit of the present
invention. Further, terms such as "first", "second" etc. are merely
for illustrative purposes and should not be construed to limit the
scope of the present invention.
First Embodiment
[0021] FIGS. 2A to 2I are schematic cross-sectional views showing a
method for fabricating a semiconductor package according to a first
embodiment of the present invention and an application example of
the semiconductor package.
[0022] Referring to FIG. 2A, a first substrate 20 is provided,
which has a dielectric layer 201, a first metal layer 202 and a
second metal layer 203 sequentially stacked. The dielectric layer
201 can be made of FR4, the first metal layer 202 can be a copper
layer and the second metal layer 203 can be a copper foil.
[0023] Referring to FIG. 2B, a plurality of first conductive posts
204 are formed on the second metal layer 203 of the first substrate
20. The first conductive posts 204 can be made of copper. In the
present embodiment, a plurality of conductive elements 205 made of
such as a solder material are further formed on top ends of the
first conductive posts 204. In another embodiment, referring to
FIG. 2B', the conductive elements 205 can be omitted.
[0024] Referring to FIG. 2C, a second substrate 21 is provided. The
second substrate 21 can be, for example, a BT substrate, an FR-4
substrate or a ceramic substrate. The second substrate 21 has a
third surface 21a and a fourth surface 21b opposite to the third
surface 21a. A chip 22 is disposed on the third surface 21a.
Further, the third surface 21a has a plurality of conductive pads
211. Further, referring to FIG. 2C', a plurality of second
conductive posts 212 can be formed on the conductive pads 211.
Furthermore, referring to FIG. 2C'', a plurality of conductive
elements 213 made of such as a solder material can be formed on the
second conductive posts 212.
[0025] Referring to FIG. 2D, the first substrate 20 is disposed on
the second substrate 21 by correspondingly electrically connecting
the first conductive posts 204 to the conductive pads 211. In
another embodiment, referring to FIG. 2D', the first conductive
posts 204 are correspondingly electrically connected to the second
conductive posts 212.
[0026] Referring to FIG. 2E, continued from FIG. 2D, an encapsulant
23 is formed between the first substrate 20 and the second
substrate 21. The encapsulant 23 has a first surface 23a adjacent
to the first substrate 20 and a second surface 23b opposite to the
first surface 23a.
[0027] Referring to FIG. 2F, the dielectric layer 201 and the first
metal layer 202 are removed by such as peeling.
[0028] Referring to FIG. 2G, the second metal layer 203 is removed
by such as etching to expose the first conductive posts 204. If
needed, an OSP (Organic Solderability Preservative) layer (not
shown) can be formed on the first conductive posts 204.
[0029] Referring to FIG. 2H, a plurality of conductive elements 24
are formed on the fourth surface 21b of the second substrate 21,
thereby forming a semiconductor package 2.
[0030] Referring to FIG. 2I, an electronic element 25, such as
another semiconductor package or a semiconductor chip, is disposed
on the semiconductor package 2 and electrically connected to the
first conductive posts 204.
Second Embodiment
[0031] FIGS. 3A to 3K are schematic cross-sectional views showing a
method for fabricating a semiconductor package according to a
second embodiment of the present invention and an application
example of the semiconductor package.
[0032] Referring to FIG. 3A, a second substrate 30 is provided,
which has a first carrier 301 and an adhesive layer 302
sequentially stacked. The second substrate 30 has a third surface
30a having at least a chip 22 disposed thereon and a fourth surface
30b opposite to the third surface 30a. The first carrier 301 can be
made of glass or silicon and in a wafer or panel form.
[0033] Referring to FIG. 3B, a first substrate 20 is provided,
which has a dielectric layer 201, a first metal layer 202 and a
second metal layer 203 sequentially stacked. The dielectric layer
201 can be made of FR4, the first metal layer 202 can be a copper
layer and the second metal layer 203 can be a copper foil. A
plurality of first conductive posts 204 are formed on the second
metal layer 203 of the first substrate 20. The first substrate 20
is disposed on the second substrate 20 with the first conductive
posts 204 attached to the adhesive layer 302.
[0034] Referring to FIG. 3C, an encapsulant 23 is formed between
the first substrate 20 and the second substrate 30. The encapsulant
23 has a first surface 23a adjacent to the first substrate 20 and a
second surface 23b opposite to the first surface 23a.
[0035] Referring to FIG. 3D, the dielectric layer 201 and the first
metal layer 202 are removed by such as peeling.
[0036] Referring to FIG. 3E, the second metal layer 203 is removed
by such as etching to expose the first conductive posts 204. If
needed, an OSP layer (not shown) can be formed on the first
conductive posts 204.
[0037] Referring to FIG. 3F, a first redistribution layer 31 is
formed on the first surface 23a of the encapsulant 23.
[0038] Referring to FIG. 3G, the second substrate 30 is
removed.
[0039] Referring to FIG. 3H, if needed, a second carrier 32 is
disposed on the first redistribution layer 31 through an adhesive
layer 33.
[0040] Referring to FIG. 3I, a second redistribution layer 34 is
formed on the second surface 23b.
[0041] Referring to FIG. 3J, a plurality of conductive elements 24
are formed on the second redistribution layer 34, thereby forming a
semiconductor package 3.
[0042] Referring to FIG. 3K, an electronic element 25, such as
another semiconductor package or a semiconductor chip, is disposed
on the semiconductor package 3 and electrically connected to the
first conductive posts 204.
[0043] Referring to FIG. 3J, the present invention further provides
a semiconductor package, which has: an encapsulant 23 having a
first surface 23a and a second surface 23b opposite to the first
surface 23a; a chip 22 embedded in the encapsulant 23 and exposed
from the second surface 23b of the encapsulant 23; a plurality of
first conductive posts 204 formed in the encapsulant 23 and
penetrating the first and second surfaces 23a, 23b; a first
redistribution layer 31 formed on the first surface 23a of the
encapsulant 23 and electrically connected to the first conductive
posts 204; and a second redistribution layer 34 formed on the
second surface 23b of the encapsulant 23 and electrically connected
to the chip 22 and the first conductive posts 204.
[0044] The above-described semiconductor package can further have a
plurality of conductive elements 24 formed on the second
redistribution layer 34.
[0045] According to the present invention, a plurality of
conductive posts are formed to electrically connect upper and lower
substrates and after an encapsulant is formed between the upper and
lower substrates, the upper substrate is removed. Since less space
is consumed by the conductive posts compared with the conventional
solder balls, the present invention meets the fine pitch
requirement and prevents solder bridging from occurring, thereby
improving the product yield.
[0046] The above-described descriptions of the detailed embodiments
are only to illustrate the preferred implementation according to
the present invention, and it is not to limit the scope of the
present invention. Accordingly, all modifications and variations
completed by those with ordinary skill in the art should fall
within the scope of present invention defined by the appended
claims.
* * * * *