U.S. patent application number 14/588337 was filed with the patent office on 2016-06-30 for vertical gate all-around transistor.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.. Invention is credited to Lawrence A. CLEVENGER, Carl RADENS, Yiheng XU, John H. ZHANG.
Application Number | 20160190312 14/588337 |
Document ID | / |
Family ID | 56165197 |
Filed Date | 2016-06-30 |
United States Patent
Application |
20160190312 |
Kind Code |
A1 |
ZHANG; John H. ; et
al. |
June 30, 2016 |
VERTICAL GATE ALL-AROUND TRANSISTOR
Abstract
Vertical GAA FET structures are disclosed in which a
current-carrying nanowire is oriented substantially perpendicular
to the surface of a silicon substrate. The vertical GAA FET is
intended to meet design and performance criteria for the 7 nm
technology generation. In some embodiments, electrical contacts to
the drain and gate terminals of the vertically oriented GAA FET can
be made via the backside of the substrate. Examples are disclosed
in which various n-type and p-type transistor designs have
different contact configurations. In one example, a backside gate
contact extends through the isolation region between adjacent
devices. Other embodiments feature dual gate contacts for circuit
design flexibility. The different contact configurations can be
used to adjust metal pattern density.
Inventors: |
ZHANG; John H.; (Altamont,
NY) ; RADENS; Carl; (LaGrangeville, NY) ;
CLEVENGER; Lawrence A.; (LaGrangeville, NY) ; XU;
Yiheng; (Hopewell Junction, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMICROELECTRONICS, INC.
INTERNATIONAL BUSINESS MACHINES CORPORATION |
Coppell
Armonk |
TX
NY |
US
US |
|
|
Family ID: |
56165197 |
Appl. No.: |
14/588337 |
Filed: |
December 31, 2014 |
Current U.S.
Class: |
257/192 ;
257/329; 438/268 |
Current CPC
Class: |
H01L 29/165 20130101;
H01L 29/66666 20130101; H01L 29/7827 20130101; H01L 21/823885
20130101; H01L 27/092 20130101; H01L 21/823871 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/16 20060101 H01L029/16; H01L 21/28 20060101
H01L021/28; H01L 29/267 20060101 H01L029/267; H01L 27/092 20060101
H01L027/092; H01L 29/66 20060101 H01L029/66; H01L 29/423 20060101
H01L029/423; H01L 29/165 20060101 H01L029/165 |
Claims
1. A vertical field effect transistor, comprising: a silicon
substrate having a front surface and a back surface; an epitaxial
source region; an epitaxial drain region; a channel located between
the source region and the drain region, the channel having a
channel axis that is oriented transverse to the front surface of
the substrate; a gate that wraps around the channel, the gate
configured to control current flow in the channel; a low-k
encapsulant, overlying and in contact with the gate; and one or
more electrical contacts accessible from the back surface of the
substrate.
2. An n-type transistor according to claim 1 wherein the epitaxial
source region is made of indium-doped silicon.
3. A p-type transistor according to claim 1 wherein the epitaxial
source region is made of silicon germanium.
4. The transistor of claim 1 wherein the channel includes a
multi-layer work function material including one or more of
titanium, tungsten, titanium nitride, and titanium carbide, the
channel having a channel length in the range of about 1-100 nm.
5. The transistor of claim 1 wherein the channel includes a III-V
semiconductor material.
6. The transistor of claim 1 wherein the low-k encapsulant includes
one or more of the silicon compounds SiOCN and SiBCN.
7. The transistor of claim 1 wherein the low-k encapsulant has a
thickness in the range of about 8-30 nm.
8. The transistor of claim 1 wherein a metal density associated
with electrical contacts accessible from the back surface of the
substrate is balanced by an approximately equal metal density
associated with electrical contacts accessible from the front
surface of the substrate.
9. A CMOS device, comprising: a vertical n-type gate-all-around
transistor having a front side gate contact and a back side source
contact; and a vertical p-type gate-all-around transistor having a
back side gate contact and a back side source contact.
10. The device of claim 9 wherein the backside gate contact passes
through an isolation region.
11. A CMOS device, comprising: a vertical n-type gate-all-around
transistor having dual front side gate contacts and a back side
source contact; and a vertical p-type gate-all-around transistor
having dual back side gate contacts and a back side source
contact.
12. The device of claim 11 wherein the dual backside gate contacts
pass through respective isolation regions.
13. A CMOS device, comprising: a vertical n-type gate-all-around
transistor having a front side gate contact and a back side source
contact; and a vertical p-type gate-all-around transistor having a
front side gate contact and a back side source contact.
14. A CMOS device, comprising: a vertical n-type gate-all-around
transistor having dual front side gate contacts, a back side gate
contact, and a back side source contact; and a vertical p-type
gate-all-around transistor having a front side gate contact, a back
side gate contact, and a back side source contact.
15. The device of claim 14 wherein the backside gate contacts pass
through respective isolation regions.
16. A method of making a transistor, the method comprising: forming
isolation regions in a silicon substrate; forming a doped drain
region in the silicon substrate by ion implantation; forming an
insulating layer on top of the doped drain region; depositing a
thick polymer coating; forming openings in the insulating layer and
the thick polymer coating to expose a portion of the drain region;
forming a vertical channel and a source region by epitaxial growth
of a semiconducting nanowire from the exposed drain region; forming
a gate structure surrounding the semiconducting nanowire; recessing
the thick polymer coating and the gate structure to reveal the
source region; and removing the thick polymer coating.
17. The method of claim 16, further comprising: encapsulating the
gate structure and the nanowire; and filling non-encapsulated
regions with an inter-layer dielectric material.
18. The method of claim 16 wherein the polymer coating is made of
benzocyclobutene.
19. A method of making a transistor, the method comprising: forming
isolation regions in a silicon substrate; forming a doped drain
region in the silicon substrate by ion implantation; forming an
insulating layer on top of the doped drain region; forming an
opening in the insulating layer to expose a portion of the drain
region; forming a vertical channel and a source region by selective
epitaxial growth of a semiconducting nanowire from the exposed
drain region; and forming a gate structure surrounding the vertical
channel of the semiconducting nanowire;
20. The method of claim 19, further comprising: encapsulating the
gate structure and the nanowire; and filling non-encapsulated
regions with an inter-layer dielectric material.
21. The method of claim 19 wherein forming the gate structure
entails use of a polymer coating made of benzocyclobutene.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The present disclosure generally relates to various
geometries for gate all-around transistor devices built on a
silicon substrate and, in particular, to vertically oriented gate
all-around transistors in which current flows in a direction
transverse to the surface of the silicon substrate.
[0003] 2. Description of the Related Art
[0004] Conventional integrated circuits incorporate planar field
effect transistors (FETs) in which current flows through a
semiconducting channel between a source and a drain, in response to
a voltage applied to a control gate. The semiconductor industry
strives to obey Moore's law, which holds that each successive
generation of integrated circuit devices shrinks to half its size
and operates twice as fast. As device dimensions have shrunk below
100 nm, however, conventional silicon device geometries and
materials have experienced difficulty maintaining switching speeds
without incurring failures such as, for example, leaking current
from the device into the semiconductor substrate. Several new
technologies emerged that allowed chip designers to continue
shrinking gate lengths to 45 nm, 22 nm, and then as low as 14 nm.
One particularly radical technology change entailed re-designing
the structure of the FET from a planar device to a
three-dimensional device in which the semiconducting channel was
replaced by a fin that extends out from the plane of the substrate.
In such a device, commonly referred to as a FinFET, the control
gate wraps around three sides of the fin so as to influence current
flow from three surfaces instead of one. The improved control
achieved with a 3-D design results in faster switching performance
and reduced current leakage. Building taller devices has also
permitted increasing the device density within the same footprint
that had previously been occupied by a planar FET. Examples of
FinFET devices are described in further detail in U.S. Pat. No.
8,759,874 and U.S. Patent Application Publication US2014/0175554,
assigned to the same assignee as the present patent
application.
[0005] The FinFET concept was further extended by developing a gate
all-around FET, or GAA FET, in which the gate fully wraps around
the channel for maximum control of the current flow therein. In the
GAA FET, the channel can take the form of a cylindrical nanowire
that is isolated from the substrate, in contrast to the peninsular
fin. In the GAA FET the cylindrical nanowire is surrounded by the
gate oxide, and then by the gate. Existing GAA FETs are oriented
horizontally, such that the nanowire extends in a direction that is
substantially parallel to the surface of the semiconductor
substrate. GAA FETs are described in, for example, U.S. Patent
Application Publication No. 2013/0341596 to Chang et al., of IBM
and in U.S. patent application Ser. No. 14/312,418, assigned to the
same assignee as the present patent application.
BRIEF SUMMARY
[0006] Vertical GAA FET structures are disclosed in which a
current-carrying nanowire is oriented substantially perpendicular
to the surface of a silicon substrate. The vertical GAA FET is
intended to meet design and performance criteria for the 7 nm
technology generation. In some embodiments, electrical contacts to
the drain and gate terminals of the vertically oriented GAA FET can
be made via the backside of the substrate. Examples are disclosed
in which various n-type and p-type transistor designs have
different contact configurations. In one example, a backside gate
contact extends through the isolation region between adjacent
devices. Other embodiments feature dual gate contacts for circuit
design flexibility. The different contact configurations can be
used to adjust metal pattern density.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0007] In the drawings, identical reference numbers identify
similar elements or acts. The sizes and relative positions of
elements in the drawings are not necessarily drawn to scale.
[0008] FIG. 1 is a cross-sectional view of n-type and p-type
vertical gate-all-around (GAA) transistors, according to one
embodiment described herein.
[0009] FIGS. 2-4 are cross-sectional views of alternative
embodiments of the vertical GAA transistors shown in FIG. 1,
wherein each embodiment has a different gate contact configuration,
as described herein
[0010] FIG. 5 is a flow diagram summarizing a sequence of
processing steps that can be used to fabricate the vertical GAA
transistors shown in FIGS. 1-4, according to a first exemplary
embodiment described herein.
[0011] FIGS. 6-9 are cross-sectional views of the vertical GAA
transistor configuration shown in FIG. 1, at various steps during
the processing sequence shown in FIG. 5.
[0012] FIG. 10 is a cross-sectional view of completed n-type and
p-type vertical gate-all-around (GAA) transistors having the gate
contact configuration shown in FIG. 1, according to one embodiment
described herein.
[0013] FIG. 11 is a flow diagram summarizing a sequence of
processing steps that can be used to fabricate the vertical GAA
transistors shown in FIGS. 1-4, according to a second exemplary
embodiment described herein.
DETAILED DESCRIPTION
[0014] In the following description, certain specific details are
set forth in order to provide a thorough understanding of various
aspects of the disclosed subject matter. However, the disclosed
subject matter may be practiced without these specific details. In
some instances, well-known structures and methods of semiconductor
processing comprising embodiments of the subject matter disclosed
herein have not been described in detail to avoid obscuring the
descriptions of other aspects of the present disclosure.
[0015] Unless the context requires otherwise, throughout the
specification and claims that follow, the word "comprise" and
variations thereof, such as "comprises" and "comprising" are to be
construed in an open, inclusive sense, that is, as "including, but
not limited to."
[0016] Reference throughout the specification to "one embodiment"
or "an embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment. Thus, the appearance of the
phrases "in one embodiment" or "in an embodiment" in various places
throughout the specification are not necessarily all referring to
the same aspect. Furthermore, the particular features, structures,
or characteristics may be combined in any suitable manner in one or
more aspects of the present disclosure.
[0017] Reference throughout the specification to integrated
circuits is generally intended to include integrated circuit
components built on semiconducting substrates, whether or not the
components are coupled together into a circuit or able to be
interconnected. Throughout the specification, the term "layer" is
used in its broadest sense to include a thin film, a cap, or the
like and one layer may be composed of multiple sub-layers.
[0018] Reference throughout the specification to conventional thin
film deposition techniques for depositing silicon nitride, silicon
dioxide, metals, or similar materials include such processes as
chemical vapor deposition (CVD), low-pressure chemical vapor
deposition (LPCVD), metal organic chemical vapor deposition
(MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma
vapor deposition (PVD), atomic layer deposition (ALD), molecular
beam epitaxy (MBE), electroplating, electro-less plating, and the
like. Specific embodiments are described herein with reference to
examples of such processes. However, the present disclosure and the
reference to certain deposition techniques should not be limited to
those described. For example, in some circumstances, a description
that references CVD may alternatively be done using PVD, or a
description that specifies electroplating may alternatively be
accomplished using electro-less plating. Furthermore, reference to
conventional techniques of thin film formation may include growing
a film in-situ. For example, in some embodiments, controlled growth
of an oxide to a desired thickness can be achieved by exposing a
silicon surface to oxygen gas or to moisture in a heated
chamber.
[0019] Reference throughout the specification to conventional
photolithography techniques, known in the art of semiconductor
fabrication for patterning various thin films, includes a
spin-expose-develop process sequence typically followed by an etch
process. Alternatively or additionally, photoresist can also be
used to pattern a hard mask (e.g., a silicon nitride hard mask),
which, in turn, can be used to pattern an underlying film.
[0020] Reference throughout the specification to conventional
etching techniques known in the art of semiconductor fabrication
for selective removal of polysilicon, silicon nitride, silicon
dioxide, metals, photoresist, polyimide, or similar materials
includes such processes as wet chemical etching, reactive ion
(plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray
cleaning, chemical-mechanical planarization (CMP) and the like.
Specific embodiments are described herein with reference to
examples of such processes. However, the present disclosure and the
reference to certain deposition techniques should not be limited to
those described. In some instances, two such techniques may be
interchangeable. For example, stripping photoresist may entail
immersing a sample in a wet chemical bath or, alternatively,
spraying wet chemicals directly onto the sample.
[0021] Specific embodiments are described herein with reference to
vertical gate-all-around devices that have been produced; however,
the present disclosure and the reference to certain materials,
dimensions, and the details and ordering of processing steps are
exemplary and should not be limited to those shown.
[0022] Turning now to the figures, FIGS. 1-4 show various different
embodiments of vertical GAA transistors. FIG. 1 shows CMOS n-type
and p-type vertical gate all-around (GAA) transistors, an n-FET
device 100 and a p-FET device 101, respectively, built on a silicon
substrate 102, according to one embodiment described herein. Each
one of the vertical GAA transistors is essentially a linear, or 1-D
device in the form of a nanowire 104 oriented in a direction
transverse to planar front and back surfaces of the silicon
substrate 102. Two such nanowires are shown in FIGS. 1, 104n and
104p. The nanowire 104n is the channel region of the n-FET device
100 and the nanowire 104p is the channel region of the p-FET device
101. The nanowire 104n includes a silicon channel 106n that couples
an N+ drain 105n located below the channel 106n to an N+ source
107n located above the channel 106n along a channel axis 108; the
nanowire 104p includes a SiGe channel 106p that couples a P+ drain
105p below the channel 106p to a P+ source 107p above the channel
106p. Alternatively, one or both channels can be made of a III-V
semiconducting material such as InAs, as suggested by Ionescu and
Riel in "Tunnel Field-Effect Transistors as Energy-Efficient
Electronic Switches," [Nature, Vol. 479, November 17, 201, p. 379].
The vertical nanowire 104 desirably has a diameter in the range of
6-10 nm.
[0023] The n-type material in the source and drain of the n-FET
device 100 can be, for example, epitaxially grown indium-doped
silicon. The p-type material in the source and drain of the p-FET
device 101 can be, for example, epitaxially grown SiGe. In one
embodiment the channel length can be as long as 100 nm. A long
channel length having an aspect ratio in the range of about
4:1-10:1 provides a high gate contact area to maintain low
resistance contacts. Backside nanowire contacts 110n and 110p are
also shown in FIG. 1, along with front side nanowire contacts 112n
and 112p.
[0024] Metal gates 114 wrap around each of the nanowires 104. In
one embodiment, the metal gates 114 include a stack of work
function materials. For example, the metal gate for the n-FET
device 100 is a three-layer stack that includes a 4-nm thick layer
of titanium carbide (TiC) sandwiched between two 3-nm layers of
titanium nitride (TiN). The metal stack for the p-FET device 101 is
a three-layer stack of TiN that yields a total thickness of about
10 nm. The metal gates 114 are spaced apart from the channel by a
wrap-around gate dielectric 115 made of a high-k material, e.g.,
HfO.sub.2. The n-FET has a front side gate contact 116n and the
p-FET has a backside gate contact 116p. Each contact contains a
bulk metal and a liner, as is customary in the art. The gate
contacts 116 are isolated from the source regions by a thick hard
mask 117 made of silicon nitride (SiN) or silicon carbide
(SiC).
[0025] The transistors 100 and 101 are separated by an isolation
region 118 that is filled with an insulator, e.g., an oxide
material with a silicon nitride liner. The backside gate contact
116p passes through the isolation region 118.
[0026] Finally, the nanowires 104 are covered by a low-k
encapsulant 120, which is, in turn, covered, by an insulating
material 122. In one embodiment, the low-k encapsulant 120 is made
of SiOCN or SiBCN, having a thickness in the range of about 8-30
nm.
[0027] Comparing FIGS. 1-4, it becomes apparent that the different
embodiments shown present alternative contact arrangements to the
two nanowire devices, and in particular, alternative gate contact
arrangements. The nanowires 104 and the geometries of the
source/drain contacts 110 and 112 are substantially the same
throughout FIGS. 1-4. However, the structure and placement of the
various gate contacts 116 differs. For example, in FIG. 1, each
device has a single gate contact, wherein the n-FET gate is
accessible from the front side of the silicon, while the p-FET gate
contact is accessible from the back side. Whereas, in the
arrangement 102 shown in FIG. 2, each nanowire has a dual gate
contact. For example, the n-FET gate 114n is accessible via two
front side gate contacts 116n, while the p-FET gate 114p is
accessible via two back side gate contacts 116p, each of which is
disposed in an isolation region 118. A symmetric contact design in
which an equal number of connections is made on the top side and
the back side of the silicon maintains a balanced metal line
pattern density. Maintaining consistent pattern density facilitates
processes that are particularly sensitive to pattern uniformity
such as photolithography and planarization processes. Another
advantage of using back side contacts is that they can be large
compared with front side contacts, for example 10-100 nm or larger,
and can thus serve as heat sinks.
[0028] In FIG. 3, each transistor gate 114 is accessible by a
single front side gate contact 116.
[0029] In FIG. 4, each transistor gate 114 is accessible by both a
front side gate contact 116 and a backside gate contact 116. In
addition, the n-FET has a dual front-side contact 116n. Providing
more than one gate contact is helpful in the design of Boolean
logic circuit applications, for example.
[0030] FIG. 5 shows steps in a method 200 of fabricating the
vertical GAA transistors shown in FIG. 1, as an example. The method
shown in FIG. 5 is further illustrated by FIGS. 6-10, and described
below. The exemplary method 200 uses a technique that entails
coating and removal of a sacrificial polymer material, for example,
benzocyclobutene (BCB). An alternative method of fabrication may
use a method known as inlay banding.
[0031] At 201, isolation regions are formed in the substrate 202 as
shown in FIG. 6 by known methods.
[0032] At 202, drain regions are formed in the substrate 102, as
shown in FIG. 6 by, for example, implant doping, in the usual way.
The N+ concentration, typically boron, is desirably in the range of
about 1E16-3E20 cm.sup.-3, with a target concentration of 2E19
cm.sup.-3. The P+ concentration, typically arsenic or phosphorous,
is desirably in the range of about 1E16-5E20 cm.sup.-3, with a
target concentration of 5E19 cm.sup.-3.
[0033] At 203, following an anneal step to drive the dopants to a
desired depth, the insulating layer 117 is formed.
[0034] At 204, a first thick coating of the polymer BCB 150 is
applied.
[0035] At 206, the BCB 150 is patterned using a reactive ion etch
(RIE) process to form trenches for the nanowires 104. The trenches
diameter is in the range of about 2-200 nm and the trench height is
in the range of about 8-800 nm.
[0036] At 208, the channels 106 and then the source regions are
formed by epitaxial growth within the high aspect ratio trenches,
as shown in FIG. 6. The n-FET channel can be formed of silicon or
indium arsenide (InAs), and the p-FET channel is formed of SiGe.
The source regions can be formed by in-situ doping during
epitaxy.
[0037] At 210, the metal gates 114n and 114p are formed, as shown
in FIG. 7. First, a gate trench is formed using an RIE process that
stops on the silicon nitride (SiN) layer 117. Then, the gate
trenches are filled with the high-k wrap-around gate dielectric
115, a metal liner, one or more work function metals as discussed
above, and then the metal gates 114 are polished to stop on the BCB
150.
[0038] At 212 The BCB 150 and the metal gates 114n and 114p are
recessed, by selective etching, to reveal the source regions 107n
and 107p.
[0039] At 214, the BCB 150 is removed, as shown in FIG. 8. In
addition, the high-k dielectric material 115 on the outsides of the
metal gates 114 is removed. Some high-k material may remain on the
exposed source regions 107.
[0040] At 216, the devices are encapsulated with the low-k
encapsulant 120 for capacitance reduction.
[0041] At 218, inter-device regions are filled with the inter-layer
dielectric (ILD) 122, and the ILD 122 is then planarized to stop on
the low-k encapsulant 120, as shown in FIG. 9.
[0042] Opening contacts to the source, drain, and gate terminals of
the n-FET and p-FET devices then produces the structure shown in
FIG. 10, which is a reproduction of FIG. 1, or alternatively, the
structures shown in FIGS. 2-4, which have different gate contact
arrangements. The vertical geometry of the GAA transistors this
formed allows flexibility in circuit design because it is possible
to access the devices from different front side and back side
locations by simply changing the contact configuration. For
example, the NFET gate contact can extend from the front side,
while the PFET gate contact can extend from the back side, or vice
versa. One or more gate contacts can pass through isolation regions
118 for an even more compact design, as shown in FIGS. 1, 2, and
4.
[0043] An alternative method 300 of fabricating the vertical GAA
devices shown in FIGS. 1-4 is shown in FIG. 11, in accordance with
methods described in a manuscript by Bjork et al. in "Si--InAs
Heterojunction Esaki Tunnel Diodes with High Current Densities".
Steps 302-306 of the method 300 are the same as steps 201-203 of
FIG. 5.
[0044] Then, at 308-310, instead of forming trenches in a layer of
BCB 150 and filling the trenches to form the nanowires 104, the
drain regions are exposed at 308, and then at 310 vertical
nanowires 104 are selectively grown from the drain regions 105. In
one example, after opening the SiN layer 117 to expose the drain
regions, selective nanowire growth is performed in an MOCVD system
at 400-600 C and a reactor pressure of 60 Torr, using a
trimethyl-indium (TMIn) and a tertiarybutyl-arsine molar flow of
0.7 .mu.Mol/min and 12.6 .mu.Mol/min, respectively to create InAs
nanowires. Doping of the InAs is achieved by injecting disilane
(Si.sub.2H.sub.6) during growth at Si.sub.2H.sub.6/TMIn ratios of
1E-6 to 1E-2.
[0045] At 312, once the nanowires 104 are in place, the metal gates
114 are formed by depositing the gate stack, including the high-k
dielectric, the metal liner, the work function material, and the
bulk metal gate layer, conformally over the nanowires 104, and
etching away portions outside a desired radius from the nanowires
104. A BCB layer can then be used to mask the gate structure around
the channel portions of the nanowires 104 while selectively etching
gate stack material from the source region portions of the
nanowires 104.
[0046] Steps 314-316 of the method 300 are the same as steps
216-218 of the method 200 described above.
[0047] It will be appreciated that, although specific embodiments
of the present disclosure are described herein for purposes of
illustration, various modifications may be made without departing
from the spirit and scope of the present disclosure. Accordingly,
the present disclosure is not limited except as by the appended
claims.
[0048] These and other changes can be made to the embodiments in
light of the above-detailed description. In general, in the
following claims, the terms used should not be construed to limit
the claims to the specific embodiments disclosed in the
specification and the claims, but should be construed to include
all possible embodiments along with the full scope of equivalents
to which such claims are entitled. Accordingly, the claims are not
limited by the disclosure.
[0049] The various embodiments described above can be combined to
provide further embodiments. All of the U.S. patents, U.S. patent
application publications, U.S. patent applications, foreign
patents, foreign patent applications and non-patent publications
referred to in this specification and/or listed in the Application
Data Sheet are incorporated herein by reference, in their entirety.
Aspects of the embodiments can be modified, if necessary to employ
concepts of the various patents, applications and publications to
provide yet further embodiments.
* * * * *